Integrated Device Technology, Inc. 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS FEATURES: IDT74FCT163601/A ADVANCE INFORMATION universal bus transceivers combine D-type latches and Dtype flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-toB data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The FCT163601 has series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors. • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP • Extended commercial range of -40°C to +85°C • VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range • CMOS power levels (0.4µW typ. static) • Rail-to-Rail output swing for increased noise margin • Low Ground Bounce (0.3V typ.) • Inputs (except I/O) can be driven by 3.3V or 5V components DESCRIPTION: The FCT163601/A 18-bit registered transceiver is built using advanced dual metal CMOS technology. These 18-bit FUNCTIONAL BLOCK DIAGRAM OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA A1 1 56 55 2 28 30 29 27 CE 1D C1 CLK 3 54 B1 CE 1D C1 CLK TO 17 OTHER CHANNELS 3251 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. AUGUST 1996 5.9 DSC-3251/1 1 IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance OEAB 1 56 CLKENAB LEAB 2 55 CLKAB A1 3 54 B1 GND 4 53 GND A2 5 52 B2 A3 6 51 B3 VCC 7 50 VCC A4 8 49 B4 A5 9 48 B5 A6 10 47 B6 GND 11 46 GND A7 12 45 B7 A8 13 44 B8 A9 14 B9 A10 15 SO56-1 43 SO56-2 SO56-3 42 A11 16 41 B11 A12 17 40 B12 GND 18 39 GND A13 19 38 B13 A14 20 37 B14 A15 21 36 B15 VCC 22 35 VCC A16 23 34 B16 A17 24 33 B17 CLKENAB GND 25 32 GND X A18 26 31 B18 Conditions VIN = 0V Typ. 3.5 VOUT = 0V 3.5 Max. Unit 6.0 pF 8.0 NOTE: 1. This parameter is measured at characterization but not tested. pF 3251 lnk 04 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) TSTG Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature I OUT DC Output Current VTERM(3) VTERM(4) B10 Max. –0.5 to +4.6 Unit V –0.5 to +7.0 V –0.5 to VCC + 0.5 –65 to +150 V °C –60 to +60 mA 3251 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals. FUNCTION TABLE(1,4) OEAB Inputs LEAB CLKAB A Outputs B H X X X Z X L H X L L L H X H H X B0(2) OEBA 27 30 CLKBA X LEBA 28 29 CLKENBA H L L X L L L ↑ L L L L L ↑ H H L L L L X B0(2) L L L H X B0(3) SSOP TSSOP/TVSOP TOP VIEW 3251 drw 02 PIN DESCRIPTION Pin Names OEAB OEBA Description B-to-A Output Enable Input (Active LOW) LEAB A-to-B Latch Enable Input LEBA B-to-A Latch Enable Input CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input Ax A-to-B Data Inputs or B-to-A 3-State Outputs Bx B-to-A Data Inputs or A-to-B 3-State Outputs CLKENAB CLKENBA NOTES: 3251 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA and CLKENBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance ↑ = LOW-to-HIGH Transition A-to-B Output Enable Input (Active LOW) A to B Clock Enable Input (Active LOW) B to A Clock Enable Input (Active LOW) 3251 tbl 01 5.9 2 IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V Symbol VIH Parameter Input HIGH Level (Input pins) Test Conditions(1) Guaranteed Logic HIGH Level Input HIGH Level (I/O pins) VIL Input LOW Level Guaranteed Logic LOW Level Min. 2.0 Typ.(2) — Max. 5.5 2.0 — VCC+0.5 –0.5 — 0.8 V — — ±1 µA Unit V (Input and I/O pins) II H II L Input HIGH Current (Input pins) VI = 5.5V Input HIGH Current (I/O pins) VI = VCC — — ±1 Input LOW Current (Input pins) VI = GND — — ±1 Input LOW Current (I/O pins) VI = GND — — ±1 VO = V CC — — ±1 VO = GND — — ±1 — –0.7 –1.2 V –36 –60 –110 mA I OZH High Impedance Output Current I OZL (3-State Output pins) VIK Clamp Diode Voltage I ODH VCC = Max. Output HIGH Current VCC = Max. VCC = Min., IIN = –18mA VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3) 1.5V(3) I ODL Output LOW Current VCC = 3.3V, V IN = VIH or VIL, VO = VOH Output HIGH Voltage VCC = Min. I OH = –0.1mA VIN = VIH or V IL VOL Output LOW Voltage I OS Short Circuit Current(4) VH Input Hysteresis I CCL I CCH I CCZ Quiescent Power Supply Current µA 50 90 200 mA VCC– 0.2 — — V I OH = –3mA 2.4 3.0 — VCC = 3.0V VIN = VIH or V IL VCC = Min. I OH = –8mA 2.4 (5) 3.0 — I OL = 0.1mA — — 0.2 VIN = VIH or V IL I OL = 16mA — 0.2 0.4 I OL = 24mA — 0.3 0.55 VCC = 3.0V I OL = 24mA VIN = VIH or V IL VCC = Max., VO = GND(3) — 0.3 0.50 –60 –135 –240 mA — 150 — mV — 0.1 10 µA — VCC = Max., VIN = GND or VCC NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC –0.6V at rated current. 5.9 V 3251 lnk 05 3 IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol Parameter ∆ICC Quiescent Power Supply Current TTL Inputs HIGH ICCD Dynamic Power Supply Current(4) Test Conditions(1) Min. Typ.(2) Max. Unit — 2.0 30 µA VIN = VCC VIN = GND — 60 100 µA/ MHz VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEBA = GND CLKENBA = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VIN = VCC VIN = GND — 0.6 1.0 mA VIN = VCC –0.6 VIN = GND — 0.6 1.0 VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEBA = GND CLKENBA = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND — 3.0 5.0(5) VIN = VCC –0.6 VIN = GND — 3.0 5.3(5) VCC = Max. VIN = VCC –0.6V(3 VCC = Max., Outputs Open OEAB = VCC OEBA = GND One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 5.9 3251 tbl 06 4 IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT163601 Symbol Parameter frequency(4) fMAX CLKAB or CLKBA tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA Hold Time HIGH or LOW Ax to CLKAB, Bx to CLKBA Set-up Time Clock HIGH or LOW LOW Ax to LEAB, Clock Bx to LEBA HIGH Set-up Time, CLKEN to CLK tH tSU tSU tH tH tW Hold Time, HIGH or LOW Ax to LEAB, Bx to LEBA Hold Time, CKLEN after CLK LEAB or LEBA Pulse Width HIGH(4) tW CLKAB or CLKBA Pulse Width HIGH or LOW(4) tSK(o) Output Skew (3) FCT163601A Condition(1) Min.(2) Max. Min.(2) Max. Unit CL = 50pF — 100 — 150 MHz RL = 500Ω 1.5 6.5 1.5 5.5 ns 1.5 7.2 1.5 6.2 ns 1.5 7.3 1.5 6.3 ns 1.5 7.5 1.5 6.5 ns 1.5 6.5 1.5 5.2 ns 4.0 — 3.0 — ns 0 — 0 — ns 2.5 — 2.5 — ns 2.0 — 2.0 — ns 3.0 — 2.5 — ns 1.5 — 1.0 — ns 0 — 0 — ns 3.0 — 2.5 — ns 3.0 — 3.0 — ns — 0.5 — 0.5 NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested. 5.9 ns 3251 tbl 07 5 IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS 6V ← V CC 500Ω V V IN Pulse Generator Open GND OUT D.U.T. 50pF R T C Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch 6V GND Open 3251 tbl 08 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω L 3251 lnk 04 SET-UP, HOLD AND RELEASE TIMES DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW HIGH-LOW-HIGH PULSE 1.5V 3251 lnk 06 3V 1.5V 0V tH 3251 lnk 05 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V 3251 lnk 07 DISABLE 3V CONTROL INPUT 1.5V tPZL OUTPUT NORMALLY SWITCH 6V LOW tPZH OUTPUT NORMALLY HIGH SWITCH GND 0V tPLZ 3V 3V 1.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V 3251 lnk 08 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 3. If VCC is below 3V, input voltage swings should be adjusted not to exceed VCC. 5.9 6 IDT74FCT163601/A 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX FCT XXXX Temp. Range Device Type X Package 5.9 PV PA PF Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 163601 163601A Non-Inverting 18-Bit Registered Transceiver 74 –40°C to +85°C 7