TI1 LM5160QPWPTQ1 Wide input 65v 1.5a synchronous buck / fly-buck converter Datasheet

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LM5160-Q1
SNVSAE4A – JULY 2015 – REVISED NOVEMBER 2015
LM5160-Q1 Wide Input 65-V, 1.5-A Synchronous Buck / Fly-Buck™ Converter
1 Features
3 Description
•
The LM5160 family is a 65-V, 1.5-A synchronous
step-down converter with integrated high-side and
low-side MOSFETs. The constant-on-time control
scheme requires no loop compensation and supports
high step-down ratios with fast transient response. An
internal feedback amplifier maintains ±1% output
voltage regulation over the entire operating
temperature range. The on-time varies inversely with
input voltage resulting in nearly constant switching
frequency. Peak and valley current limit circuits
protect against overload conditions. The undervoltage
lockout
(EN/UVLO)
circuit
provides
independently
adjustable
input
under-voltage
threshold and hysteresis. The LM5160 is
programmed through the FPWM pin to operate in
continuous conduction mode (CCM) from no load to
full load or to automatically switch to discontinuous
conduction mode (DCM) at light load for higher
efficiency. Forced CCM operation supports multiple
output and isolated Fly-Buck applications using a
coupled inductor.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Grade 1 Qualified with the following
results:
– Device Temperature Grade 1: -40°C to 125°C
Ambient Operating Temperature Range
Wide 4.5-V to 65-V Input Voltage Range
Integrated High and Low Side Switches
– No Schottky Diode Required
1.5-A Maximum Load Current
Constant On-Time Control
– No External Loop Compensation
– Fast Transient Response
Selectable Forced CCM or DCM Operation
CCM Option Supports Multi-Output Fly-Buck
Nearly Constant Switching Frequency
Frequency Adjustable up to 1 MHz
Programmable Soft-Start Time
Pre-Biased Startup
Peak Current Limiting Protection
Adjustable Input UVLO and Hysteresis
±1% Feedback Voltage Reference
Thermal Shutdown Protection
Device Information(1)
PART NUMBER
LM5160-Q1
PACKAGE
BODY SIZE (NOM)
HTSSOP (14) PWP
4.4 mm x 5.0 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
•
•
Industrial Programmable Logic Controller
IGBT Gate Drive Bias Supply
Telecom Primary/Secondary Side Bias
E-meter Power Line Communication
Low Power Isolated DC-DC (Fly-Buck)
Automotive Electronics
Typical Fly-Buck Application Circuit
Typical Sync-Buck Application Circuit
VOUT-SEC
VIN
VIN
VIN
BST
LM5160A
LM5160
VOUT
VIN
BST
SW
SW
RON
RON
VOUT-PRI
LM5160A
LM5160
FB
EN/UVLO
VCC
SS
AGND
EN/UVLO
FPWM
PGND
FB
VCC
SS
AGND
FPWM
PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5160-Q1
SNVSAE4A – JULY 2015 – REVISED NOVEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
6
7
8
Absolute Maximum Ratings .....................................
ESD Ratings: LM5160-Q1 .......................................
Recommended Operating Conditions ......................
Thermal Information .................................................
Electrical Characteristics...........................................
Switching Characteristics .........................................
Typical Characteristics .............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................ 11
7.2 Functional Block Diagram ...................................... 11
7.3 Feature Description ................................................ 12
7.4 Device Functional Modes ....................................... 14
8
Applications and Implementation ...................... 16
8.1 Application Information .......................................... 16
8.2 Typical Application .................................................. 16
8.3 Do's and Don'ts ...................................................... 25
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................ 26
10.2 Layout Example ................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
Related Documentation .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Original (July 2015) to Revision A
•
2
Page
Changed current limit off-timer in the Electrical Characteristics to 16.................................................................................... 6
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5 Pin Configuration and Functions
PWP Package
14-Pin HTSSOP
Top View
AGND
1
PGND
2
VIN
3
EN/UVLO
4
RON
5
SS
6
9
FB
NC
7
8
FPWM
LM5160-Q1
THERMAL
PAD
14
NC
13
SW
12
SW
11
BST
10
VCC
Pin Functions
PIN
NAME
DESCRIPTION
NUMBER
HTSSOP
WSON
AGND
1
1
Analog Ground. Ground connection of internal control circuits.
PGND
2
2
Power Ground. Ground connection of the internal synchronous rectifier FET.
VIN
3
3
Input supply connection. Operating input range is 4.5 V to 65 V.
EN/UVLO
4
4
Precision enable. Input pin of under-voltage lockout (UVLO) comparator.
RON
5
5
On-time programming pin. A resistor between this pin and VIN sets the switch on-time as a
function of input voltage.
SS
6
6
Soft-start. Connect a capacitor from SS to AGND to control output rise time and limit overshoot.
FPWM
8
7
Forced PWM logic input pin. Connect to AGND for discontinuous conduction mode (DCM) with
light loads. Connect to VCC for continuous conduction mode (CCM) at all loads and Fly-Buck
configuration.
FB
9
8
Feedback input of voltage regulation comparator.
VCC
10
9
Internal high voltage startup regulator bypass capacitor pin.
BST
11
10
Bootstrap capacitor pin. Connect a capacitor between BST and SW to bias gate driver of high
side buck FET.
SW
12,13
11,12
NC
7,14
-
EP
Switch node. Source connection of high side buck FET and drain connection of low side
synchronous rectifier FET.
No Connection.
Exposed Pad. Connect to AGND and printed circuit board ground plane to improve power
dissipation.
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6 Specifications
6.1 Absolute Maximum Ratings
Input Voltage
Output Voltage
MIN
MAX
VIN to AGND
–0.3
70
EN/UVLO to AGND
–0.3
70
RON to AGND
-0.3
70
BST to AGND
-0.3
84
VCC to AGND
-0.3
14
FPWM to AGND
-0.3
14
SS to AGND
-0.3
7
FB to AGND
-0.3
7
BST to SW
-0.3
14
BST to VCC
70
SW to AGND
–1.5
SW to AGND (20 ns transient)
70
V
V
–3
Lead Temperature(4)
Maximum Junction Temperature
UNIT
200
(3)
Storage temperature range TSTG
–40
150
–65
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
(4) For detailed information on soldering plastic SO PowerPAD package, refer to the SNOA549 available from Texas Instruments. Maximum
solder time not to exceed 4 seconds.
6.2 ESD Ratings: LM5160-Q1
V(ESD)
(1)
VALUE
UNIT
Human body model (HBM), per AEC Q100-002 (1)
±2000
V
Charged device model (CDM), per AEC Q100-011
±750
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions (1)
Over operating free-air temperature range (unless otherwise noted)
MIN
VIN Input Voltage
MAX
UNIT
4.5
65
V
1.5
A
-40
150
°C
IO Output Current
Operating Junction Temperature (2) (LM5160-Q1 only)
(1)
(2)
4
NOM
Operating Ratings are conditions under the device is intended to be functional. For specifications and test conditions, see Electrical
Characteristics
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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6.4 Thermal Information (1)
LM5160, LM5160-Q1
THERMAL METRIC
RθJA
Junction-to-ambient thermal resistance (1)
(1)
PWP (HTSSOP)
DNT (WSON)
14 PINS
12 PINS
39.3
33.4
RθJCbot
Junction-to-case (bottom) thermal resistance
2.0
1.9
ψJB
Junction-to-board thermal characteristic parameter
19.3
11.3
RθJB
Junction-to-board thermal resistance
19.6
11.1
RθJCtop
Junction-to-case (top) thermal resistance
22.8
24.7
ψJT
Junction-to-top thermal characteristic parameter
0.5
0.2
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C(1)(2) for the LM5160Q1. Unless otherwise stated, VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISD
Input Shutdown Current
VIN = 24 V, EN/UVLO = 0 V
50
90.7
µA
IOP
Input Operating Current
VIN = 24 V, FB = 3 V, Non-switching
2.3
2.84
mA
VCC
Bias Regulator Output
VIN = 24 V, ICC = 20 mA
7.5
8.52
V
VCC
Bias Regulator Current Limit
VIN = 24 V
VCC(UV)
VCC Undervoltage Threshold
VCC rising
3.98
4.1
VCC(HYS)
VCC Undervoltage Hysteresis
VCC falling
185
VCC(LDO)
VIN - VCC Dropout Voltage
VIN = 4.5 V, ICC = 20 mA
165
VCC SUPPLY
6.47
30
mA
V
mV
260
mV
HIGH-SIDE FET
Ω
RDS(ON)
High Side On Resistance
V(BST - SW) = 7 V, ISW = 1 A
0.29
BST(UV)
Bootstrap Gate Drive UV
V(BST - SW) rising
2.93
BST(HYS)
Gate Drive UV hysteresis
V(BST - SW) falling
200
mV
ISW = 1 A
0.13
Ω
3.6
V
LOW-SIDE FET
RDS(ON)
Low Side On Resistance
HIGH SIDE CURRENT LIMIT
ILIM
High Side Current Limit Threshold
(HS)
2.125
(HS)Threshold detect to FET Turn-off
2.5
2.875
100
A
TRES
Current Limit Response Time
ILIM
ns
TOFF1
Current Limit Forced Off-Time
FB = 0 V, VIN = 65 V
16
29
39.8
µs
TOFF2
Current Limit Forced Off-Time
FB = 1 V, VIN = 24 V
2.18
3.5
5.12
µs
1.9
2.5
3.0
LOW SIDE CURRENT LIMIT
ISOURCE(LS)
Sourcing Current Limit
ISINK(LS)
Sinking Current Limit
5.4
A
DIODE EMULATION
VFPWM(LOW)
FPWM Input Logic Low
VIN = 24 V
VFPWM(HIGH)
FPWM Input Logic High
VIN = 24 V
IZX
Zero Cross Detect Current
FPWM = 0 (Diode Emulation)
1
3
0
V
mA
REGULATION COMPARATOR
VREF
FB Regulation Level
I(Bias)
FB Input Bias Current
VIN = 24 V (WSON-12)
1.977
2
2.017
VIN = 24 V (HTSSOP-14)
1.975
1.995
2.015
VIN = 24 V
100
V
nA
ERROR CORRECTION AMPLIFIER & SOFT-START
GM
Error Amp Transconductance
FB = VREF (+/–) 10 mV
IEA(Source)
Error Amp Source Current
FB = 1 V, SS = 1 V
7.62
10.2
105
12.51
µA/V
IEA(Sink)
Error Amp Sink Current
FB = 5 V, SS = 2.25 V
7.46
10
12.2
V(SS-FB)
VSS - VFB Clamp Voltage
FB = 1.75 V, CSS= 1 nF
ISS
Soft-Start Charging current
SS = 0.5 V
7.63
10.2
12.5
1.213
1.24
1.277
V
15
20
25
µA
0.28
0.35
135
µA
mV
µA
ENABLE/UVLO
VUVLO (TH)
UVLO Threshold
EN/UVLO rising
IUVLO(HYS)
UVLO Hysteresis Current
EN/UVLO = 1.4 V
VSD(TH)
Shutdown Mode Threshold
EN/UVLO falling
VSD(HYS)
Shutdown Threshold Hysteresis
EN/UVLO rising
47
V
mV
THERMAL SHUTDOWN
TSD
Thermal Shutdown Threshold
175
TSD(HYS)
Thermal Shutdown Hysteresis
20
6
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(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD • RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.
6.6 Switching Characteristics (1)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 125°C for the LM5160-Q1.
Unless otherwise stated, VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MINIMUM OFF-TIME
TOFF-MIN
Minimum Off-Time, FB = 0 V
170
ns
ON-TIME GENERATOR
TON Test 1 VIN = 24 V, RON = 100 kΩ
312
428
520
TON Test 2 VIN = 24 V, RON = 200 kΩ
625
818
1040
TON Test 3 VIN = 8 V, RON = 100 kΩ
937
1247
1563
TON Test 4 VIN = 65 V, RON = 100 kΩ
132
176
220
(1)
ns
All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
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6.7 Typical Characteristics
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
At TA = 25°C and applicable to LM5160-Q1, unless otherwise noted.
70
60
50
40
70
60
50
40
Vin = 18V
Vin = 24V
Vin = 48V
30
Vin = 12V
Vin = 24V
Vin = 48V
30
20
20
0
0.2
0.4
VOut= 10V
L=47µH
0.6
0.8
1
Load Current (A)
1.2
1.4
1.6
0
ROn=200kΩ
0.2
0.4
0.6
0.8
1
Load Current (A)
VOut= 5V
L=100µH
Figure 1. Efficiency at 500 kHz
1.2
1.4
1.6
ROn=215kΩ
Figure 2. Efficiency at 250 kHz
100
100
FPWM = 0
50
Efficiency (%)
Efficiency (%)
90
FPWM = 1
80
70
IO = 0.5A
IO = 1A
IO = 1.5A
Vin = 12V
Vin = 24V
Vin = 48V
20
0.005
60
0.01
0.05
0.1
Load Current (A)
VOut= 5V
L=47µH
0.5
5
1 1.5
ROn=169kΩ
FSW=300 kHz
15
25
VOut= 5V
L=47µH
Figure 3. Efficiency CCM vs. DCM at 300kHz
35
45
Input Voltage (V)
55
65
ROn=169kΩ
Figure 4. Efficiency vs. Input Voltage at 300kHz
8
8
7
6
Vcc Voltage (V)
Vcc Voltage (V)
6
4
5
4
3
2
2
1
0
0
0
2
4
6
8
Input Voltage (V)
10
12
14
0
0.01
0.02
0.03
0.04
Icc Current (A)
0.05
0.06
VIN = 24V
Figure 5. VCC vs. VIN
8
Figure 6. VCC vs. ICC
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Typical Characteristics (continued)
At TA = 25°C and applicable to LM5160-Q1, unless otherwise noted.
2000
Vin = 12V
Vin = 24V
Vin = 48V
Vin = 65V
25
22.5
20
1000
On - Time (ns)
Peak Current LImit Off-Timer (Ps)
27.5
17.5
15
12.5
10
500
7.5
100
5
Ron = 200k:
Ron = 169k:
Ron = 100k:
2.5
0
0
0.2
0.4
0.6 0.8
1
1.2 1.4
Feedback Voltage (V)
1.6
1.8
50
10
2
15
20
25
30
35
40
Input Voltage (V)
45
50
55
60
VOUT = 5V
Figure 8. TON vs. VIN
4
650
3.5
Operating Current (mA)
Switching Frequency (kHz)
Figure 7. TOFF (ILIM) vs. VFB
750
550
450
350
250
Ron = 169k:
Ron = 100k:
Ron = 200k:
150
50
10
15
20
25
30
35
40
Input Voltage (V)
45
50
55
3
2.5
2
1.5
1
10
60
15
20
25
VOUT = 5V
45
50
55
60
VFB = 3V
Figure 9. Switching Frequency vs. VIN
Figure 10. IIN vs. VIN (Operating, Non Switching)
4
2.05
3.25
2.025
Reference Voltage (V)
Gate Drive UVLO Threshold (V)
30
35
40
Input Voltage (V)
2.5
1.75
2
1.975
Falling
Rising
1
-50
-25
0
25
50
75
100
Junction Temperature (oC)
125
150
1.95
-50
VIN = 24V
-25
0
25
50
75
100
Junction Temperature (oC)
125
150
VIN = 24V
Figure 11. Gate Drive UVLO vs. Temperature
Figure 12. Reference Voltage vs. Temperature
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Typical Characteristics (continued)
At TA = 25°C and applicable to LM5160-Q1, unless otherwise noted.
60
Input Shutdown Current (PA)
Input Operating Current (mA)
2.5
2.25
2
1.75
1.5
-50
-25
0
25
50
75
100
Junction Temperature (oC)
125
55
50
45
40
35
30
-50
150
-25
0
VIN = 24V
Figure 13. Input Operating Current vs. Temperature
Figure 14. Input Shutdown Current vs. Temperature
4.1
Current Limit (A)
2.75
3.95
3.8
2.5
2.25
3.65
3.5
-50
-25
0
25
50
75
100
Junction Temperature (oC)
125
High Side FET
Low Side FET
2
-50
150
-25
0
VIN = 24V
25
50
75
100
Junction Temperature (oC)
150
Figure 16. Current Limit vs. Temperature
0.45
2.5
0.35
FET RDSON
3
2
1.5
0.25
0.15
Rising
Falling
1
-50
125
VIN = 24V
Figure 15. VCC UVLO vs. Temperature
FPWM Threshold (V)
150
3
Falling
Rising
-25
0
25
50
75
100
Junction Temperature (oC)
125
VIN = 24V
150
High Side FET
Low Side FET
0.05
-50
-25
ISW = 200mA
Figure 17. FPWM Threshold vs. Temperature
10
125
VIN = 24V
4.25
Vcc UVLO Threshold (V)
25
50
75
100
Junction Temperature (oC)
0
25
50
75
100
Junction Temperature (oC)
125
150
D001
VIN = 24V
Figure 18. Switch Resistance vs. Temperature
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7 Detailed Description
7.1 Overview
The LM5160 family of step-down switching regulators features all the functions needed to implement a low cost,
efficient buck converter capable of supplying 1.5 A to the load. This high voltage regulator contains 65-V NChannel buck and synchronous rectifier switches and is available in the WSON-12 package. The LM5160-Q1 is
available in the HTSSOP-14 package. The regulator operation is based on constant on-time control where the
on-time is inversely proportional to input voltage VIN. This feature maintains a relatively constant operating
frequency with load and input voltage variations. A constant on-time switching regulator requires no loop
compensation resulting in fast load transient response. Peak current limit detection circuit is implemented with a
forced off-time during current limiting which is inversely proportional to voltage at the feedback pin, VFB and
directly proportional to VIN. Varying the current limit off-time with VFB and VIN ensures short circuit protection with
minimal current limit foldback. The LM5160 can be applied in numerous end equipment systems requiring
efficient step-down regulation from higher input voltages. This regulator is well suited for 24 V industrial systems
as well as 48 V telecom and PoE voltage ranges. The LM5160 integrates an under-voltage lockout (EN/UVLO)
circuit to prevent faulty operation of the device at low input voltages and features intelligent current limit and
thermal shutdown to protect the device during overload or short circuit.
The LM5160 device name is used generically throughout this document and represents both the LM5160-Q1 and
LM5160A unless stated otherwise. The only difference between the two is the ability to connect an external
voltage source to the VCC pin of the LM5160A.
7.2 Functional Block Diagram
LM5160
VIN
VIN
VCC
VCC REGULATOR
RUV2
VCC UVLO
CVCC
20µA
CIN
EN/UVLO
STANDBY
RUV1
SHUTDOWN
THERMAL
SHUTDOWN
VIN
1.24V
BIAS
REGULATOR
BST
0.35V
VIN
RON
CBST
RON
ON/OFF
TIMERS
VOUT
RFB2
CSS
FEEDBACK
COMPARATOR
SS
DISABLE
CONSTANT
ON-TIME
CONTROL
LOGIC
SW
VCC
L
VOUT
RESR
COUT
FB
RFB1
PGND
GM ERROR
AMP
2.0V
AGND
CURRENT
LIMIT TIMER
CURRENT LIMIT
COMPARATOR
+
VILIM
FPWM
DIODE
EMULATION
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7.3 Feature Description
7.3.1 Control Circuit
The LM5160 step-down switching regulator employs a control principle based on a comparator and a one-shot
on-timer, with the output voltage feedback (FB) compared to the voltage at the Soft-Start (SS) pin (VSS). If the FB
voltage is below VSS, the internal buck switch is turned on for a time period determined by the input voltage and
one-shot programming resistor (RON). Following the on-time, the buck switch must remain off for the minimum
off-time forced by the minimum off-time one-shot. The buck switch remains off until the FB voltage falls below the
Soft-Start again, when it turns back on for another on-time one-shot period.
During a rapid start-up or when the load current increases suddenly, the regulator will operate with minimum offtime per cycle. When regulating the output in steady state operation, the off-time will automatically adjust to
produce the SW pin duty cycle required for output voltage regulation.
When in regulation, the LM5160 operates in continuous conduction mode at heavy load currents. If the FPWM
pin is connected to ground or left floating, the regulator will operate in discontinuous conduction mode at light
load with the synchronous rectifier FET in diode emulation. With sufficient load, the LM5160 operates in
continuous conduction mode with the inductor current never reaching zero during the off-time of the high side
FET. In this mode the operating frequency remains relatively constant with load and line variations. The minimum
load current for continuous conduction mode is one-half the inductor’s ripple current amplitude. The operating
frequency is programmed by the RON pin resistor and can be calculated from Equation 1 with RON expressed in
ohms.
VOUT
Fsw
Hz
RON u 1u 10 10
(1)
In discontinuous conduction mode, current through the inductor ramps up from zero to a peak value during the
on-time, then ramps back to zero before the end of the off-time. The next on-time period starts when the voltage
at FB falls below VSS. When the inductor current is zero during the high side FET off-time, the load current is
supplied by the output capacitor. In this mode, the operating switching frequency is lower than the continuous
conduction mode switching frequency and the frequency varies with load. The discontinuous conduction mode
maintains conversion efficiency at light loads since the switching losses decrease with the decrease in load and
frequency.
The output voltage is set by two external resistors ( RFB1, RFB2). The regulated output voltage is calculated from
Equation 2, where VREF = 2 V (typ) is the feedback reference voltage.
VREF u (RFB2 RFB1 )
VOUT
V
RFB1
(2)
7.3.2 VCC Regulator
The LM5160 contains an internal high voltage linear regulator with a nominal output voltage of 7.5 V (typ). The
VCC regulator is internally current limited to 30 mA (minimum). This regulator supplies power to internal circuit
blocks including the synchronous FET gate driver and the logic circuits. When the voltage on the VCC pin
reaches the under-voltage lockout (VCC(UV)) threshold of 3.98 V (typ), the IC is enabled. An external capacitor at
the VCC pin stabilizes the regulator and supplies transient VCC current to the gate drivers. An internal diode
connected from VCC to the BST pin replenishes the charge in the high side gate drive bootstrap capacitor when
the SW pin is low.
In high input voltage applications, the power dissipated in the regulator is significant and can limit the efficiency
and maximum achievable output power. The LM5160A allows the internal VCC regulator power loss to be
reduced by supplying the VCC voltage via a diode from an external voltage source regulated between 9V and 13
V. The external VCC bias can be supplied from the LM5160A converter output rail if the regulation voltage is
within this range. When the VCC pin of the LM5160A is raised above the regulation voltage (7.5 V typical), the
internal regulator is disabled and the power dissipation in the IC is reduced. The only difference between the
LM5160 and LM5160A is wide operating VCC voltage range of the LM5160A.
12
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Feature Description (continued)
7.3.3 Regulation Comparator
The feedback voltage at the FB pin is compared to the SS pin voltage VSS. In normal operation when the output
voltage is in regulation, an on-time period is initiated when the voltage at FB pin falls below VSS. The high side
buck switch will stay on for the on-time one-shot period causing the FB voltage to rise. After the on-time period
expires, the high side switch will remain off until the FB voltage falls below VSS. During the startup, the FB
voltage will be below VSS at the end of each on-time period and the high side switch turns on again after the
minimum forced off-time of 170 ns (typ). When the output is shorted to ground (FB = 0 V), the high side peak
current limit is triggered, the high side FET is turned off, and remains off for a period determined by the current
limit off-timer. See the Current Limit section for additional information.
7.3.4 Soft-Start
The soft-start feature of the LM5160 allows the converter to gradually reach a steady state operating point,
thereby reducing start-up stresses and current surges. When the EN/UVLO pin is above the EN/UVLO standby
threshold VUVLO(TH) = 1.24 V (typ) and the VCC exceeds the VCC under-voltage VCC(UV) = 3.98 V (typ) threshold,
an internal 10 µA current source charges the external capacitor at the SS pin (CSS) from 0 V to 2 V. The voltage
at the SS pin is the non-inverting input of the internal FB comparator. The soft-start interval ends when the SS
capacitor is charged to the 2V reference level. The ramping voltage at the SS pin produces a controlled,
monotonic output voltage start-up. A minimum 1 nF soft-start capacitor should be used in all applications.
7.3.5 Error Transconductance (GM) Amplifier
The LM5160 provides a trans-conductance (GM) error amplifier that minimizes the difference between the
reference voltage (VREF) and the average feedback (FB) voltage. This amplifier reduces the load and line
regulation errors that are common in constant-on-time regulators. The soft-start capacitor (CSS) provides
compensation for this error correction loop. The soft-start capacitor should be greater than 1 nF to ensure
stability.
7.3.6 On-Time Generator
The on-time of the LM5160 high side FET is determined by the RON resistor and is inversely proportional to the
input voltage (VIN). The inverse relationship with VIN results in a nearly constant frequency as VIN is varied. The
on-time can be calculated from Equation 3 with RON expressed in ohms.
TON
RON u 1u 10
VIN
10
s
(3)
To set a specific continuous conduction mode switching frequency (FSW expressed in Hz), the RON resistor is
determined from the following:
VOUT
:
RON
FSW u 1u 10 10
(4)
RON should be selected for a minimum on-time (at maximum VIN) greater than 150 ns for proper operation. This
minimum on-time requirement will limit the maximum switching frequency of applications with relatively high VIN
and low VOUT.
7.3.7 Current Limit
The LM5160 provides an intelligent current limit off-timer that adjusts the off-time to reduce the foldback in the
current limit. If the peak value of the current in the buck switch exceeds 2.5 A (typ) the present on-time period is
immediately terminated, and a non-resettable off-timer is initiated. The length of the off-time is controlled by the
FB voltage and the input voltage VIN. As an example, when VFB = 0 V and VIN = 24 V, the off-time is set to 10 μs.
This condition would occur if the output is shorted or during the initial phase of start-up. In cases of output
overload where the FB voltage is greater than zero volts (a soft short), the current limit off-time is reduced.
Reducing the off-time during less severe overloads reduces the current limit foldback, overload recovery time,
and start-up time. The current limit off-time, TOFF(CL) is calculated from Equation 5:
5VIN
TOFF(CL)
Ps
24VFB 12
(5)
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Feature Description (continued)
7.3.8 N-Channel Buck Switch and Driver
The LM5160 integrates an N-Channel buck switch and associated floating high side gate driver. The gate driver
circuit works in conjunction with an external bootstrap capacitor and an internal high voltage bootstrap diode. A
10 nF or larger ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the
high-side driver during the buck switch on-time. During the off-time, the SW node is pulled down to approximately
0 V and the bootstrap capacitor charges from VCC through the internal bootstrap diode. The minimum off-time of
170 ns (typ) provides a minimum time each cycle to recharge the bootstrap capacitor.
7.3.9 Synchronous Rectifier
The LM5160 provides an internal low side synchronous rectifier N-Channel FET. This low side FET provides a
low resistance path for the inductor current when the high-side FET is turned off.
With the FPWM pin connected to ground or left floating, the LM5160 synchronous rectifier operates in diode
emulation mode. Diode emulation enables the pulse-skipping during light load conditions. This leads to a
reduction in the average switching frequency at light loads. Switching losses and FET gate driver losses, both of
which are proportional to switching frequency, are significantly reduced and efficiency is improved. This pulseskipping mode also reduces the circulating inductor currents and losses associated with a continuous conduction
mode (CCM).
When the FPWM pin is pulled high, diode emulation is disabled. The inductor current can flow in either direction
through the low side FET resulting in CCM operation with nearly constant switching frequency. A negative sink
current limit circuit limits the current that can flow into the SW pin and through the low side FET to ground. In a
buck regulator application, large negative current will only flow from VOUT to the SW pin if VOUT is lifted above the
output regulation set-point.
7.3.10 Enable / Under-Voltage Lockout (EN/UVLO)
The LM5160 contains a dual level under-voltage lockout (EN/UVLO) circuit. When the EN/UVLO pin voltage is
below 0.35 V, the regulator is in a low current shutdown mode. When the EN/UVLO pin voltage is greater than
0.35 V (typ.) but less than 1.24 V (typ.), the regulator is in standby mode. In standby mode, the VCC bias
regulator is active but converter switching remains disabled. When the voltage at the VCC pin exceeds the VCC
rising threshold VCC(UV) = 3.98 V (typ) and the EN/UVLO pin voltage is greater than 1.24 V, normal switching
operation begins. An external resistor voltage divider from VIN to GND can be used to set the minimum
operating voltage of the regulator.
EN/UVLO hysteresis is accomplished with an internal 20 μA (typ) current source (IUVLO(HYS)) that is switched on
or off into the impedance of the EN/UVLO pin resistor divider. When the EN/UVLO threshold is exceeded, the
current source is activated to effectively raise the voltage at the EN/UVLO pin. The hysteresis is equal to the
value of this current times the upper resistance of the resistor divider, (RUV2) (See Functional Block Diagram ).
7.3.11 Thermal Protection
The LM5160 should be operated such that the junction temperature does not exceed 150 °C during normal
operation. An internal Thermal Shutdown circuit is provided to protect the LM5160 in the event of a higher than
normal junction temperature. When activated, typically at 175 °C, the controller is forced into a low power reset
state, disabling the high side buck switch and the VCC regulator. This feature prevents catastrophic failures from
accidental device overheating. When the junction temperature falls below 155 °C (typical hysteresis = 20 °C), the
VCC regulator is enabled, and operation resumes.
7.4 Device Functional Modes
7.4.1 Forced Pulse Width Modulation (FPWM) Mode
The Synchronous Rectifier section gives a brief introduction to the LM5160 diode emulation feature. The FPWM
pin allows the power supply designer to select either CCM or DCM mode of operation at light loads. When the
FPWM pin is connected to ground or left floating (FPWM = 0), a pulse-skipping mode is enabled and a zerocross current detector circuit is enabled. The zero-cross detector will turn off the low side FET when the inductor
current falls to zero (IZX, see Electrical Characteristics ). This feature allows the LM5160 regulator to operate in
DCM mode at light loads. In the DCM state, the switching frequency will decrease with lighter loads.
14
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Device Functional Modes (continued)
If the FPWM pin is pulled high (FPWM connected to VCC), the LM5160 will operate in CCM mode even at light
loads. This option allows the synchronous rectifier FET to conduct continuously until the start of the next high
side switch cycle. The inductor current will drop to zero and then reverse direction (negative direction through
inductor), passing from drain to source of low side FET. The current will flow continuously until the FB
comparator initiates another high side switch on-time. CCM operation reduces efficiency at light load but
improves the output transient response to step load changes and provides nearly constant switching frequency.
Table 1. FPWM Pin Mode Summary
FPWM PIN CONNECTION
LOGIC STAGE
DESCRIPTION
GND or Floating (High Z)
0
The FPWM pin is grounded or left floating. DCM enabled at light
loads.
VCC
1
The FPWM pin is connected to VCC. The LM5160 then operates
in CCM mode at light loads.
7.4.2 Under-Voltage Detector
The following table summarizes the dual threshold levels of the under-voltage lockout (EN/UVLO) circuit
explained in Enable / Under-Voltage Lockout (EN/UVLO) .
Table 2. UVLO Pin Mode Summary
EN/UVLO PIN
VOLTAGE
VCC REGULATOR
MODE
< 0.35 V
Off
Shutdown
VCC regulator disabled. High and low side
FETs disabled.
0.35 V to 1.24 V
On
Standby
VCC regulator enabled. High and low side
FETs disabled.
VCC < VCC(UV)
Standby
VCC regulator enabled. High and low side
FETs disabled.
VCC > VCC(UV)
Operating
VCC regulator enabled. Switching enabled.
> 1.24 V
DESCRIPTION
If an EN/UVLO set-point is not required, the EN/UVLO pin can be driven by a logic signal as an enable input or
connected directly to the VIN pin. If the EN/UVLO is directly connected to the VIN pin, the regulator will begin
switching when the VCC(UV) = 3.98 V (typ) is satisfied.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5160 family is a synchronous-buck regulator converter designed to operate over a wide input voltage and
output current range. Spreadsheet based Quick-Start Calculator tools, available on the www.ti.com product
website, can be used to design a single output synchronous buck converter or an isolated dual output Fly-Buck
converter using both the LM5160 and LM5160A. See application note AN-2292 for a detailed design guide for
the Fly-Buck converter. Alternatively, online WEBENCH® software can be used to create a complete buck or FlyBuck designs and generate the bill of materials, estimated efficiency, solution size, and cost of the complete
solution.
Typical Application describes a few application circuits using the LM5160 or LM5160A with detailed, step by step
design procedures.
8.2 Typical Application
8.2.1 LM5160 Synchronous Buck (10-V to 60-V Input, 5-V Output, 1.5-A Load)
A typical application example is a synchronous buck converter operating from a wide input voltage range of 10 V
to 65 V and providing a stable 5 V output voltage with maximum output current capability of 1.5 A. The complete
schematic for a typical synchronous buck application circuit is shown in Figure 19 . In the application schematic
below, the components are labeled by numbers instead of the descriptive name used in the previous sections.
For example, R3 represents RON and so on.
TP
C4
VIN
3
R3
J1
2
1
C1
2.2μF
C10
2.2μF
R1
C2
127k
0.47μF
5
VIN
6
VIN 10 - 60VDC
SW
SW
EN/UVLO
FPWM
SS
VCC
C3
0.022uF
1
2
AGND
PGND
PAD
10
L1
0.01μF
RON
169k
4
BST
FB
VOUT
12
11
47uH
7
R4
9
DNP
8
R5
3.01k
C6
R7
0.47
J2
2
1
DNP
C7
DNP
VOUT 5VDC @ 1.5A
C8
10μF
C9
10μF
C5
1 μF
R6
2.00k
R2
18.2k
GND
GND
GND
GND
GND
GND
GND
Figure 19. Synchronous Buck Application Circuit
8.2.1.1 Design Requirements
A typical synchronous-buck application introduced in LM5160 Synchronous Buck (10-V to 60-V Input, 5-V
Output, 1.5-A Load) , Table 3 summarizes the operating parameters:
Table 3. Design Parameters
16
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
10 V to 65 V
Output
5V
Maximum Load Current
1.5 A
Nominal Switching Frequency
300 kHz
Light Load Operating Mode
CCM, FPWM=1
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Output Resistor Divider Selection
With the required output voltage set point at 5 V and VFB = 2 V (typ.), the ratio of R6 (RFB1) to R5 (RFB2) can be
calculated using the formula:
RFB2 VOUT
1
RFB1 VREF
(6)
The resistor ratio calculates to be 3:2. Standard values of R6 (RFB1) = 2 kΩ and R5 (RFB2 ) =3.01 kΩ are chosen.
Higher or lower values could be used as long as the ratio of the 3:2 is maintained.
8.2.1.2.2 Frequency Selection
The duty cycle required to maintain output regulation at the minimum input voltage restricts the maximum
switching frequency of LM5160. The maximum value of the minimum forced off-time TOFF,min (max), limits the
duty cycle and therefore the switching frequency. The maximum frequency that will avoid output dropout at
minimum input voltage can be calculated from Equation 7.
VIN, min VOUT
FSW, max (@ VIN, min )
VIN, min u TOFF, min (ns)
(7)
For this design example, the maximum frequency based on the minimum off-time limitation for TOFF,min(typ) = 170
ns is calculated to be FSW,max(@VIN,min) = 2.9 MHz. This value is well above 1 MHz, the maximum possible
operating frequency of the LM5160. Therefore, the minimum off-time parameter cannot be used further for the
maximum achievable switching frequency calculation in this application.
At the maximum input voltage, the maximum switching frequency of LM5160 is restricted by the minimum ontime, TON,min which limits the minimum duty cycle of the converter. The maximum frequency at maximum input
voltage can be calculated using Equation 8.
VOUT
FSW, max (@ VIN, max )
VIN, max u TON, min (ns)
(8)
Using Equation 8 and TON,min (typ) = 150 ns, the maximum achievable switching frequency is
FSW,max(@VIN,min)=514 kHz. Taking this value as the maximum possible operational switching frequency over the
input voltage range in this application, a nominal switching frequency of FSW = 300 kHz is chosen for this design.
The value of the resistor, RON sets the nominal switching frequency based on Equation 9.
VOUT
:
RON
FSW u 1u 10 10
(9)
For this particular application with FSW = 300 kHz, RON calculates to be 167 kΩ . Selecting a standard value for
R3 (RON) = 169 kΩ (±1%) will result in an ideal nominal frequency of 296 kHz. The resistor value may need to
adjusted further in order to achieve the required switching frequency as the switching frequency in COTs varies
slightly(±10%) with input voltage and/or output current. Operation at a lower nominal switching frequency will
result in higher efficiency but increase in the inductor and capacitor values leading to a larger total solution size.
8.2.1.2.3 Inductor Selection
The inductor is selected to limit the inductor ripple current between 20 and 40 percent of the maximum load
current. The minimum value of the inductor required in this application can be calculated from:
VO u (VIN, max VO )
Lmin
VIN, max u FSW u IO, max u 0.4
(10)
Based on Equation 10 , the minimum value of the inductor is calculated to be 26 µH for VIN = 65 V (max) and
inductor current ripple equal to 40 percent of the maximum load current. Allowing some margin for inductance
variation and inductor saturation, a higher standard value of L1 (L) = 47 µH is selected for this design.
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The peak inductor current at maximum load must be smaller than the minimum current limit threshold of the high
side FET as given in Electrical Characteristics table. The inductor current ripple at any input voltage is given by:
VO u (VIN VO )
'IL
VIN u FSW u L
(11)
The peak-to-peak inductor current ripple is calculated to be 180 mA and 332 mA at the minimum and maximum
input voltages respectively. The maximum peak inductor current in the buck FET is given by:
'IL, max
IL(peak) IO, max
(12)
2
In this design with maximum output current of 1.5 A, the maximum peak inductor current is calculated to be
approximately 1.67 A which is less than the minimum high-side FET current limit threshold.
The saturation current of the inductor must also be carefully considered. The peak value of the inductor current
will be bound by the high side FET current limit during overload or short circuit conditions. Based on the high
side FET current limit specification in the Electrical Characteristics , an inductor with saturation current rating
above 2.875 A (max) should be selected.
8.2.1.2.4 Output Capacitor Selection
The output capacitor is selected to limit the capacitive ripple at the output of the regulator. Maximum capacitive
ripple is observed at maximum input voltage. The output capacitance required for a ripple voltage ∆VO across the
capacitor is given by Equation 13.
'IL, max
COUT
8 u FSW u 'VO, ripple
(13)
Substituting ∆VO, ripple = 10 mV gives COUT = 14 μF. Two standard 10 μF ceramic capacitors in parallel (C8, C9)
are selected. An X7R type capacitor with a voltage rating 16 V or higher should be used for COUT (C8, C9) to limit
the reduction of capacitance due to dc bias voltage.
8.2.1.2.5 Series Ripple Resistor - RESR
The series resistor is selected such that sufficient ripple injection is ensured at the feedback node FB. The ripple
produced by RESR is proportional to the inductor current ripple, and therefore, RESR should be chosen for
minimum inductor current ripple which occurs at minimum input voltage. The RESR is calculated by Equation 14.
25 mV u VO
RESR t
VREF u 'IL, min
(14)
With VO = 5 V, VREF = 2 V and ΔIL, min = 180 mA (at VIN, min= 10 V) as calculated in Equation 11, Equation 14
requires an RESR greater than or equal to 0.35 Ω. Selecting R7 (RESR) = 0.47 Ω will result in ~150 mV of
maximum output voltage ripple at VIN,max. For applications requiring lower output voltage ripple, Type II or Type III
ripple injection circuits should be used as described in Ripple Configuration.
8.2.1.2.6 VCC and Bootstrap Capacitor
The VCC capacitor charges the bootstrap capacitor during the off-time of the high side switch and powers
internal logic circuits and the low side sync FET gate driver. The bootstrap capacitor biases the high side gate
driver during the high side FET on-time. A good value for C5 (CVCC) is 1 µF. A good choice for C4 (CBST) is 10
nF. Both should be high quality X7R ceramic capacitors.
8.2.1.2.7 Input Capacitor Selection
The input capacitor must be large enough to limit the input voltage ripple to an acceptable level. Equation 15
provides the input capacitance CIN required for a worst case input ripple of ∆VIN, ripple .
IO, max u D u (1 D)
CIN
'VIN, ripple u FSW
(15)
18
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CIN (C1, C10) supplies most of the switch current during the on-time to limit the voltage ripple at the VIN pin. At
maximum load current, when the buck switch turns on, the current into the VIN pin quickly increases to the valley
current of the inductor ripple and then ramps up to the peak of the inductor ripple during the on-time of the high
side FET. The average current during the on-time is the output load current. For a worst case calculation, CIN
must supply this average load current during the maximum on-time, without letting the voltage at VIN drop more
than the desired input ripple. For this design, the input voltage drop is limited to 0.5 V and the value of CIN is
calculated using Equation 15.
Based on Equation 15, the value of the input capacitor is calculated to be approximately 2.5 µF at D = 0.5.
Taking into account the decrease in capacitance over an applied voltage, two standard value ceramic capacitors
of 2.2 μF are selected for C1 and C10. The input capacitors should be rated for the maximum input voltage
under all operating and transient conditions. A 100 V, X7R dielectric was selected for this design.
A third input capacitor C2 may be needed in this design as a bypass path for the high frequency component of
the input switching current. The value of C2 is 0.47 μF and this bypass capacitor (when used with the LM5160Q1 HTSSOP-14 package, a bypass capacitor C2 = 0.1 μF is used) should be placed directly across VIN and
PGND (pin 3 and 2) near the IC. The CIN values and location are critical to reducing switching noise and
transients.
8.2.1.2.8 Soft-Start Capacitor Selection
The capacitor at the SS pin determines the soft-start time, i.e. the time for the output voltage to reach its final
steady state value. The capacitor value is determined from Equation 16:
ISS u TStartup
CSS
VSS
(16)
With C3 (CSS) set at 22 nF and the Vss = 2 V, ISS = 10 µA, the TStartup should measure approximately 4 ms.
8.2.1.2.9 EN/UVLO Resistor Selection
The UVLO resistors R1 (RUV2) and R2 (RUV1) set the input under-voltage lockout threshold and hysteresis
according to the following equations:
VIN(HYS) IUVLO(HYS) u RUV2
(17)
and,
VIN, UVLO(rising)
§ RUV2 ·
VUVLO(TH) ¨ 1
¸
RUV1 ¹
©
(18)
From the Electrical Characteristics table, IUVLO(HYS) = 20 μA (typ). To design for VIN rising threshold (VIN,
UVLO(rising)) at 10 V and EN/UVLO hysteresis of 2.5 V, Equation 17 and Equation 18 yield RUV1 = 17.98 kΩ and
RUV2 = 125 kΩ . Selecting 1% standard value of R2 (RUV1) = 18.2 kΩ and R1 (RUV2) = 127 kΩ results in UVLO
thresholds and hysteresis of 9.89 V and 2.54 V respectively.
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8.2.1.3 Application Performance Plots
5.025
100
90
80
70
Efficiency (%)
Output Voltage (V)
5.015
5.005
4.995
Vin = 12V
4.985
Vin = 24V
Vin = 48V
4.975
0.00
0.25
0.50
0.75
1.00
Load Current (A)
1.25
1.50
60
50
40
30
Vin = 12V
20
Vin = 24V
10
Vin = 48V
0
0.00
0.25
0.50
0.75
1.00
1.25
1.50
Load Current (A)
C002
Figure 20. Load Regulation
1.75
C001
Figure 21. Efficiency vs IOUT
Figure 22. EN/UVLO Startup at VIN= 24 V and IOUT = 1 A
Figure 23. Pre-Bias Startup at VIN= 48 V and RLOAD = 3Ω
Figure 24. EN/UVLO Startup at VIN= 24 V and RLOAD = 100Ω
20
Figure 25. Startup at VIN= 48 V and RLOAD = 10Ω
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iLIND (500 mA/div)
VSW (20 V/div)
VSS (2 V/div)
VOUT (5 V/div)
Time = 50 µs/div)
Figure 26. Load Transient (300 mA - 1.5 A) at VIN = 24 V
with Type 3 Ripple Configuration
Figure 27. Output Short-Circuit at VIN = 48 V
8.2.2 LM5160 Isolated Fly-Buck (18-V to 32-V Input, 12-V/4.5W Isolated Output)
A typical application example for an isolated Fly-Buck converter operates over an input voltage range of 18 V to
32 V. It provides a stable 12 V isolated output voltage with output power capability of 4.5 W. The complete
schematic of the Fly-Buck application circuit is shown in Figure 28 .
C3
2200pF
J1
GND
ISOGND
R1
0
C1
10µF
C2
10µF
R2
2.0k
2
1
D1
R6
127k
C6
2.2uF
18-32VIN
C7
2.2uF
C8
0.47µF
R7
5
301k
4
J3
6
2
1
VIN
BST
RON
SW
SW
EN/UVLO
FPWM
SS
VCC
C13
0.082µF
J4
1
R10
10.0k
1
2
AGND
PGND
PAD
FB
10
12
11
C5
0.01µF
R3
3
3
1
TP1
VIN
0
51.1k
7
VOUT
C4
R4
1000pF
J2
1
2
C9
0.1µF
9
12VOUT
6
4
VOUTISO
DFLS1100-7
T1
750314597
8VOUT
R8
6.04K
8
C10
10µF
C11
10µF
LM5160DNT
GND
GND
GND
GND
R9
2.00k
C12
1µF
GND
GND
GND
GND
Figure 28. 12 V/ 4.5 W Fly-Buck Schematic
8.2.2.1 LM5160 Fly-Buck Design Requirements
The LM5160 Fly-Buck application example is designed to operate from a 24 V DC supply with line variations
from 18 V to 32 V. This example provides a space-optimized and efficient 12 V isolated output solution with
secondary load current capability from 0 mA to 400 mA. The primary side remains unloaded in this application.
The switching frequency is set at 300 kHz (nominal). This design achieves greater than 88% peak efficiency.
Table 4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
18 V - 32 V
Isolated output
12 V
Isolated load current range
0 mA to 400 mA
Nominal switching frequency
300 KHz
Peak Efficiency
88%
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8.2.2.2 Detailed Design Procedure
The Fly-Buck converter design procedure closely follows the buck converter design outlined in LM5160
Synchronous Buck (10-V to 60-V Input, 5-V Output, 1.5-A Load) . The selection of primary output voltage,
transformer turns ratio, rectifier diode, and output capacitors are covered here.
8.2.2.2.1 Selection of VOUT1 and Turns Ratio
The primary output voltage in a Fly-Buck converter should be no more than one half of the minimum input
voltage. For a minimum VIN of 18 V, the primary output voltage (VOUT) should be no higher than 9 V. To generate
an isolated output voltage of VOUT (ISO) = 12 V, a transformer turns ratio (N1:N2) of 1:1.5 is selected. Using this
turns ration, the required primary output voltage VOUT is calculated to be:
VOUT(ISO) 0.7 V
VOUT
8.47 V
1.5
(19)
The 0.7 V subtracted from VOUT(ISO) represents the forward voltage drop of the secondary rectifier diode. Fine
tuning the primary side VOUT1 may be required to account for voltage errors due to the leakage inductance of the
transformer and the resistance of the transformer windings and the low side FET of LM5160.
8.2.2.2.2 Secondary Rectifier Diode
The secondary rectifier diode must block the maximum input voltage multiplied by the transformer turns ratio.
The minimum diode reverse voltage VR(diode) rating is given by:
N2
VR(diode) VIN(max) u
32 V u 1.5 48 V
(20)
N1
A diode of 60 V or higher reverse voltage rating should be selected in this application. If the input voltage (VIN)
has transients above the normal operating maximum input voltage of 32 V, then the worst case transient input
voltage should be used in the diode voltage calculation of Equation 20.
8.2.2.2.3 External Ripple Circuit
Type 3 ripple circuit is required for Fly-Buck applications. The design procedure for ripple components is identical
to that in a buck converter. See Ripple Configuration for ripple design information.
8.2.2.2.4 Output Capacitor (COUT2)
The Fly-Buck output capacitor conducts higher ripple current than a buck converter output capacitor. The
capacitive ripple for the isolated output capacitor is calculated based on the time the rectifier diode is off. During
this time the entire output current is supplied by the output capacitor. The required capacitance for a worst case
VOUT2 (VOUT (ISO)) ripple voltage can be calculated using Equation 21 where, ΔVOUT2 is the target ripple at the
secondary output.
COUT2
IOUT2 § VOUT1 · 1
¨
¸u
'VOUT2 ¨© VIN(MIN) ¸¹ fsw
(21)
Equation 21 is an approximation and ignores the ripple components associated with ESR and ESL of the output
capacitor. For a ΔVOUT2 = 100 mV, Equation 21 requires COUT2 = 6.5 µF. When selecting a capacitor, its DC bias
should be considered to ensure sufficient capacitance over the output voltage.
22
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8.2.2.3 Application Performance Plots
Isolated Sec. Output Voltage (V)
14
13
12
11
10
Vin = 18V
9
Vin = 24V
Vin = 32V
8
0.0
0.1
0.2
0.3
0.4
Secondary Load Current (A)
0.5
C002
Figure 30. Efficiency vs. IOUT2
Figure 29. Load Regulation
VSW (20 V/div)
VD1-ISOGND (20 V/div)
iLSEC (500 mA/div)
iLPRI (500 mA/div)
Time = 1 µs/div
Figure 31. Primary Switch Node at VIN = 24 V
and IOUT2 = 200 mA
Figure 32. Load Transient at IOUT2 = 100 mA - 300mA
VOUT1 (10 V/div)
VOUT2 (10 V/div)
iLPRI (2 A/div)
Time = 100 µs/div
Figure 33. VIN Startup at IOUT2 = 200 mA
Figure 34. Secondary Short at IOUT2 = 600mA
and IOUT1 = 200mA
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8.2.3 LM5160A Isolated Fly-Buck (18-V to 32-V Input, 12-V/4.5W Isolated Output)
The LM5160A when used in either the buck or the Fly-Buck application, can also be biased by an external
voltage source for improved efficiency requirements. The LM5160A, can be externally biased to VOUT by
connecting VCC to VOUT through a diode as shown in the Fly-Buck application circuit in Figure 35 . In this dual
output rail Fly-Buck application circuit, the VCC pin is externally diode connected (D2) to VOUT (primary). The
design procedure with LM5160A, for both Buck and the Fly-Buck™, remain same as with LM5160. The voltage
applied to the VCC pin, either from VOUT or an external supply should be between 9V and 13V.
C3
2200pF
J1
GND
ISOGND
R1
0
C1
10µF
C2
10µF
R2
2.0k
2
1
D1
3
R7
R6
127k
18-32VIN
C6
2.2µF
C7
2.2µF
5
VIN
4
6
10
SW
SW
EN/UVLO
FPWM
SS
VCC
1
2
13
J4
C13
0.082µF
1
1040
R4
VOUT
7
51.1k
VOUT
C4
1000pF
D2
C9
0.1µF
9
FB
J2
R8
6.04K
1
2
C10
10µF
GND
GND
C11
10µF
8VOUT
8
AGND
PGND
PAD
C12
1µF
LM5160A
GND
0
12
11
B0530W-7-F
R10
10.0k
GND
R3
0.01µF
RON
301k
C8
0.47µF
C5
BST
1
VIN
2
1
3
U1
J3
GND
12VOUT
6
4
VOUTISO
DFLS1100-7
T1
750314597
TP1
R9
2.00k
GND
GND
GND
Figure 35. 12 V/ 4.5 W Fly-Buck Schematic with LM5160A
8.2.4 Ripple Configuration
LM5160 and LM5160A uses a Constant-On-Time (COT) control scheme, in which the on-time is terminated by a
one-shot, and the off-time is terminated by the feedback voltage (VFB) falling below the reference voltage.
Therefore, for stable operation, the feedback voltage must decrease monotonically in phase with the inductor
current during the off-time. Furthermore, this change in feedback voltage (VFB) during off-time must be large
enough to dominate any noise present at the feedback node.
Table 5 presents three different methods for generating appropriate voltage ripple at the feedback node. Type 1
and Type 2 ripple circuits couple the ripple from the output of the converter to the feedback node (FB). The
output voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor and
R3.
The capacitive ripple is out of phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at output
(VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
Type 3 ripple method uses a ripple injection circuit with RA, CA and the switch node (SW) voltage to generate a
triangular ramp. This triangular ramp is then ac coupled into the feedback node (FB) using the capacitor CB.
Since this circuit does not use the output voltage ripple, it is suited for applications where low output voltage
ripple is imperative. See application note AN-1481 for more details for each ripple generation method.
24
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Table 5. Ripple Configuration
TYPE 1
TYPE 2
TYPE 3
Lowest Cost
Reduced Ripple
Minimum Ripple
VOUT
VOUT
L1
VOUT
L1
L1
R FB2
Cff
R FB2
R3
To FB
C OUT
COUT
R FB2
GND
R FB1
GND
25 mV u VO
VREF u 'IL1, min
CA
CB
To FB
R FB1
R3 t
RA
R3
C OUT
To FB
R FB1
GND
Cff t
5
FSW u (RFB2 IIRFB1 )
R A CA t
(22) R t 25 mV
3
'IL1, min
(VIN, min
VO ) u TON(@ VIN, min )
25mV
(24)
(23)
8.3 Do's and Don'ts
As mentioned earlier in Soft-Start , the SS capacitor CSS, should always be more than 1 nF in both buck and FlyBuck applications. Apart from determining the startup time, this capacitor serves as the external compensation of
the internal GM error amplifier. A minimum value of 1 nF is necessary to maintain stability. The SS pin should not
be left floating.
The VCC pin in the LM5160-Q1 should not be biased with an external voltage source. When improved efficiency
requirement warrants an external Vcc bias, the LM5160A should be used.
9 Power Supply Recommendations
The LM5160 is designed to operate with an input power supply capable of supplying a voltage range between
4.5 V and 65 V. The power supply should be well regulated and capable of supplying sufficient current to the
regulator during the sync buck mode or the isolated Fly-Buck mode of operation. As in all DC/DC applications,
the power supply source impedance must be small compared to the converter input impedance in order to
maintain the stability of the converter.
If the LM5160 is used in a buck topology with low input supply voltage (4.5 V) and large load current (1.5 A), it is
prudent to add a large electrolytic capacitor, in parallel the CIN capacitors. The electrolytic capacitor will stabilize
the input voltage to the IC and prevent droop or oscillation, over the entire load range.
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10 Layout
10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should
be observed:
• CIN: The loop consisting of input capacitor (CIN), VIN pin, and PGND pin carries the switching current.
Therefore, in both the LM5160 and the LM5160A, the input capacitor should be placed close to the IC,
directly across VIN and PGND pins, and the connections to these two pins should be direct to minimize the
loop area. In general it is not possible to place all of input capacitances near the IC. A good layout practice
includes placing the bulk capacitor as close as possible to the VIN pin (see Figure 36).When using the
LM5160-Q1 HTSSOP-14 package, a bypass capacitor measuring ~0.1 μF should be placed directly across
VIN and PGND (pin 3 and 2), as close as possible to the IC while complying with all layout design rules.
• CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and
low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the
connecting trace length and loop area should be minimized (see Figure 36).
• The feedback trace carries the output voltage information and a small ripple component that is necessary for
proper operation of both the LM5160 and the LM5160A. Therefore, care should be taken while routing the
feedback trace to avoid coupling any noise into this pin. In particular, the feedback trace should be short and
not run close to magnetic components, or parallel to any other switching trace.
• SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a source of
noise. The SW node area should be minimized. In particular, the SW node should not be inadvertently
connected to a copper plane or pour.
10.2 Layout Example
VIN
AGND
CIN
CIN
SW
PGND
SW
CBST
LM5160
VIN
BST
EN/
UVLO
VCC
VOUT
THERMAL
PAD
RON
FB
SS
FPWM
CVCC
RFB2
RFB1
Figure 36. Placement of Bypass Capacitors
26
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11 Device and Documentation Support
11.1 Related Documentation
AN-2292 Designing an Isolated Buck (Fly-Buck) Converter
AN-1481 Controlling Output Ripple & Achieving ESR Independence in Constant On-Time Regulator Designs
SPRA953 IC Package Thermal Metrics application report,
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
Fly-Buck, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM5160QPWPQ1
ACTIVE
HTSSOP
PWP
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
5160
QPWPQ1
LM5160QPWPRQ1
ACTIVE
HTSSOP
PWP
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
5160
QPWPQ1
LM5160QPWPTQ1
ACTIVE
HTSSOP
PWP
14
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
5160
QPWPQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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14-Oct-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5160-Q1 :
• Catalog: LM5160
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM5160QPWPRQ1
HTSSOP
PWP
14
2500
330.0
12.4
LM5160QPWPTQ1
HTSSOP
PWP
14
250
178.0
12.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.95
5.6
1.6
8.0
12.0
Q1
6.95
5.6
1.6
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5160QPWPRQ1
HTSSOP
PWP
14
2500
367.0
367.0
35.0
LM5160QPWPTQ1
HTSSOP
PWP
14
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
PWP0014A
MXA14A (Rev A)
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