CS44130
60 W Quad Half-Bridge Digital Amplifier Power Stage
Features
Configurable Outputs (10% THD+N)
–
–
–
–
Single (+10.8 V to +21 V) High Voltage Supply
2 x 30 W into 8 Ω, Full-Bridge
1 x 60 W into 4 Ω, Parallel Full-Bridge
4 x 15 W into 4 Ω, Half-Bridge
2 x 15 W into 4 Ω, Half-Bridge + 1 x 30 W
into 8 Ω, Full-Bridge
Space-Efficient, Thermally-Enhanced QFN
Package
High Efficiency (90%)
Low RDS(ON)
Low Quiescent Current
Low Power Standby Mode
Common Applications
®
PWM Popguard Technology for Quiet Startup
> 100 dB Dynamic Range - System Level
MP3 Docking Stations
< 0.12% THD+N @ 1 W - System Level
Mini Shelf Systems
Built-In Protection with Error Reporting
–
–
–
–
Digital Televisions
Networked Audio/POE Systems
Over-Current
Thermal Warning
Thermal Fault
Under-Voltage
Desktop Speakers
General Description provided on page 2.
VD
VL
IN[4:1]
VP
Non-Overlap
Time Insertion
Level Shifters
Gate
Drivers
OUT[4:1]
PGND
GND
Protection and Error Reporting
(Open Drain with Internal Pull-ups)
Control Logic
M[3:1] OCREF LVD RAMP RST1/2
Preliminary Product Information
http://www.cirrus.com
RST3/4
ERROC1/2 ERROC3/4
ERRUVTE TWR
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
JULY '06
DS690PP1
CS44130
General Description
The CS44130 is a high-efficiency power stage for digital Class-D amplifiers designed to recieve PWM signals from
a modulator such as the CS44800/600. The power stage outputs can be configured as four half-bridge channels,
two half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full-bridge channel.
The CS44130 integrates on-chip protection for over-current, under-voltage, and over-temperature events. Addtionally, it integrates error reporting for these events, as well any thermal warning events. The low RDS(ON) of the outputs
allows the part to operate at up to 90% efficiency. This efficiency provides for a smaller device package, no heat
sink requirements, and smaller power supplies.
The CS44130 is available in a 48-pin QFN package for commercial grades (-10° to +70° C). The CRD44130-FB is
also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on
page 23 for complete ordering information.
2
DS690PP1
CS44130
TABLE OF CONTENTS
1. PIN DESCRIPTION ............................................................................................................................... 4
1.1 I/O Pin Characteristics ................................................................................................................... 6
2. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 7
SPECIFIED OPERATING CONDITIONS .............................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7
DC ELECTRICAL CHARACTERISTICS ............................................................................................... 8
PWM OUTPUT CHARACTERISTICS ................................................................................................... 9
DIGITAL INTERFACE CHARACTERISTICS ........................................................................................ 9
3. TYPICAL CONNECTION DIAGRAMS .............................................................................................. 10
4. APPLICATIONS .................................................................................................................................. 14
4.1 Overview ....................................................................................................................................... 14
4.2 Feature Set Summary .................................................................................................................. 14
4.3 Output Mode Configuration .......................................................................................................... 15
4.4 Output Filter .................................................................................................................................. 16
4.4.1 Half-Bridge Output Filter .................................................................................................. 16
4.4.2 Full-Bridge Output Filter (Stereo or Parallel) .................................................................... 17
4.5 Protection and Error Reporting ..................................................................................................... 18
4.5.1 Over-Current Protection ................................................................................................... 18
4.5.2 Under-Voltage and Thermal Protection ........................................................................... 18
5. RESET AND POWER-UP .................................................................................................................... 19
5.1 PWM Popguard Transient Control ................................................................................................ 19
5.2 Recommended Power-Up Sequence ........................................................................................... 19
5.3 Recommended Power-Down Sequence ....................................................................................... 19
6. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ...................................................................... 20
7. PARAMETER DEFINITIONS ............................................................................................................... 20
8. PACKAGE DIMENSIONS ................................................................................................................. 21
9. THERMAL CHARACTERISTICS ........................................................................................................ 22
9.1 Thermal Flag ................................................................................................................................ 22
10. ORDERING INFORMATION ............................................................................................................. 23
11. REFERENCES ................................................................................................................................... 23
12. REVISION HISTORY ......................................................................................................................... 23
LIST OF FIGURES
Figure 1. Typical Connection Diagram - Stereo Full-Bridge....................................................................... 10
Figure 2. Typical Connection Diagram - 2.1 Channels (2 x Half-Bridge + 1 x Full-Bridge) ........................ 11
Figure 3. Typical Connection Diagram - 4-Channel Half-Bridge ................................................................ 12
Figure 4. Typical Connection Diagram - Mono Parallel Full-Bridge ........................................................... 13
Figure 5. Output Filter - Half-Bridge ........................................................................................................... 16
Figure 6. Output Filter - Full-Bridge............................................................................................................ 17
LIST OF TABLES
Table 1. Output Mode Configuration Options............................................................................................. 15
Table 2. Low-Pass Filter Components - Half-Bridge.................................................................................. 16
Table 3. DC-Blocking Capacitors Values - Half-Bridge.............................................................................. 16
Table 4. Low-Pass Filter Components - Full-Bridge .................................................................................. 17
Table 5. Over-Current Error Conditions ..................................................................................................... 18
Table 6. Thermal and Under-Voltage Error Conditions.............................................................................. 18
DS690PP1
3
CS44130
4
PGND
PGND
PGND
VP
PGND
RST1/2
ERROC1/2
M1
M2
M3
VL
48
47
46
45
44
43
42
41
40
39
38
37
VP
1
36
GND
OUT1
2
35
VD
PGND
3
34
IN1
VP
4
33
GND
OUT2
5
32
VD
PGND
6
31
IN2
PGND
7
30
LVD
OUT3
8
29
IN3
VP
9
28
VD
PGND
10
27
GND
OUT4
11
26
IN4
VP
12
25
VD
Pin Name
Pin #
VP
1
4
9
12
44
PGND
PGND
1. PIN DESCRIPTION
PGND
PGND
PGND
TWR
ERRUVTE
19
20
21
22
23
24
RAMP
18
RST3/4
17
ERROC3/4
16
GND
15
VD
14
OCREF
13
PGND
Thermal Pad
Pin Description
High Voltage Output Power (Input) - High voltage power supply for the individual output power
half-bridge devices.
3, 6
7, 10
13, 14
Power Ground (Input) - Ground for the individual output power half-bridge devices. These pins
15, 16
should be connected to the common system ground.
43, 45
46, 47
48
DS690PP1
CS44130
Pin Name
VD
Pin #
Pin Description
20, 25
28, 32 Core Logic Power (Input) - Low voltage power supply for internal logic.
35
VL
37
Control Interface and PWM Input Power (Input) - Supply for the I/O.
GND
21
27
33
36
Ground (Input) - Ground for the internal logic and I/O. These pins should be connected to the
common system ground.
OUT1
OUT2
OUT3
OUT4
2
5
8
11
PWM Output (Output) - Amplified PWM power half-bridge outputs.
IN1
IN2
IN3
IN4
34
31
29
26
PWM Input (Input) - Inputs from a PWM modulator. These pins should not be left floating.
RST1/2
RST3/4
42
23
Reset Input (Input) - Reset inputs for channel 1, 2, 3, and 4; active low. These pins should not be
left floating.
ERROC1/2
ERROC3/4
41
22
Over-Current Error Output (Output) - Over-current error flag for OUTx. Open drain with internal
pull-up, active low. See Protection and Error Reporting on page 18 for details.
ERRUVTE
18
Thermal and Under-Voltage Error Output (Output) - Error flag for thermal shutdown and undervoltage. Open drain with internal pull-up, active low. See Protection and Error Reporting on
page 18 for details.
TWR
17
Thermal Warning Output (Output) - Thermal warning output. Open drain with internal pull-up,
active low. See Protection and Error Reporting on page 18 for details.
LVD
30
Input Voltage Level Select (Output) - Input voltage indicator of VD. A high level indicates VD is
set to 5.0 V. A low level indicates VD is set to 3.3 V. This pins should not be left floating.
M1
M2
M3
40
39
38
OCREF
19
Over-Current Reference (Input) - Over-current trip level setting. This pin should be connected
through a 60 kΩ resistor to GND. See Protection and Error Reporting on page 18 for details.
This pins should not be left floating.
24
Ramp-Up/Down Select (Input) - When set high, ramping is enabled. When set low, ramping is
disabled. See PWM Popguard Transient Control on page 19 for details. This pin should not
be left floating. Ramp should only be used in half bridge mode or in full bridge configuration
modes 010 and 011.
RAMP
DS690PP1
Mode Select (Input) - Used to set the operating mode. See Output Mode Configuration on
page 15 for details. These pins should not be left floating.
5
CS44130
1.1
I/O Pin Characteristics
Signal Name Power Rail
I/O
Driver
Receiver
OUT1
VP
Output
10.8 V-21.0 V Power MOSFET
-
OUT2
VP
Output
10.8 V-21.0 V Power MOSFET
-
OUT3
VP
Output
10.8 V-21.0 V Power MOSFET
-
OUT4
VP
Output
10.8 V-21.0 V Power MOSFET
-
IN1
VL
Input
-
2.5 V to 5.0 V Compatible.
IN2
VL
Input
-
2.5 V to 5.0 V Compatible.
IN3
VL
Input
-
2.5 V to 5.0 V Compatible.
IN4
VL
Input
-
2.5 V to 5.0 V Compatible.
RST1/2
VL
Input
-
2.5 V to 5.0 V Compatible.
RST3/4
VL
Input
-
2.5 V to 5.0 V Compatible.
ERROC1/2
VL
Output
Open Drain, Internal pull-up
-
ERROC3/4
VL
Output
Open Drain, Internal pull-up
-
ERRUVTE
VL
Output
Open Drain, Internal pull-up
-
TWR
VL
Output
Open Drain, Internal pull-up
-
LVD
VL
Input
-
2.5 V to 5.0 V Compatible.
RAMP
VL
Input
-
2.5 V to 5.0 V Compatible.
M1
VL
Input
-
2.5 V to 5.0 V Compatible.
M2
VL
Input
-
2.5 V to 5.0 V Compatible.
M3
VL
Input
-
2.5 V to 5.0 V Compatible.
All input pins should be connected and not left floating.
6
DS690PP1
CS44130
2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND/PGND = 0 V, all voltages with respect to ground, unless otherwise specified)
Parameter
Symbol
Min
Typ
Max
Units
Power Stage Supply
VP
Core Logic
3.3 V
5.0 V
VD
Control Interface and PWM Inputs
2.5 V
3.3 V
5.0 V
VL
10.8
3.14
4.75
2.37
3.14
4.75
3.3
5.0
2.5
3.3
5.0
21.0
3.47
5.25
2.63
3.47
5.25
V
V
V
V
V
V
-10
-
+70
°C
-
+150
°C
DC Power Supply
PWM Outputs
Ambient Operating Temperature
Commercial
-CNZ
TA
TJ
Junction Temperature
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
(GND/PGND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Input Current
Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
Symbol
PWM Outputs
Core Logic
Control Interface and PWM Inputs
(Note 1)
(Note 2)
Commercial
VP
VD
VL
Iin
VIN
TA
Tstg
Min
-0.3
-0.3
-0.3
-0.4
-20
Max
23.0
7.0
7.0
±10
VL+0.4
+85
Units
-65
+150
°C
V
V
V
mA
V
°C
Notes:
1. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-up.
2. The maximum over/under-voltage is limited by the input current.
DS690PP1
7
CS44130
DC ELECTRICAL CHARACTERISTICS
(GND/PGND = 0 V, all voltages with respect to ground; PWM Switch Rate = 384 kHz unless otherwise specified.
VD = 3.3 V and VL = 3.3 V, unless otherwise specified.)
Parameter
Symbol
Min
Typ
Max
VL = 2.5 V
VL = 3.3 V
VL = 5.0 V
VD = 3.3 V
VD = 5.0 V
VL = 2.5 V
VL = 3.3 V
VL = 5.0 V
VD = 3.3 V
VD = 5.0 V
IL
IL
IL
ID
ID
Pdl
Pdl
Pdl
Pdd
Pdd
-
0.29
0.01
2.29
1.60
2.00
6.00
5.30
16.73
5.30
10.00
-
VL = 2.5 V
VL = 3.3 V
VL = 5.0 V
VD = 3.3 V
VD = 5.0 V
IL
IL
IL
ID
ID
-
17.10
16.80
16.40
1.30
1.50
-
Units
Normal Operation (Note 3)
Power Supply Current (Note 4)
Power Dissipation (Ptotal = Pdl + Pdd)
mA
mW
Power-Down Mode (Note 5)
Power Supply Current
µA
µA
µA
nA
nA
3. Normal operation is defined with RSTx/y = HI.
4. Current consumption increases with increasing PWM switch rates.
5. Power-Down Mode is defined as RSTx/y = LOW with all input lines held low.
8
DS690PP1
CS44130
PWM OUTPUT CHARACTERISTICS
(Unless otherwise noted: GND/PGND = 0 V, all voltages with respect to ground, VP = 21 V, RL = 8 Ω in Full-Bridge
Mode, RL = 4 Ω in Half-Bridge Mode, PWM Switch Rate = 384 kHz, Modulation Index = 0.88; Measurement bandwidth is 10 Hz to 20 kHz; Performance measurements taken with a full scale 997 Hz and AES17 filter.)
Parameters
Power Output per Channel
Symbol
Conditions
Min
Typ
Max
PO
THD+N =10%
THD+N =1%
THD+N = 10%
THD+N = 1%
THD+N = 10%
THD+N = 1%
-
15
11
30
20
60
40
-
PO = 1 W
PO =7.8 W (0 dBFS)
PO = 1 W
PO = 15.9 W (0 dBFS)
PO = 1 W
PO = 30.8 W (0 dBFS)
-
.20
.35
.12
.19
.14
.29
-
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
PO = -60 dBFS, A-Weighted
PO = -60 dBFS, Unweighted
Id = 1 A, TA = 25°C
0 dBFS PO = 2 x 24 W
No Load
Resistive Load
Resistive Load
-
102
99
107
105
102
99
450
90
60
20
20
125
150
6
1.5
50
550
-
Half-Bridge
Full-Bridge
Parallel Full-Bridge
Units
W
Total Harmonic Distortion + Noise
Half-Bridge
Full-Bridge THD+N
Parallel Full-Bridge
%
Dynamic Range
Half-Bridge
Full-Bridge
DR
Parallel Full-Bridge
MOSFET On Resistance
Efficiency (Full Bridge)
Minimum Output Pulse Width
Rise Time of OUTx
Fall Time of OUTx
Junction Thermal Warning Trip Point
Junction Overtemperature Trip Point
VP Under-voltage Trip Point
Ramp Up Time (Half-Bridge Mode)
Ramp Down Time (Half-Bridge Mode)
RDS(ON)
h
PWmin
tr
tf
TTW
TOT
VUV
TRU
TRD
TA = 25°C
DC Blocking Cap = 1000 µF
DC Blocking Cap = 1000 µF
dB
mΩ
%
ns
ns
ns
°C
°C
V
s
s
DIGITAL INTERFACE CHARACTERISTICS
(GND/PGND = 0 V, all voltages with respect to ground)
Parameters
High-Level Input Voltage
Low-Level Input Voltage
Low-Level Output Voltage at Io=2 mA
Input Leakage Current
Input Capacitance
DS690PP1
Symbol
(% of VL)
VIH
(% of VL)
VIL
(% of VL) VOL
Iin
Min
70%
-
Typ
-
Max
30%
20%
±10
8
Units
V
V
V
µA
pF
9
CS44130
3. TYPICAL CONNECTION DIAGRAMS
VD (+3.3 V or +5.0 V)
47 µF
VP (+10.8 V to +21 V)
0.1 µF (X5)
0.1 µF
VD VD VD VD VD VP
VL (+2.5 V, +3.3 V, or +5.0 V)
VP
VP
VL
0.1 µF
0.1 µF
PWM1+
IN1
PWM2+
IN2
PWM3+
IN3
PWM4+
IN4
Output
Filter
OUT1
PGND
VP
0.1 µF
CS44130
470 µF
M1
Hardware
Control
Settings
M2
OUT2
M3
PGND
Output
Filter
LVD
RAMP
VP
VP
0.1 µF
RST1/2
Output
Filter
OUT3
RST3/4
System
Control
Logic
PGND
ERROC1/2
ERROC3/4
VP
ERRUVTE
0.1 µF
470 µF
TWR
OUT4
OCREF
Output
Filter
PGND
60K
GND GND GND GND GND
Figure 1. Typical Connection Diagram - Stereo Full-Bridge
10
DS690PP1
CS44130
VD (+3.3 V or +5.0 V)
47 µF
VP (+10.8 V to +21 V)
0.1 µF (X5)
0.1 µF
VD VD VD VD VD VP
VP
VP
VL (+2.5 V, +3.3 V, or +5.0 V)
VL
0.1 µF
470 µF
0.1 µF
PWM1+
IN1
PWM2+
IN2
PWM3+
IN3
PWM4+
IN4
Output
Filter
OUT1
PGND
VP
VP
0.1 µF
CS44130
470 µF
M1
Hardware
Control
Settings
M2
OUT2
M3
PGND
Output
Filter
LVD
RAMP
VP
VP
0.1 µF
RST1/2
Output
Filter
OUT3
RST3/4
System
Control
Logic
PGND
ERROC1/2
ERROC3/4
VP
ERRUVTE
0.1 µF
470 µF
TWR
OUT4
OCREF
Output
Filter
PGND
60K
GND GND GND GND GND
Figure 2. Typical Connection Diagram - 2.1 Channels (2 x Half-Bridge + 1 x Full-Bridge)
DS690PP1
11
CS44130
VD (+3.3 V or +5.0 V)
47 µF
VP (+10.8 V to +21 V)
0.1 µF (X5)
0.1 µF
VD VD VD VD VD VP
VP
VP
VL (+2.5 V, +3.3 V, or +5.0 V)
VL
0.1 µF
470 µF
0.1 µF
PWM1+
IN1
PWM2+
IN2
PWM3+
IN3
PWM4+
IN4
Output
Filter
OUT1
PGND
VP
VP
0.1 µF
M1
Hardware
Control
Settings
470 µF
CS44130
M2
OUT2
M3
PGND
LVD
RAMP
Output
Filter
VP
VP
0.1 µF
470 µF
RST1/2
Output
Filter
OUT3
RST3/4
System
Control
Logic
PGND
ERROC1/2
VP
ERROC3/4
VP
ERRUVTE
0.1 µF
470 µF
TWR
OUT4
OCREF
Output
Filter
PGND
60K
GND GND GND GND GND
Figure 3. Typical Connection Diagram - 4-Channel Half-Bridge
12
DS690PP1
CS44130
VD (+3.3 V or +5.0 V)
47 µF
VP (+10.8 V to +21 V)
0.1 µF (X5)
0.1 µF
VD VD VD VD VD VP
VP
VP
VL (+2.5 V, +3.3 V, or +5.0 V)
VL
0.1 µF
0.1 µF
PWM1+
IN1
PWM2+
IN2
PWM3+
IN3
PWM4+
IN4
OUT1
PGND
VP
0.1 µF
M1
Hardware
Control
Settings
470 µF
CS44130
M2
OUT2
M3
PGND
Output
Filter
LVD
RAMP
VP
0.1 µF
RST1/2
Output
Filter
OUT3
RST3/4
System
Control
Logic
PGND
ERROC1/2
ERROC3/4
VP
ERRUVTE
0.1 µF
TWR
OUT4
OCREF
60K
PGND
GND GND GND GND GND
Figure 4. Typical Connection Diagram - Mono Parallel Full-Bridge
DS690PP1
13
CS44130
4. APPLICATIONS
4.1
Overview
The CS44130 is a high-efficiency power stage for digital Class-D amplifiers. It has been designed to be configured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge
channels, or one parallel full-bridge channel.
The CS44130 integrates on-chip protection for over-current, under-voltage, and over-temperature events.
Addtionally, it integrates error reporting for these events, as well any thermal warning events. The low
RDS(ON) of the outputs allows the part to operate at up to 90% efficiency. This efficiency provides for a smaller device package, no heat sink requirements, and smaller power supplies.
The CS44130 is ideal for digital audio systems requiring space-efficient, high quality audio, such as Digital
Televisions, MP3 Docking Stations, Mini Shelf Systems, and Desktop Speakers.
4.2
14
Feature Set Summary
•
VD voltage pins for internal core logic levels between 3.3 V and 5.0 V.
•
VL voltage pin for PWM input, mode configuration, and error reporting logic levels between 2.5 V and
5.0 V.
•
VP voltage pin for PWM output levels between +10.8 V and +21 V.
•
Protection and Error Reporting for Over-current, Under-voltage, and Thermal Overload Protection
events.
•
PWM Popguard for Quiet Startup (valid for Half Bridge configurations only.)
DS690PP1
CS44130
4.3
Output Mode Configuration
The CS44130 can be configured for several modes of operation. Table 1 shows the setting of the M[3:1]
inputs and the corresponding mode of operation. These pins should remain static during operation (RSTx/y
set high).
M3 M2 M1
0
0
0
0
0
1
0
1
0
0
1
1
1
x
x
Output Mode
Auto-Reset
Description
When an error condition occurs on a channel, that channel is auto-reset until
the error condition is removed.
IN1 must be inverted from IN2 for full-bridge operation.
IN3 must be inverted from IN4 for full-bridge operation.
Latched Shutdown When an error condition occurs on a channel, that channel is shutdown until
the error condition is removed and the channel reset is toggled.
IN1 must be inverted from IN2 for full-bridge operation.
IN3 must be inverted from IN4 for full-bridge operation.
Auto-Reset with This mode should only be used for full-bridge applications.
Inversion
When an error condition occurs on a channel, that channel is auto-reset until
the error condition is removed.
IN2 is internally inverted for the second half-bridge.1
IN4 is internally inverted for the second half-bridge.1
Latched Shutdown This mode should only be used for full-bridge applications.
with Inversion
When an error condition occurs on a channel, that channel is shutdown until
the error condition is removed and the channel reset is toggled.
IN2 is internally inverted for the second half-bridge.1
IN4 is internally inverted for the second half-bridge.1
Reserved
This setting is reserved and should not be used.
Table 1. Output Mode Configuration Options
1. In modes 010 and 011, IN1 should be connected to IN2 (external to the chip) and driven with a single
PWM signal. Likewise, in these same modes, IN3 should be connected to IN4 (external to the chip) and
driven with a single PWM signal.
DS690PP1
15
CS44130
4.4
Output Filter
The RC filter placed after the PWM outputs can greatly affect the output performance. The filter not only
reduces radiated EMI (snubber filter) but also filters high-frequency content from the switching output before
going to the speaker (low-pass filter).
4.4.1
Half-Bridge Output Filter
Figure 5 shows the output filter for a half-bridge configuration. The transient-voltage suppression circuit,
(snubber circuit) is comprised of a resistor (5.6 Ω, 1/8 W) and capacitor (560 pF) and should be placed as
close as possible to the corresponding PWM output pin. This will greatly reduce radiated EMI.
VP
PWM
Output
L1
C2
+
-
5.6 Ω
560 pF
*Diode is Zetex
ZHCS400 or
equivalent
C1
Figure 5. Output Filter - Half-Bridge
The inductor, L1, and capacitor, C1, comprise the low-pass filter. Along with the nominal load impedance
of the speaker, these values set the cutoff frequency of the filter. Table 2 shows the component values for
L1 and C1 based on nominal speaker (load) impedance for a corner frequency (-3 dB point) of approximately 35 kHz.
Load
L1
C1
4Ω
22 µH
1.0 µF
6Ω
33 µH
0.68 µF
8Ω
47 µH
0.47 µF
Table 2. Low-Pass Filter Components - Half-Bridge
C2 is the DC-blocking capacitor. Table 3 shows the component values for C2 based corner frequency (3 dB point) and a nominal speaker (load) impedance of 4 Ω. This capacitor should also be chosen to have
a ripple current rating above the amount of current that will pass through it.
Corner Frequency
36 Hz
54 Hz
110 Hz
C2
1000 µF
680 µF
330 µF
Table 3. DC-Blocking Capacitors Values - Half-Bridge
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4.4.2
Full-Bridge Output Filter (Stereo or Parallel)
Figure 6 shows the output filter for a full-bridge configuration. The snubber resistor (20 Ω, 1/10 W) and
capacitor (330 pF), as well as the diodes, should be placed as close as possible to the corresponding
PWM output pins. This will greatly reduce radiated EMI. The inductors, L1 and L2, and capacitor, C1, comprise the low-pass filter. Along with the nominal load impedance of the speaker, these values set the cutoff
frequency of the filter. Table 4 shows the component values based on nominal speaker (load) impedance
for a corner frequency (-3 dB point) of approximately 35 kHz.
VP
+ PWM
Output
L1
*Diode is Zetex
ZHCS400 or
equivalent
20 Ω
330 pF
C1
VP
- PWM
Output
L2
Figure 6. Output Filter - Full-Bridge
Load
4Ω
6Ω
8Ω
L1 & L2
10 µH
15 µH
22 µH
C1
1.0 µF
0.47 µF
0.47 µF
Table 4. Low-Pass Filter Components - Full-Bridge
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CS44130
4.5
Protection and Error Reporting
The CS44130 has built-in protection circuitry for over-current, under-voltage, and thermal warning/overload
conditions. All error outputs are open-drain, active low, and can safely be tied together in any combination.
These pins also have internal pull-up resistors, alleviating the need for external resistors.
4.5.1
Over-Current Protection
Over-current errors are reported on the ERROCx/y pins (example: over-current error on OUT1 would be
reported on ERROC1/2). The over-current error is designed to go low for conditions that could potentially
damage the part. In order for ERROCx/y to go low only under conditions that could damage the part, it is
recommended that a 60 kΩ resistor be connected from the OCREF pin to ground. If the part has been
configured for latched shutdown, as specified in Table 1 on page 15, the channel which is reporting the
over-current condition will be shut down (OUTx set to HI-Z) until the error condition has been removed
and the RSTx/y for that channel has been cycled from low to high.
If the part has been configured for auto-reset, as specified in Table 1 on page 15, the channel which is
reporting the over-current condition will be shut down (OUTx set to HI-Z). After approximately 85 milliseconds, the part will try to re-enable the outputs. If the fault has been cleared, the unit will return to normal
operation. If the fault is still present, the outputs will remain disabled and the part will try again in approximately 85 milliseconds. After 5 unsuccessful attempts, the outputs will latch in the off (OUTx set to HI-Z)
condition and wait for RSTx/y to be reset.
ERROCx/y
Error Condition
0
Over-current error on channel x or channel y
1
Normal operation
Table 5. Over-Current Error Conditions
4.5.2
Under-Voltage and Thermal Protection
Table 6 shows the behavior of the TWR and ERRUVTE pins. When the junction temperature exceeds the
Junction Thermal Warning Trip Point (TTW, as specified in the “PWM Output Characteristics” on page 9),
the TWR pin will be set low. If the junction temperature continues to increase beyond the Junction Overtemperature Trip Point (TOT, as specified in the “PWM Output Characteristics” on page 9), the ERRUVTE
pin will be set low. If the voltage on VP falls below the VP Under-voltage Trip Point (VUV, as specified in
the “PWM Output Characteristics” on page 9), ERRUVTE will be set low.
If the part has been configured for auto-reset, as specified in Table 1 on page 15, the channel which is
reporting the over-current condition will be shut down (OUTx set to HI-Z). After approximately 85 milliseconds, the part will try to re-enable the outputs. If the fault has been cleared, the unit will return to normal
operation. If the fault is still present, the outputs will remain disabled and the part will try again in approximately 85 milliseconds. After 5 unsuccessful attempts, the outputs will latch in the off (OUTx set to HI-Z)
condition and wait for RSTx/y to be reset.
TWR
ERRUVTE
Error Condition
0
0
Thermal warning and thermal error and/or under-voltage error.
0
1
Thermal warning only.
1
0
Under-voltage error.
1
1
Normal operation.
Table 6. Thermal and Under-Voltage Error Conditions
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5. RESET AND POWER-UP
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, and
configuration pins are stable. It is also recommended that the RSTx/y pin be activated if the voltage supplies
drop below the recommended operating condition to prevent power-glitch- related issues.
When RSTx/y is low, the corresponding channels of the CS44130 enter a low-power mode and all internal
states are reset and the outputs are set to HI-Z. When RSTx/y is high, the desired mode settings will be
loaded and the outputs will begin normal operation.
5.1
PWM Popguard Transient Control
The CS44130 uses Popguard® technology to minimize the effects of output transients during power-up
and power-down for half-bridge configurations. This technique reduces the audio transients commonly
produced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors
connected in series with the audio outputs.
When the device is configured for ramping (RAMP set high) and RSTx/y is set high and the inputs are
pulsed, the OUTx output will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time
for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient. The OUTx output will not begin normal operation until the ramp has reached the bias point. The INx
input must begin switching before the ramp cycle begins.
When the device is configured for ramping (RAMP set high) and RSTx/y is set low, the OUTx output will
begin to slowly ramp down from the bias point to PGND, allowing the DC-blocking capacitor to discharge.
It is not necessary to complete a ramp up/down sequence before ramping up/down again. PWM Popguard
should only be used in Half Bridge configurations.
5.2
Recommended Power-Up Sequence
1. Turn on the system power.
2. Hold RSTx/y low until the power supply and system clocks are stable. In this state, all associated
outputs are HI-Z.
3. Start the PWM modulator output.
4. Once the PWM modulator output is valid, release RSTx/y high. If the CS44130 is configured for
ramping, the outputs will ramp to the bias point and then begin switching normally. If the CS44130 is
not configured for ramping, the outputs will begin switching after approximately 35 cycles of the PWM
input signal.
5.3
Recommended Power-Down Sequence
1. Set RSTx/y low. If the CS44130 is configured for ramping, the outputs will ramp down to PGND and
then become HI-Z. If the CS44130 is not configured for ramping, the outputs will immediately become
HI-Z.
2. Power-down the remainder of the system.
3. Turn off the system power.
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CS44130
6. POWER SUPPLY, GROUNDING, AND PCB LAYOUT
The CS44130 requires a 3.3 V or 5.0 V digital power supply for the core logic. In order to support a number of PWM
frontend solutions, a separate VL power pin is provided to condition the interface signals to support up to 5.0 V levels. The VL power pins control the voltage levels for all PWM input, mode, and error reporting signals.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. It is necessary to decouple the power supply by placing capacitors directly between the
power and ground of the CS44130. The recommended procedure is to place a 0.1 µF capacitor as close as physically possible to each power pin. Decoupling capacitors should be as near to the pins of the CS44130 as possible,
with the low value ceramic capacitor being the nearest and should be mounted on the same side of the board as the
CS44130 to minimize inductance effects
7. PARAMETER DEFINITIONS
Dynamic Range (DR)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer
the measurement to full-scale, with units in dBFS. This measurement can be made “weighted” or “unweighted”. The weighting that was used during for the test is usually indicated by a letter following the units.
For instance, “dBFS A” would indicate that an A-weighted filter was used during testing.
This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Frequency Response (FR)
FR is the deviation in signal level versus frequency. The 0 dB reference point is 1 kHz. The amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed
minimum and maximum frequencies are guaranteed to be within the AC from minimum frequency to maximum frequency inclusive.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
FFT
Fast Fourier Transform.
Fs
Sampling Frequency.
Signal to Noise Ratio (SNR)
SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor, in
the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB.
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in %.
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8. PACKAGE DIMENSIONS
48L QFN (9 × 9 MM BODY) PACKAGE DRAWING
e
b
D
Pin #1 ID
Pin #1 ID
E
E2
A1
L
D2
A
Top View
Side View
Bottom View
INCHES
DIM
A
A1
b
D
D2
E
E2
e
L
MIN
-0.0000
0.0118
0.2618
0.2618
0.0177
NOM
--0.0138
0.3543 BSC
0.2677
0.3543 BSC
0.2677
0.0256 BSC
0.0217
MILLIMETERS
MAX
0.0354
0.0020
0.0157
MIN
-0.00
0.30
0.2736
6.65
0.2736
6.65
0.0276
0.45
NOM
--0.35
9.00 BSC
6.80
9.00 BSC
6.80
0.65 BSC
0.55
NOT
E
MAX
0.90
0.05
0.40
6.95
6.95
0.70
1
1
1,2
1
1
1
1
1
1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
Notes:
1. Dimensioning and tolerance per ASME Y4.5M - 1994.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
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CS44130
9. THERMAL CHARACTERISTICS
Parameter
Junction to Case Thermal Impedance
Junction to Ambient Thermal Impedance (Note 1)
2-Layer PCB
4-Layer PCB
Symbol
Min
Typ
Max
θJC
-
1
20
18.5
-
θJA
Units
°C/Watt
°C/Watt
1. θJA is stated for a system with a thermal flag as described in Section 9.1 below.
9.1
Thermal Flag
This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane on the
PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be coupled with vias to
a large metal plane on the backside (and inner ground layer, if applicable) of the PCB.
In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those immediately surrounding the CS44130. In addition to improving in electrical performance, this practice also aids in heat
dissipation.
The heat dissipation capability required of the metal plane for a given output power can be calculated as follows:
TCA = [(TJ(MAX) - TA) / PD] - θJC
where,
TCA = Thermal resistance of the metal plane in °C/Watt
TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150 °C
TA = Ambient temperature in °C
PD = RMS power dissipation of the device, equal to 0.10*PRMS (assuming 90% efficiency)
θJC = Junction-to-case thermal resistance of the device in °C/Watt
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CS44130
10.ORDERING INFORMATION
Product
CS44130
Description
Package
Quad Half-Bridge
Digital Amplifier
Power Stage
PbFree
Grade
Temp Range Container
Rail
48-QFN
Yes
-
-
CRD44130-FB 20 W x 2 + 40 W x 1
Reference Design
Order#
CS44130-CNZ
Commercial -10° to +70°C Tape and
CS44130-CNZR
Reel
-
-
-
CRD44130-FB
11.REFERENCES
1. Cirrus Logic, AN018: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,
Version 6.0, February 1998.
12.REVISION HISTORY
Release
A1
Date
Changes
September 2005 Initial Advance Release
A2
April 2006
P1
July 2006
2nd Advance Release
-Updated “Features” on page 1
-Updated “Specified Operating Conditions” on page 7
-Updated “Absolute Maximum Ratings” on page 7
-Updated “PWM Output Characteristics” on page 9
-Updated “Protection and Error Reporting” on page 18
-Updated “Thermal Characteristics” on page 22
Preliminary Datasheet Release
-Updated “DC Electrical Characteristics” on page 8
-Updated “PWM Output Characteristics” on page 9
-Updated “Thermal Characteristics” on page 22
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus")
believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS"
without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment,
including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use
of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of
Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such
as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
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