STMicroelectronics M24M02-DR 2-mbit serial ic bus eeprom Datasheet

M24M02-DR
2-Mbit serial I²C bus EEPROM
Datasheet - production data
Features
SO8 (MN)
150 mil width
WLCSP
• Compatible with all I2C bus modes:
– 1 MHz
– 400 kHz
– 100 kHz
• Memory array:
– 2 Mbit (256 Kbyte) of EEPROM
– Page size: 256 byte
– Additional Write lockable page
• Single supply voltage:
– 1.8 V to 5.5 V over –40 °C / +85 °C
•
Write:
– Byte Write within 10 ms
– Page Write within 10 ms
• Random and sequential Read modes
• Write protect of the whole memory array
• Enhanced ESD/Latch-Up protection
• More than 4 million Write cycles
• More than 200-years data retention
Packages
• SO8 ECOPACK2®
• WLCSP ECOPACK2®
July 2015
This is information on a product in full production.
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www.st.com
Contents
M24M02-DR
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.2
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
4.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.3
Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.4
Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.5
ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 17
5.1.6
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1
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Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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M24M02-DR
Contents
5.2.2
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.3
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.4
Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.5
Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.1
SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.2
WLCSP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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3
List of tables
M24M02-DR
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
4/38
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signals vs. bump position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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M24M02-DR
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO8 connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WLCSP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13.
Maximum Rbus value versus bus parasitic capacitance Cbus) for
an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 31
SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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5
Description
1
M24M02-DR
Description
The M24M02-DR is a 2 Mbit I2C-compatible EEPROM (Electrically Erasable
PROgrammable Memory) organized as 256 K × 8 bits.
The M24M02-DR can operate with a supply voltage from 1.8 V to 5.5 V, over an ambient
temperature range of –40 °C / +85 °C.
The M24M02-DR offers an additional page, named the Identification Page (256 byte). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
6##
%
3#,
3$!
-- $2
7#
633
!)
Table 1. Signal names
Signal name
Function
Direction
E2
Chip Enable
Input
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
-
VSS
Ground
-
Figure 2. SO8 connections, top view
$5
6 ##
$5
7#
%
3#,
6 33
3$!
!)V
1. DU: Don’t use (no signal should be applied on this pin; if connected, must be connected to VSS)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1
6/38
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M24M02-DR
Description
Figure 3. WLCSP connections
$
$
%
%
&
&
'
'
0DUNLQJVLGH
WRSYLHZ
%XPSVLGH
ERWWRPYLHZ
069
1. DU: Don’t use (no signal should be applied on this pin; if connected, must be connected to Vss)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Table 2. Signals vs. bump position
Position
A
B
C
D
1
-
-
SCL
-
2
VCC
WC
-
SDA
3
DU
-
-
VSS
4
-
DU
E2
-
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Signal description
M24M02-DR
2
Signal description
2.1
Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2
Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected (Figure 12 indicates how to calculate the
value of the pull-up resistor).
2.3
Chip Enable (E2)
This input signal is used to set the value that is to be looked for on the bit b3 of the 7-bit
device select code. This input must be tied to VCC or VSS, to establish the device select
code as shown in Figure 4. When not connected (left floating), this input is read as low (0
Figure 4. Chip enable inputs connection
9&&
9&&
0[[[
0[[[
(L
(L
966
2.4
966
$L
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
2.5
VSS (ground)
VSS is the reference for the VCC supply voltage.
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M24M02-DR
Signal description
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2
Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters).
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
parameters).
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4
Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
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Memory organization
3
M24M02-DR
Memory organization
The memory is organized as shown below.
Figure 5. Block diagram
7#
%
(IGH VOLTAGE
GENERATOR
#ONTROL LOGIC
3#,
3$!
)/ SHIFT REGISTER
$ATA
REGISTER
9 DECODER
!DDRESS REGISTER
AND COUNTER
PAGE
)DENTIFICATION PAGE
8 DECODER
-36
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4
Device operation
Device operation
The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 6. I2C bus protocol
3#,
3$!
3$!
)NPUT
34!24
#ONDITION
3#,
3$!
-3"
3$!
#HANGE
34/0
#ONDITION
!#+
34!24
#ONDITION
3#,
3$!
-3"
!#+
34/0
#ONDITION
!)"
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Device operation
4.1
M24M02-DR
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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4.5
Device operation
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 3 (most significant bit first).
Table 3. Device select code
Chip
Enable
Device type identifier(1)
MSB address
bits
RW
b7
b6
b5
b4
b3
b2
b1
b0
Device select code
when addressing
the memory array
1
0
1
0
E2(2)
A17
A16
RW
Device select code
when addressing
the Identification
page
1
0
1
1
E2(2)
X
X
RW
1. The most significant bit, b7, is sent first.
2. E2 bit value is compared to the logic level applied on the input pin E2.
When the device select code is received, the device only responds if the Chip Enable
Address is the same as the value on the Chip Enable (E2) input.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
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Instructions
M24M02-DR
5
Instructions
5.1
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Table 4. Most significant address byte
A15
A14
A13
A12
A11
A10
A9
A8
A1
A0
Table 5. Least significant address byte
A7
A6
A5
A4
A3
A2
The 256 Kbytes (2 Mb) are addressed with 18 address bits, the 16 lower address bits being
defined by the two address bytes and the most significant address bits (A17, A16) being
included in the Device Select code (see Table 4).
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 8.
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M24M02-DR
Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 7.
Figure 7. Write mode sequences with WC = 0 (data write enabled)
7#
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5.1.1
Instructions
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Instructions
5.1.2
M24M02-DR
Page Write
The Page Write mode allows up to 256 byte to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A17/A8, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 256 byte of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 8. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 8. Write mode sequences with WC = 1 (data write inhibited)
7#
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16/38
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M24M02-DR
5.1.3
Instructions
Write Identification Page
The Identification Page (256 byte) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
•
Device type identifier = 1011b
•
MSB address bits A17/A8 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A7/A0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
5.1.4
Lock Identification Page
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
5.1.5
•
Device type identifier = 1011b
•
Address bit A10 must be ‘1’; all other address bits are don't care
•
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
ECC (Error Correction Code) and Write cycling
The Error Correction Code (ECC) is an internal logic function which is transparent for the
I2C communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes(1). Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(1). As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined Table 10: Cycling performance.
1. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
DocID18204 Rev 8
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37
Instructions
5.1.6
M24M02-DR
Minimizing Write delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time
is shorter. To make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in Figure 9, is:
•
Initial condition: a Write cycle is in progress.
•
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
•
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 9. Write cycle polling flowchart using ACK
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1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the
figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling
instruction in the figure).
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DocID18204 Rev 8
M24M02-DR
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 10. Read mode sequences
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5.2
Instructions
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Instructions
5.2.1
M24M02-DR
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
5.2.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 10, without acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the byte location in the Identification page, therefore the next Current
Address Read in the memory uses this new address counter value. When accessing the
memory, it is safer to always use the Random Address Read instruction (this instruction
loads the address counter with the byte location to read in the memory, see Section 5.2.1)
instead of the Current Address Read instruction.
5.2.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 10.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
5.2.4
Read Identification Page
The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A17/A8 are don't
care, the LSB address bits A7/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 100d, the number of bytes should be less than
or equal to 156, as the ID page boundary is 256 bytes).
20/38
DocID18204 Rev 8
M24M02-DR
5.2.5
Instructions
Read the lock status
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
•
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
•
Stop: the device is then set back into Standby mode by the Stop condition.
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Initial delivery state
6
M24M02-DR
Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
22/38
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M24M02-DR
7
Maximum rating
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 6. Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
(1)
°C
Lead temperature during soldering
IOL
DC output current (SDA = 0)
VIO
Input or output range
VCC
Supply voltage
VESD
Electrostatic pulse (Human Body
see note
-
model)(2)
mA
–0.50
6.5
V
–0.50
6.5
V
-
3000
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS
directive 2011/65/EU of July 2011).
2. Positive and negative pulses applied on different combinations of pin connections, according to AECQ100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012 standard, C1=100 pF, R1=1500 Ω).
DocID18204 Rev 8
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DC and AC parameters
8
M24M02-DR
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 7. Operating conditions
Symbol
VCC
TA
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Max.
Unit
Table 8. AC measurement conditions
Symbol
Cbus
Parameter
Min.
Load capacitance
100
-
pF
-
SCL input rise/fall time, SDA input fall time
50
ns
-
Input levels
0.2 VCC to 0.8 VCC
V
-
Input and output timing reference levels
0.3 VCC to 0.7 VCC
V
Figure 11. AC measurement I/O waveform
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Table 9. Input parameters
Symbol
Parameter(1)
Test condition
Min.
Max.
Unit
CIN
Input capacitance (SDA)
-
-
8
pF
CIN
Input capacitance (other pins)
-
-
6
pF
VIN < 0.3 VCC
30
-
kΩ
VIN > 0.7 VCC
500
-
kΩ
ZL
ZH
Input impedance (E2, WC)(2)
1. Characterized only, not tested in production.
2.
24/38
input impedance when the memory is selected (after a Start condition).
DocID18204 Rev 8
M24M02-DR
DC and AC parameters
Table 10. Cycling performance
Symbol
Ncycle
Parameter
Write cycle
endurance(1)
Test condition
Max.
TA ≤ 25 °C, VCC(min) < VCC < VCC(max)
4,000,000
TA = 85 °C, VCC(min) < VCC < VCC(max)
1,200,000
Unit
Write cycle(2)
1. The write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2,
4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and qualification.
2. A Write cycle is executed when either a Page Write, a Byte write, a Write Identification Page or a Lock
Identification Page instruction is decoded. When using the Byte Write, the Page Write or the Write
Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling
Table 11. Memory cell data retention
Parameter
Data retention(1)
Test condition
TA = 55 °C
Min.
Unit
200
Year
1. For products identified by process letter K. The data retention behavior is checked in production, while the
200-year limit is defined from characterization and qualification results.
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DC and AC parameters
M24M02-DR
Table 12. DC characteristics
Symbol
Test conditions (in addition to
those in Table 7 and Table 8)
Parameter
Min.
Max.
Unit
ILI
Input leakage current
( E2, SCL, SDA)
VIN = VSS or VCC
device in Standby mode
-
±2
µA
ILO
Output leakage current
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
-
±2
µA
VCC = 1.8 V, fc= 400 kHz
-
1
mA
VCC = 2.5 V, fc =400 kHz
-
1
mA
VCC = 5.5 V, fc =400 kHz
-
2
mA
1.8 V < VCC < 5.5 V, fc= 1 MHz
-
2.5
mA
Average value during tW,
1.8 V ≤ VCC ≤ 5.5 V
-
2(1)
mA
Device not selected(2),
VIN = VSS or VCC, VCC = 1.8 V
-
3
µA
Device not selected(2),
VIN = VSS or VCC, VCC = 2.5 V
-
5
µA
Device not selected(2),
VIN = VSS or VCC, VCC = 5.5 V
-
5
µA
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
V
2.5 V ≤ VCC < 5.5 V
–0.45
0.30 VCC
V
1.8 V ≤ VCC < 2.5 V
0.75 VCC
VCC+1
2.5 V ≤ VCC < 5.5 V
0.70 VCC
VCC+1
IOL = 1.0 mA, VCC = 1.8 V
-
0.2
V
IOL = 2.1 mA, VCC = 2.5 V
-
0.4
V
IOL = 3.0 mA, VCC = 5.5 V
-
0.4
V
ICC
ICC0
ICC1
Supply current (Read)
Supply current (Write)
Standby supply current
VIL
Input low voltage
(SCL, SDA, WC)
VIH
Input high voltage
(SCL, SDA, WC)
VOL
Output low voltage
1. Characterized only, not tested in production.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
26/38
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M24M02-DR
DC and AC parameters
Table 13. 400 kHz AC characteristics
Parameter(1)
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
tCLCH
tLOW
tQL1QL2(2)
tF
tXH1XH2
tR
Min.
Max.
Unit
-
400
kHz
Clock pulse width high
600
-
ns
Clock pulse width low
1300
-
ns
SDA (out) fall time
20(3)
120
ns
Input signal rise time
(4)
(4)
ns
(4)
(4)
ns
100
-
ns
0
-
ns
tXL1XL2
tF
Input signal fall time
tDXCH
tSU:DAT
Data in set up time
tCLDX
tHD:DAT
Data in hold time
tCLQX
(5)
tDH
Data out hold time
100
-
ns
tCLQV
(6)
tAA
Clock low to next data valid (access time)
100
900
ns
tCHDL
tSU:STA
Start condition setup time
600
-
ns
tDLCL
tHD:STA
Start condition hold time
600
-
ns
tCHDH
tSU:STO
Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tWLDL(7)
tSU:WC
WC set up time (before the Start condition)
0
-
µs
(8)
tHD:WC
WC hold time (after the Stop condition)
1
-
µs
Write time
-
10
ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-
80
ns
tDHWH
tW
tWR
tNS(2)
-
1. Test conditions (in addition to those specified under Operating conditions and AC test measurement
conditions in Section 8: DC and AC parameters).
2. Characterized only, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
5. The min value for tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the
undefined region of the falling edge SCL.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12.
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
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DC and AC parameters
M24M02-DR
Table 14. 1 MHz AC characteristics
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
tCLCH
tXH1XH2
tXL1XL2
Min.
Max.
Unit
0
1
MHz
Clock pulse width high
260
-
ns
tLOW
Clock pulse width low
400
-
ns
tR
Input signal rise time
(1)
(1)
ns
Input signal fall time
(1)
(1)
ns
120
ns
50
-
ns
0
-
ns
100
-
ns
-
450
ns
tF
Parameter
tQL1QL2(2)
tF
SDA (out) fall time
tDXCH
tSU:DAT
Data in setup time
tCLDX
tHD:DAT Data in hold time
20
(3)
tCLQX(4)
tDH
Data out hold time
tCLQV(5)
tAA
Clock low to next data valid (access time)
tCHDL
tSU:STA
Start condition setup time
250
-
ns
tDLCL
tHD:STA
Start condition hold time
250
-
ns
tCHDH
tSU:STO Stop condition setup time
250
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
500
-
ns
tWLDL(6)
tSU:WC
WC set up time (before the Start condition)
0
-
µs
tDHWH(7)(2)
tHD:WC
WC hold time (after the Stop condition)
1
-
µs
tW
tWR
Write time
-
10
ms
tNS(2)
-
Pulse width ignored (input filter on SCL and
SDA)
-
80
ns
1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.
2. Characterized only, not tested in production.
3. With CL = 10 pF.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13.
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
28/38
DocID18204 Rev 8
M24M02-DR
DC and AC parameters
Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz
"US LINE PULL UP RESISTOR
K
K½
4HE 2 BUS X #BUS TIME CONSTANT
MUST BE BELOW THE NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFT
2
BU
S §
#
BU
S (ERE 2BUS § #BUS NS
6##
2BUS
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Figure 13. Maximum Rbus value versus bus parasitic capacitance Cbus) for
an I2C bus at maximum frequency fC = 1MHz
"US LINE PULL UP RESISTOR K
6##
4HE 2BUS § #BUS TIME CONSTANT
MUST BE BELOW THE NS
TIME CONSTANT LINE REPRESENTED
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BUS §
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BUS NS
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-36
DocID18204 Rev 8
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37
DC and AC parameters
M24M02-DR
Figure 14. AC waveforms
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DocID18204 Rev 8
M24M02-DR
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
9.1
SO8N package information
Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
K[Û
$
$
F
FFF
E
H
PP
*$8*(3/$1(
'
N
(
(
$
/
/
62$B9
1. Drawing is not to scale.
Table 15. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data
Symbol
inches(1)
millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
1.750
-
-
0.0689
A1
0.100
-
0.250
0.0039
-
0.0098
A2
1.250
-
-
0.0492
-
-
b
0.280
-
0.480
0.0110
-
0.0189
c
0.170
-
0.230
0.0067
-
0.0091
D
4.800
4.900
5.000
0.1890
0.1929
0.1969
E
5.800
6.000
6.200
0.2283
0.2362
0.2441
E1
3.800
3.900
4.000
0.1496
0.1535
0.1575
e
-
1.270
-
-
0.0500
-
h
0.250
-
0.500
0.0098
-
0.0197
k
0°
-
8°
0°
-
8°
L
0.400
-
1.270
0.0157
-
0.0500
L1
-
1.040
-
-
0.0409
-
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
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37
Package mechanical data
M24M02-DR
Figure 16. SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint
[
2B621B)3B9
1. Dimensions are expressed in millimeters.
9.2
WLCSP package information
Figure 17. WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
package outline
H
EEE =
) *
; <
'
+
H H
'HWDLO$
(
)
$
$
DDD
:DIHUEDFNVLGH
[
-
6LGHYLHZ
+
%XPSVLGH
2ULHQWDWLRQ
UHIHUHQFH
'HWDLO$
5RWDWHGƒ
%XPS
$
HHH =
‘E
FFF
GGG
=;<
=
=
6HDWLQJSODQH
:/&63B(B&B0(B9
1. Drawing is not to scale.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
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Package mechanical data
Table 16. WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.500
0.540
0.580
0.0197
0.0213
0.0228
A1
-
0.190
-
-
0.0075
-
A2
-
0.350
-
-
0.0138
-
(2)
-
0.270
-
-
0.0106
-
D
-
3.556
3.576
-
0.1400
0.1408
E
-
2.011
2.031
-
0.0792
0.0800
e
-
1.000
-
-
0.0394
-
e1
-
1.200
-
-
0.0472
-
e2
-
2.100
-
-
0.0827
-
F
-
0.505
-
-
0.0199
-
G
-
0.500
-
-
0.0197
-
H
-
0.728
-
-
0.0287
-
J
-
0.200
-
-
0.0079
-
aaa
-
-
0.110
-
-
0.0043
bbb
-
-
0.110
-
-
0.0043
ccc
-
-
0.110
-
-
0.0043
ddd
-
-
0.060
-
-
0.0024
eee
-
-
0.060
-
-
0.0024
b
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 18. WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
package recommended footprint
:/&63B(B&B)3B9
1. Dimensions are expressed in millimeters.
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Part numbering
10
M24M02-DR
Part numbering
Table 17. Ordering information scheme
Example:
M24M02
-D
R MN 6
T
P /K
Device type
M24 = I2C serial access EEPROM
Device function
M02 = 2Mbit (256 K x 8 bit)
EEPROM with additional identification page
Device family
B = Without Identification page
D = With Identification page
Operating voltage
R = VCC = 1.8 V to 5.5 V
Package(1)
MN = SO8 (150 mil width)
CS = Standard WLCSP
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
T = Tape and reel packing
blank = tube packing
Plating technology
P or G = ECOPACK2® (RoHS compliant)
Process(2)
/K = Manufacturing technology code
1. All packages are ECOPACK2® (RoHS compliant and free of brominated, chlorinated and antimony-oxide
flame retardants).
2. The process letters apply to WLCSP device only. These process letters appear on the device package
(marking) and on the shipment box. Please contact your nearest ST Sales Office for further information.
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Part numbering
Engineering samples
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be contacted
prior to any decision to use these Engineering samples to run qualification activity.
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Revision history
11
M24M02-DR
Revision history
Table 18. Document revision history
Date
Revision
22-Dec-2010
1
Initial release.
09-Feb-2011
2
Updated:
– Section 3.18: Read Identification Page
– Section 3.19: Read the lock status
– Figure 2: SO8 connections
– Table 6: Absolute maximum ratings
– Table 10: Input parameters
– Table 11: DC characteristics
– Table 12: AC characteristics at 400 kHz
– Table 13: 1 MHz AC characteristics
Deleted:
– Table 15 “Available M24M02-x products (package, voltage range,
frequency, temperature grade)”.
09-Aug-2011
3
Updated Figure 5: Maximum Rbus value versus bus parasitic
capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz
and Table 11: DC characteristics.
4
Updated:
– Table 2: Device select code
– Table 3: Most significant address byte
– Table 4: Least significant address byte.
– Section 3.6: Write operations
– Section 3.8: Page Write
5
Updated document template and text (minor changes).
Cycling updated to 4 million cycles and data retention updated to
200 years.
Added WLCSP packages.
6
Document reformatted.
Removed information related to thin WLCSP package.
Updated:
– WLCSP package silhouette on cover page
– Section 1: Description
– Figure 3: WLCSP connections
– Note (1) under Table 6: Absolute maximum ratings.
Added Figure 18: WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level
chip scale package recommended footprint
07-Feb-2012
25-Oct-2012
04-Jun-2013
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Changes
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M24M02-DR
Revision history
Table 18. Document revision history (continued)
Date
23-May-2014
27-Jul-2015
Revision
Changes
7
removed note on page 7, Updated Table 3: Device select code,
updated section numbering for Section 5.2.4 and Section 5.2.5,
updated note 1 on Table 11: Memory cell data retention, updated
Figure 18: WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale
package recommended footprint.
8
Updated:
– Figure 3 with note 1.
– Table 2
– Section 9.1: SO8N package information and Section 9.2: WLCSP
package information
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M24M02-DR
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
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