ALSC AS7C34096-20JI 5v/3.3v 512k x8 cmos sram Datasheet

January 2005
AS7C4096
AS7C34096
®
5V/3.3V 512K × 8 CMOS SRAM
Features
• Low power consumption: STANDBY
• AS7C4096 (5V version)
• AS7C34096 (3.3V version)
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• Low power consumption: ACTIVE
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 100 mA
- 1375 mW (AS7C4096) / max @ 12 ns
- 576 mW (AS7C34096) / max @ 10 ns
Pin arrangements
Logic block diagram
VCC
36-pin SOJ (400 mil)
GND
44-pin TSOP 2
524,288 × 8
Array
(4,194,304)
I/O1
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Row decoder
Input buffer
I/O8
Control
Circuit
WE
OE
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC
NC
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
Column decoder
A0
A1
A2
A3
A4
CE
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
Selection guide
Maximum address access time
Maximum outputenable access time
Maximum operating current
Maximum CMOS standby current
1/13/05; v.1.9
AS7C4096
AS7C34096
AS7C4096
AS7C34096
–10
10
5
–
160
–
20
Alliance Semiconductor
–12
12
6
250
130
20
20
–15
15
7
220
110
20
20
–20
20
8
180
100
20
20
Unit
ns
ns
mA
mA
mA
mA
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
AS7C4096
AS7C34096
®
Functional description
The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is high the device enters standby mode. The AS7C4096/AS7C34096 is guaranteed not to exceed 110/72 mW power
consumption in CMOS standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from either a single 5V(AS7C4096) or 3.3V(AS7C34096)
supply. Both devices are available in the JEDEC standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
Absolute maximum ratings
Parameter
Voltage on VCC relative to GND
Device
AS7C4096
AS7C34096
Voltage on any pin relative to GND
Power dissipation
Storage temperature
Temperature with VCC applied
DC current unto output (low)
Symbol
Vt1
Vt1
Vt2
PD
Tstg
Tbias
IOUT
Min
–1
–0.5
–0.5
–
–65
–55
–
Max
+7.0
+5.0
VCC +0.5
1.0
+150
+125
20
Unit
V
V
V
W
°C
°C
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
DOUT
DIN
Mode
Standby (ISB, ISB1)
Output disable (ICC)
Read (ICC)
Write (ICC)
Key: X = Don’t care, L = Low, H = High
1/13/05; v.1.9
Alliance Semiconductor
P. 2 of 9
AS7C4096
AS7C34096
®
Recommended operating condition
Parameter
Device
AS7C4096
AS7C34096
AS7C34096
AS7C4096
AS7C34096
Supply voltage
Input voltage
Ambient operating
temperature
commercial
industrial
Symbol
VCC(12/15/20)
VCC (10)
VCC(12/15/20)
VIH
VIH
VIL1
TA
TA
Min
4.5
3.15
3.0
2.2
2.0
–0.5
0
–40
Nominal
5.0
3.30
3.3
–
–
–
–
–
Max
5.5
3.6
3.6
VCC + 0.5
VCC + 0.5
0.8
70
85
Unit
V
V
V
V
V
V
°C
°C
1 VIL min = –1.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)1
Parameter Symbol
Input leakage
current
Output
leakage
current
Operating
power supply
current
Standby
power supply
current
Output
voltage
Test conditions
|ILI|
VCC = Max, VIN = GND to VCC
|ILO|
VCC = Max, CE = VIH
VOUT= GND to VCC
ICC
VCC = Max, CE < VIL
f = fMax, IOUT = 0mA
ISB
VCC = Max, CE = VIH
f = fMax, IOUT = 0mA
ISB1
VOL
Device
AS7C4096/
–10
–12
–15
–20
Min Max Min Max Min Max Min Max Unit
–
1
–
1
–
1
–
1
µA
–
1
–
1
–
1
–
1
µA
AS7C4096
–
–
–
250
–
220
–
180 mA
AS7C34096
–
160
–
130
–
110
–
100
AS7C4096
AS7C34096
AS7C4096
–
–
–
–
60
–
–
–
–
60
60
20
–
–
–
60
60
20
–
–
–
60
60
20
–
20
–
20
–
20
–
20
–
0.4
–
0.4
–
0.4
–
0.4
V
–
2.4
–
2.4
–
2.4
–
V
AS7C34096
AS7C4096/
AS7C34096
VCC = Max,
CE ≥ VCC – 0.2V, VIN ≤ 0.2V or VIN
AS7C34096
≥ VCC – 0.2V, f = 0
IOL = 8 mA, VCC = Min
AS7C4096/
VOH
IOH = –4 mA, VCC = Min
AS7C34096 2.4
mA
mA
Capacitance (f = 1MHz, TA= 25° C, VCC = NOMINAL)2
Parameter
Input capacitance
I/O capacitance
1/13/05; v.1.9
Symbol
CIN
CI/O
Signals
A, CE, WE, OE
I/O
Alliance Semiconductor
Test conditions
VIN = 0V
VIN = VOUT = 0V
Max
5
7
Unit
pF
pF
P. 3 of 9
AS7C4096
AS7C34096
®
Read cycle (over the operating range)3,9
Parameter
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE Low to output in low Z
CE High to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
Power down time
–10
Symbo
l
Min
Max
tRC
10
–
tAA
–
10
tACE
–
10
tOE
–
5
tOH
3
–
tCLZ
3
–
tCHZ
–
5
tOLZ
0
–
tOHZ
–
5
tPU
0
–
tPD
–
10
Min
12
–
–
–
3
3
–
0
–
0
–
–12
Max
–
12
12
6
–
–
6
–
6
–
12
Min
15
–
–
–
3
0
–
0
–
0
–
–15
Max
–
15
15
7
–
–
7
–
7
–
15
Min
20
–
–
–
3
0
–
0
–
0
–
–20
Max
–
20
20
8
–
–
9
–
9
–
20
Unit Notes
ns
ns
3
ns
3
ns
ns
5
ns
4, 5
ns
4, 5
ns
4, 5
ns
4, 5
ns
4, 5
ns
4, 5
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
tAA
tOH
DOUT
Data valid
Read waveform 2 (CE, OE controlled)3,6,8,9
tRC1
CE
tOE
OE
tOLZ
tOHZ
tACE
tCHZ
DOUT
Data valid
tCLZ
Supply
current
1/13/05; v.1.9
tPU
tPD
50%
50%
Alliance Semiconductor
ICC
ISB
P. 4 of 9
AS7C4096
AS7C34096
®
Write cycle (over the operating range)11
–10
Parameter
Symbol Min
Max
Write cycle time
tWC
10
–
Chip enable (CE) to write end
tCW
7
–
Address setup to write end
tAW
7
–
Address setup time
tAS
0
–
Write pulse width (OE = high)
tWP1
7
–
Write pulse width (OE = low
tWP2
10
–
Address hold from end of write
tAH
0
–
Write recovery time
tWR
0
–
Data valid to write end
tDW
5
–
Data hold time
tDH
0
–
Write enable to output in high Z
tWZ
0
5
Output active from write end
tOW
3
–
–12
Min
Max
12
–
8
–
8
–
0
–
8
–
12
–
0
–
0
–
6
–
0
–
0
6
3
–
–15
Min
Max
15
–
10
–
10
–
0
–
10
–
15
–
0
–
0
–
7
–
0
–
0
7
3
–
–20
Min
Max
20
–
12
–
12
–
0
–
12
–
20
–
0
–
0
–
9
–
0
–
0
9
3
–
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
ns
4, 5
ns
4, 5
Write waveform 1 (WE controlled)10,11
tWC
tWR
tAH
tAW
Address
tWP
WE
tAS
tDW
DIN
tDH
Data valid
tWZ
tOW
DOUT
Write waveform 2 (CE controlled)10,11
tWC
tWR
tAH
tAW
Address
tAS
tCW
CE
tWP
WE
tWZ
DIN
tDW
tDH
Data valid
DOUT
1/13/05; v.1.9
Alliance Semiconductor
P. 5 of 9
AS7C4096
AS7C34096
®
AC test conditions
-
Output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figures A, B, and C.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
+3.0V
GND
90%
10%
90%
10%
2 ns
Figure A: Input pulse
DOUT
255Ω
Thevenin equivalent:
168Ω
DOUT
+1.728V
+5V
480Ω
C13
GND
Figure B: 5V Output load
+3.3V
DOUT
350Ω
320Ω
C13
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE or WE must be HIGH during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Not applicable.
C = 30pF, except at high Z and low Z parameters, where C = 5pF.
1/13/05; v.1.9
Alliance Semiconductor
P. 6 of 9
AS7C4096
AS7C34096
®
Typical DC and AC characteristics 12
1.2
ICC
1.0
Normalized ICC, ISB
0.8
0.6
ISB
0.4
0.2
0.8
0.6
ISB
0.4
Ta = 25° C
1.3
1.2
1.1
1.0
0.9
0.8
MIN
NOMINAL
Supply voltage (V)
Output source current IOH
vs. output voltage VOH
140
120
VCC = VCC(NOMINAL)
100
Ta = 25° C
60
40
20
0
1.2
1.1
1.0
0.9
Output voltage (V)
1/13/05; v.1.9
0.2
–10
35
80
125
Ambient temperature (°C)
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
1.2
VCC = VCC(NOMINAL)
1.0
Ta = 25° C
0.8
0.6
0.4
0.2
0.0
–10
35
80
125
Ambient temperature (°C)
Output sink current IOL
vs. output voltage VOL
120
VCC = VCC(NOMINAL)
100
Ta = 25° C
80
60
40
0
25
50
75
Cycle frequency (MHz)
100
Typical access time change ∆tAA
vs. output capacitive loading
35
VCC = VCC(NOMINAL)
30
20
0
VCC
1
1.4
1.3
140
80
5
–55
VCC = VCC(NOMINAL)
1.4
0.8
–55
MAX
VCC = VCC(NOMINAL)
25
–10
35
80
125
Ambient temperature (°C)
Normalized access time tAA
vs. ambient temperature Ta
1.5
Normalized access time
1.4
625
0.04
0.0
–55
MAX
Output sink current (mA)
Normalized access time
NOMINAL
Supply voltage (V)
Normalized access time tAA
vs. supply voltage VCC
1.5
Output source current (mA)
1.0
0.2
0.0
MIN
0
ICC
Normalized ICC
Normalized ICC, ISB
1.2
Normalized supply current ISB1
vs. ambient temperature Ta
Normalized ISB1 (log scale)
1.4
Normalized supply current ICC, ISB
vs. ambient temperature Ta
Change in tAA (ns)
1.4
Normalized supply current ICC, ISB
vs. supply voltage VCC
25
20
15
10
5
0
0
Output voltage (V)
Alliance Semiconductor
VCC
0
250
500
750
Capacitance (pF)
1000
P. 7 of 9
AS7C4096
AS7C34096
®
Package dimensions
c
44 434241403938373635343332313029282726252423
e He
44-pin TSOP 2
1 2 3 4 5 6 7 8 9 101112131415161718 19202122
d
A2
A
A1
E
b
e
l
0–5°
D
b
36-pin SOJ E1 E2
A
A1
b1
Pin 1
Seating
Plane
c
A2
E
1/13/05; v.1.9
Alliance Semiconductor
A
A1
A2
b
c
d
e
He
E
l
44-pin TSOP 2
Min (mm) Max (mm)
1.2
0.05
0.15
0.95
1.05
0.30
0.45
0.21
0.12
18.31
18.52
10.06
10.26
11.68
11.94
0.80 (typical)
0.40
0.60
A
A1
A2
b
b1
c
D
e
E1
E2
E
36-pin SOJ 400
Min(mm)
Max(mm)
.128
0.148
0.025
–
0.105
0.115
0.015
0.020
0.026
0.032
0.007
0.013
.920
.930
0.045
0.055
0.405
0.395
0.435
0.445
0.370 BSC
P. 8 of 9
AS7C4096
AS7C34096
®
Ordering codes
Package
SOJ
TSOP 2
Version
5V commercial
5V industrial
3.3V commercial
3.3V industrial
5V commercial
5V industrial
3.3V commercial
3.3V industrial
10 ns
NA
NA
AS7C34096-10JC
NA
NA
NA
AS7C34096-10TC
NA
12 ns
AS7C4096-12JC
AS7C4096-12JI
AS7C34096-12JC
AS7C34096-12JI
AS7C4096-12TC
AS7C4096-12TI
AS7C34096-12TC
AS7C34096-12TI
15 ns
AS7C4096-15JC
AS7C4096-15JI
AS7C34096-15JC
AS7C34096-15JI
AS7C4096-15TC
AS7C4096-15TI
AS7C34096-15TC
AS7C34096-15TI
20 ns
AS7C4096-20JC
AS7C4096-20JI
AS7C34096-20JC
AS7C34096-20JI
AS7C4096-20TC
AS7C4096-20TI
AS7C34096-20TC
AS7C34096-20TI
Note:
Add suffix “N” to the above part number for lead free devices, Ex. AS7C4096-12JCN
Part numbering system
AS7C
X
SRAM prefix
Voltage:
Blank: 5V CMOS
3: 3.3V CMOS
1/13/05; v.1.9
4096
–XX
Device Access
number time
J or T
Packages:
J: SOJ 400 mil
T: TSOP 2
Alliance Semiconductor
X
N
Temperature ranges:
C: Commercial, 0°C to 70°C Lead free device
I: Industrial, –40°C to 85°C
P. 9 of 9
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The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under
development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
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