Cypress CY2XF34FLXCT High performance lvpecl oscillator with frequency margining - pin control Datasheet

CY2XF34
High Performance LVPECL Oscillator with
Frequency Margining - Pin Control
High Performance LVPECL Oscillator with Frequency Margining - Pin Control
Features
Functional Description
■
Low Jitter Crystal Oscillator (XO)
The CY2XF34 is a high performance and high frequency Crystal
Oscillator (XO). It uses a Cypress proprietary low noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed through two select pins, allowing
easy frequency margin testing in applications.
■
Less than 1 ps Typical RMS Phase Jitter
■
Differential LVPECL Output
■
Output Frequency from 50 MHz to 690 MHz
■
Two Frequency Margining Control Pins (FS0, FS1)
■
Factory Configured or Field Programmable
■
Integrated Phase-Locked Loop (PLL)
■
Supply Voltage: 3.3 V or 2.5 V
■
Pb-Free Package: 5.0 × 3.2 mm LCC
■
Commercial and Industrial Temperature Ranges
The CY2XF34 is available as a factory configured device or as
a field programmable device.
Logic Block Diagram
C RYSTAL
OSCILLATOR
FS0
LOW -NOISE
PLL
4
CLK
5
CLK#
OUTPUT
DIVIDER
1
FREQUENCY
SELECT DECODE
FS1
2
Pinouts
Figure 1. Pin Diagram - 6-pin Ceramic LCC
FS0 1
6 VDD
FS1 2
5 CLK#
VSS 3
4 CLK
Pin Definitions
Pin
1, 2
Name
FS0, FS1
I/O Type
Description
CMOS Input
Frequency Select
4, 5
CLK, CLK#
LVPECL Output
Differential Output Clock
6
VDD
Power
Supply Voltage: 2.5 V or 3.3 V
3
VSS
Power
Ground
Cypress Semiconductor Corporation
Document Number: 001-53149 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 21, 2011
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CY2XF34
Functional Description
Factory Configured CY2XF34
The FS0 and FS1 pins select between four different output
frequencies, as shown in Table 1. Frequency margining is a
common application for this feature. One frequency is used for
the standard operating mode of the device, while the other
frequencies are available for margin testing, either during
product development or in system manufacturing test.
For customers wanting ready-to-use devices, the CY2XF34 is
available with no field programming required. All requests are
submitted to the local Cypress Field Application Engineer (FAE)
or sales representative. After the request is processed, you
receive a new part number, samples, and datasheet with the
programmed values. This part number is used for additional
sample requests and production orders.
Table 1. Frequency Select
Output Frequency
Programming Variables
FS1
FS0
0
0
Frequency 0
Output Frequencies
0
1
Frequency 1
1
0
Frequency 2
1
1
Frequency 3
The CY2XF34 is programmed with up to four independent output
frequencies, which are then selected using the FS0 and FS1
pins. The device can synthesize frequencies to a resolution of
1 part per million (ppm), but the actual accuracy of the output
frequency is limited by the accuracy of the integrated reference
crystal.
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
Programming Description
The CY2XF34 is a programmable device. Before being used in
an application, it must be programmed with the output
frequencies and other variables described in a later section. Two
different device types are available, each with its own
programming flow. They are described in the following sections.
Field Programmable CY2XF34F
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyberClocks™ Online Software to
specify the device configuration and generate a JEDEC
(extension .jed) programming file. Programming of samples and
prototype quantities is available using a Cypress programmer.
Third party vendors manufacture programmers for small to large
volume applications. Cypress’s value added distribution partners
also provide programming services. Field programmable
devices are designated with an “F” in the part number. They are
intended for quick prototyping and inventory reduction. The
CY2XF34 is One Time Programmable (OTP).
The software is located at www.cyberclocksonline.com.
Document Number: 001-53149 Rev. *D
The CY2XF34 has an output frequency range of 50 MHz to
690 MHz, but the range is not continuous. The CY2XF34 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz, and
596 MHz to 617 MHz.
Industrial Versus Commercial Device Performance
Industrial and Commercial devices have different internal
crystals. This has a potentially significant impact on performance
levels for applications requiring the lowest possible phase noise.
CyberClocks Online Software displays expected performance
for both options.
Phase Noise Versus Jitter Performance
In most cases, the device configuration for optimal phase noise
performance is different from the device configuration for optimal
cycle to cycle or period jitter. CyberClocks Online Software
includes algorithms to optimize performance for either
parameter.
Table 2. Device Programming Variables
Variable
Output Frequency 0 (Power on default)
Output Frequency 1
Output Frequency 2
Output Frequency 3
Optimization (phase noise or jitter)
Temperature range (Commercial or Industrial)
Page 2 of 10
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CY2XF34
Absolute Maximum Conditions
Parameter
Description
Min
Max
Unit
–0.5
4.4
V
Relative to VSS
–0.5
VDD + 0.5
V
Non Operating
–55
135
°C
–40
135
°C
ESD Protection (Human Body Model)
JEDEC STD 22-A114-B
2000
–
V
Thermal Resistance, Junction to Ambient
0 m/s airflow
VDD
Supply Voltage
VIN[1]
Input Voltage, DC
TS
Temperature, Storage
TJ
Temperature, Junction
ESDHBM
JA[2]
Condition
64
°C/W
Operating Conditions
Parameter
Min
Typ
Max
Unit
3.3 V Supply Voltage Range
3.135
3.3
3.465
V
2.5 V Supply Voltage Range
2.375
2.5
2.625
V
TPU
Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp
is Monotonic)
0.05
–
500
ms
TA
Ambient Temperature (Commercial)
VDD
Description
Ambient Temperature (Industrial)
0
–
70
°C
–40
–
85
°C
DC Electrical Characteristics
Parameter
IDD[3]
Description
Operating Supply Current
Min
Typ
Max
Unit
VDD = 3.465 V, CLK = 150 MHz, output
terminated
Condition
–
–
150
mA
VDD = 2.625 V, CLK = 150 MHz, output
terminated
–
–
145
mA
VOH
LVPECL High Output Voltage
VDD = 3.3 V or 2.5 V, RTERM = 50  to
VDD – 2.0 V
VDD – 1.15
–
VDD – 0.75
V
VOL
LVPECL Low Output Voltage
VDD = 3.3 V or 2.5 V, RTERM = 50  to
VDD – 2.0 V
VDD – 2.0
–
VDD – 1.625
V
VOD1
LVPECL Output Voltage Swing
(VOH – VOL)
VDD = 3.3 V or 2.5 V, RTERM = 50  to
VDD – 2.0 V
600
–
1000
mV
VOD2
LVPECL Output Voltage Swing
(VOH – VOL)
VDD = 2.5 V, RTERM = 50  to VDD – 1.5 V
500
–
1000
mV
VOCM
LVPECL Output Common Mode
Voltage ((VOH + VOL)/2)
VDD = 2.5 V, RTERM = 50  to VDD – 1.5 V
1.2
–
–
V
VIH
Input High Voltage
0.7 × VDD
–
–
V
–
–
0.3 × VDD
V
–
–
115
A
VIL
Input Low Voltage
IIH0
Input High Current, FS0 pin
IIH1
Input High Current, FS1 pin
Input = VDD
–
–
10
A
IIL0
Input Low Current, FS0 pin
Input = VSS
–50
–
–
A
IIL1
Input Low Current, FS1 pin
Input = VSS
–20
–
–
A
Input = VDD
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 × 114 × 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. IDD includes ~24 mA of current that is dissipated externally in the output termination resistors.
Document Number: 001-53149 Rev. *D
Page 3 of 10
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CY2XF34
DC Electrical Characteristics (continued)
Parameter
Description
CIN0[4]
CIN1[4]
Condition
Min
Typ
Max
Unit
Input Capacitance, FS0 pin
–
15
–
pF
Input Capacitance, FS1 pin
–
4
–
pF
Min
Typ
Max
Unit
50
–
690
MHz
AC Electrical Characteristics
The AC Electrical Characteristics for part CY2XF34 are as follows [4]
Parameter
Description
Condition
FOUT
Output Frequency[5]
FSC
Frequency Stability, commercial
devices[6]
TA = 0 °C to 70 °C
–
–
±35
ppm
FSI
Frequency Stability, industrial
devices[6]
TA = –40 °C to 85 °C
–
–
±55
ppm
AG
Aging, 10 years
–
–
±15
ppm
TDC
Output Duty Cycle
F  450 MHz, measured at zero
crossing
45
50
55
%
F > 450 MHz, measured at zero
crossing
40
50
60
%
0.2
0.4
1.0
ns
TR, TF
Output Rise and Fall Time
20% and 80% of full output swing
TLOCK
Startup Time
Time for CLK to reach valid frequency
measured from the time VDD = VDD(min)
–
–
10
ms
TLFS
Re-lock Time
Time for CLK to reach valid frequency
from FS0 or FS1 pin change
–
–
10
ms
TJitter()
RMS Phase Jitter (Random)
fOUT = 106.25 MHz (12 kHz–20 MHz)
–
1
–
ps
Typical Output Characteristics
Figure 2. 2.5V Supply and Termination to VDD–1.5 V, minimum VDD and maximum TA
0.9
1.40
0.8
0.7
VOCM (V)
Swing (V)
1.35
0.6
1.30
1.25
0.5
1.20
0.4
0
100
200
300
400
Frequency (MHz)
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Notes
4. Not 100% tested, guaranteed by design and characterization.
5. This parameter is specified in CyberClocks Online software.
6. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
Document Number: 001-53149 Rev. *D
Page 4 of 10
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CY2XF34
Figure 3. 2.5 V Supply and Termination to VDD–2 V, minimum VDD and maximum TA
0.9
0.90
0.8
0.7
VOCM (V)
Swing (V)
0.85
0.6
0.80
0.75
0.5
0.4
0.70
0
100
200
300
400
500
600
700
0
100
200
Frequency (MHz)
300
400
500
600
700
Frequency (MHz)
Figure 4. 3.3 V Supply and Termination to VDD–2 V, minimum VDD and maximum TA
0.9
1.60
0.8
0.7
VOCM (V)
Swing (V)
1.55
0.6
1.50
1.45
0.5
0.4
1.40
0
100
200
300
400
Frequency (MHz)
Document Number: 001-53149 Rev. *D
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Page 5 of 10
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CY2XF34
Switching Waveforms
Figure 5. Output DC Parameters
VA
CLK
VOD
VOCM = (VA + VB)/2
CLK#
VB
Figure 6. Duty Cycle Timing
CLK
TDC =
CLK#
TPW
TPERIOD
TPW
TPERIOD
Figure 7. Output Rise and Fall Time
CLK#
CLK
80%
80%
20%
20%
TR
TF
Termination Circuits
Figure 8. LVPECL Termination
VDD - 2V or VDD - 1.5V
(VDD = 2.5V)
VDD - 2V
(VDD = 3.3V)




CLK#
Document Number: 001-53149 Rev. *D
CLK
BUF
BUF
CLK




CLK#
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CY2XF34
Ordering Information
Part Number
Configuration
Package Description
Product Flow
Pb-Free
CY2XF34FLXCT
Field Programmable
6-pin Ceramic LCC SMD - Tape and Reel
Commercial, 0 °C to 70 °C
CY2XF34FLXIT
Field Programmable
6-pin Ceramic LCC SMD - Tape and Reel
Industrial, –40 °C to 85 °C
Possible Cofigurations
Some product offerings are factory programmed customer specific devices with customized part numbers.The Possible Configurations
table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales Representative for
more information.
Part Number [7]
Configuration
Package Description
Product Flow
Pb-Free
CY2XF34LXCxxxT
Factory Configured
6-pin Ceramic LCC SMD - Tape and Reel
Commercial, 0 °C to 70 °C
CY2XF34LXIxxxT
Factory Configured
6-pin Ceramic LCC SMD - Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 2X F34 F
L X X xxx T
T = Tape and Reel
Customer Specific Code
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package type: 6-pin Ceramic LCC SMD
Configuration: F = Field Programmable; blank = Factory Configured
Part identifier
Family
Company ID: CY = Cypress
Note
7. “xxx” is a factory assigned code that identifies the programming option.For more details, contact your local Cypress FAE or Sales Representative.
Document Number: 001-53149 Rev. *D
Page 7 of 10
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CY2XF34
Package Drawings and Dimensions
Figure 9. 6-pin 3.2 × 5.0 mm Ceramic LCC LZ06A
001-10044 *A
Document Number: 001-53149 Rev. *D
Page 8 of 10
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CY2XF34
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
ESD
electrostatic discharge
°C
degree Celsius
FAE
Field Application Engineer
µA
micro Amperes
I/O
input/output
mA
milli Amperes
OTP
One Time Programmable
mm
milli meter
PCB
printed circuit board
ms
milli seconds
PLL
phase-locked loop
mV
milli Volts
SMD
Surface Mounted Devices
MHz
Mega Hertz
ns
nano seconds
pF
pico Farad
ps
pico seconds
ppm
parts per million
V
Volts
W
Watts
%
percent

ohms
Document Number: 001-53149 Rev. *D
Symbol
Unit of Measure
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CY2XF34
Document History Page
Document Title: CY2XF34 High Performance LVPECL Oscillator with Frequency Margining - Pin Control
Document Number: 001-53149
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
2704379
KVM/PYRS
05/11/09
New datasheet
*A
2734005
WWZ
07/09/09
Post to external web
*B
2761926
KVM
09/10/09
Revised maximum output rise and fall times
Added Absolute Maximum Conditions table
*C
2898472
KVM
03/24/2010 Moved ‘xxx’ parts to Possible Configurations table.
Updated package diagram.
*D
3199911
BASH
03/18/2011 Changed status from Preliminary to Final.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated in new template.
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53149 Rev. *D
Revised March 21, 2011
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