ON NCP1239AD100R2G Fixed frequency currentâ mode controller for flyback converter Datasheet

NCP1239
Fixed Frequency
Current‐Mode Controller for
Flyback Converter
The NCP1239 is a fixed-frequency current-mode controller
featuring a high-voltage start-up current source to provide a quick and
lossless power-on sequence. This function greatly simplifies the
design of the auxiliary supply and the VCC capacitor by activating the
internal start-up current source to supply the controller during start-up,
transients, latch, stand-by etc.
With a supply range up to 35 V, the controller hosts a jittered 65 or
100-kHz switching circuitry operated in peak current mode control.
When the power on the secondary side starts to decrease, the controller
automatically folds back its switching frequency down to minimum
level of 26 kHz. As the power further goes down, the part enters skip
cycle while limiting the peak current that insures excellent efficiency
in light load condition.
NCP1239 features a timer-based fault detection circuitry that
ensures a quasi-flat overload detection, independent of the input
voltage.
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SOIC−7
CASE 751U
PIN CONNECTIONS
8
HV
3
6
VCC
4
5
DRV
Fault
1
FB
2
CS
GND
Features
• Fixed-Frequency 65-kHz or 100-kHz Current-Mode Control
Operation
MARKING DIAGRAM
• Frequency Foldback Down to 26 kHz and Skip Mode to
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximize Performance in Light Load Conditions
Adjustable Over Power Protection (OPP) Circuit
High-Voltage Current Source with Brown-Out (BO) Detection
Internal Slope Compensation
Internal Fixed 8-ms Soft-Start
Frequency Jittering in Normal and Frequency Foldback Modes
64-ms Timer-Based Short-Circuit Protection with Auto-Recovery
or Latched Operation
Pre-Short Ready for Latched OCP Versions
Latched OVP on VCC (NCP1239 A, B, D or E Versions)
Latched OVP/OTP Input for Improved Robustness
35-V VCC Operation
±500 mA Peak Source/Sink Drive Capability
Internal Thermal Shutdown
Extremely Low No-Load Standby Power
Pin-to-Pin Compatible with the Existing NCP1236/1247 Series
These Devices are Pb-Free and are RoHS Compliant
8
1239xfff
ALYWX
G
1
1239xfff = Specific Device Code
x = A, B, C, D or E
fff = 065 or 100
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 24 of
this data sheet.
Typical Applications
• AC-DC Converters for TVs, Set-Top Boxes and Printers
• Offline Adapters for Notebooks and Netbooks
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 9
1
Publication Order Number
NCP1239/D
NCP1239
Vbulk
Vout
.
.
OVP
NCP1239
.
8
1
2
3
6
4
5
OPP
adjsut.
NTC
Figure 1. Application Schematic (OPP Adjustment)
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
Fault
The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds.
A precise pull up current source allows direct interface with an NTC thermistor. Fault detection
triggers a latch.
2
FB
Hooking an optocoupler collector to this pin will allow regulation.
3
CS
This pin monitors the primary peak current but also offers an overpower compensation adjustment.
When the CS pin is brought above 1.2 V, the part is permanently latched off.
4
GND
The controller ground.
5
DRV
The driver’s output to an external MOSFET gate.
6
VCC
This pin is connected to an external auxiliary voltage. An OVP comparator monitors this pin and
offers a means to latch the converter in fault conditions.
7
NC
Non-connected for improved creepage distance.
8
HV
Connected to the bulk capacitor or rectified ac line, this pin powers the internal current source to
deliver a start-up current. It is also used to provide the brown-out detection and the HV sensing for
the Overpower protection.
Table 2. DEVICE OPTION AND DESIGNATIONS
Device
Frequency
OCP Protection
VCC OVP Protection
Fault Pin
Protection
BO Levels
NCP1239AD65R2G
65 kHz
Latch
Latch
Latch
110/101
NCP1239BD65R2G
65 kHz
Auto-Recovery
Latch
Latch
110/101
NCP1239CD65R2G
65 kHz
Auto-Recovery
Auto-Recovery
Latch
110/101
NCP1239DD65R2G
65 kHz
Auto-Recovery
Latch
Latch
101/95
NCP1239ED65R2G
65 kHz
Auto-Recovery
Auto-Recovery
Auto-Recovery
110/101
NCP1239AD100R2G
100 kHz
Latch
Latch
Latch
110/101
NCP1239BD100R2G
100 kHz
Auto-Recovery
Latch
Latch
110/101
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2
NCP1239
NC
VFault(OVP)
Vdd
600−ns time
constant
Clock
IOTP
OVP/OTP
gone?
Up counter
Fault
HV sample
BO
BO end
RST
HV detection
& sampling
HV
4
Vfault(clamp)
BO
TSD
VFault(OTP)
Option for
OVP_VCC
Dual HV startup
current source
TSD
Vcc(reset)
S
Latch
UVLO
Q
Vcc(reset)
Vdd
OVP_VCC
R
Skip
Vcc logic
management
Vdd
Q
Vcc
Jitter
20us time
constant
TSD end
Rup
VCC(OVP)
Vskip
Stop
Foldback
FB
BO end
Clock
Oscillator
65 kHz / 100 kHz
/4
Slope
Compensation
+
Clamp
S
Drv
Q
PWM
Q
Soft−start
Ramp
8 ms
HV sample
R
Soft−start
GND
BO
SS end
OPP Current
Generation
Latch
TSD
Overcurrent
S
Iopp
OCP_flag
Q
VLimit1
Q
Vdd
Skip
LEB
R
300 ns
Ibias
CS
PWM
LEB
Up counter
120 ns
4
OVP_VCC
(option)
Protection
Mode
RST
Reset
VLimit2
OCP_flag
Dmax
OCP
Timer
64 ms
OCP Fault
gone?
Auto−recovery
Timer
UVLO
1s
Vcc(reset)
Figure 2. Simplified Block Diagram
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NCP1239
Table 3. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
−0.3 to 35
V
Power Supply Voltage, VCC Pin, Continuous Voltage
Maximum Voltage on Low Power Pins CS, FB and Fault
−0.3 to 5.5
V
VDRV
−0.3 to 20
V
HV
−0.3 to 650
V
Thermal Resistance Junction-to-Air
Single Layer PCB 25 mm@, 2 Oz Cu Printed Circuit Copper Clad
RθJ−A
250
°C/W
Maximum Junction Temperature
TJ(max)
150
°C
Storage Temperature Range
TSTG
−60 to 150
°C
ESDHBM
ESDMM
4
200
kV
V
1
kV
Maximum Voltage on DRV Pin
High Voltage Pin
ESD Capability (Note 2)
Human Body Model – All Pins Except HV
Machine Model
Charged-Device Model ESD Capability per JEDEC JESD22−C101E
Moisture Sensitivity Level
MSL
1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC JESD22−A114F
ESD Machine Model tested per JEDEC JESD22−A115C
Charged-Device Model ESD Capability tested per JEDEC JESD22−C101E
Latch-up Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max Values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
START-UP SECTION
Minimum Voltage for Current Source
Operation
IHV = 90% ISTART2,
VCC = VCC(on) − 0.5 V
VHV(min)
−
25
60
V
Current Flowing Out of VCC Pin
VCC = 0 V
ISTART1
0.2
0.5
0.8
mA
Current Flowing Out of VCC Pin
VCC = VCC(on) – 0.5 V
ISTART2
1.5
3
4.5
mA
HV Pin Leakage Current
VHV = 325 V
ILEAK1
−
8
20
mA
Start-Up Threshold
HV Current Source Stop Threshold
VCC Increasing
VCC(on)
11.0
12.0
13.0
V
HV Current Source Restart Threshold
VCC Decreasing
VCC(min)
9.0
10.0
11.0
V
Minimum Operating Voltage
VCC Decreasing
VCC(off)
8.0
8.8
9.4
V
Operating Hysteresis
VCC(on) = VCC(off)
VCC(hys)
3.0
−
−
V
VCC(inhibit)
0.7
1.2
1.7
V
VCC(reset)
6.5
7
7.5
V
SUPPLY SECTION
VCC Level for ISTART1 to ISTART2 Transition
VCC Level where Logic Functions are Reset
VCC Decreasing
Internal IC Consumption
VFB = 3.2 V, FSW = 65 kHz
and CL = 0
ICC1
−
1.4
2.2
mA
Internal IC Consumption
VFB = 3.2 V, FSW = 65 kHz
and CL = 1 nF
ICC2
−
2.1
3.0
mA
Internal IC Consumption
VFB = 3.2 V, FSW = 100 kHz
and CL = 0
ICC1
−
1.7
2.5
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of IBIAS and IOPP, thus at VHV = 125 V is observed the IBIAS only, because IOPC is switched off.
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NCP1239
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(For typical values TJ = 25°C, for min/max Values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
SUPPLY SECTION
Internal IC Consumption
VFB = 3.2 V, FSW = 100 kHz
and CL = 1 nF
ICC2
−
3.1
4.0
mA
Internal IC Consumption in Skip Cycle
VCC = 12 V, VFB = 0.775 V
Driving 8 A/650 V MOSFET
ICC(stb)
−
500
−
mA
Internal IC Consumption in Fault Mode
Fault or Latch
ICC3
−
400
−
mA
Internal IC Consumption before Start-Up
VCC(min) < VCC < VCC(on)
ICC4
−
310
−
mA
Internal IC Consumption before Start-Up
VCC < VCC(min)
ICC5
−
20
−
mA
DRIVE OUTPUT
Rise Time (10−90%)
VDRV from 10 to 90%
VCC = VCC(off) + 0.2 V,
CL = 1 nF
tR
−
40
−
ns
Fall Time (90−10%)
VDRV from 90 to 10%
VCC = VCC(off) + 0.2 V,
CL = 1 nF
tF
−
30
−
ns
Source Resistance
ROH
−
6
−
W
Sink Resistance
ROL
−
6
−
W
Peak Source Current
DRV High State,
VDRV = 0 V (Note 1)
VCC = VCC(off) + 0.2 V,
CL = 1 nF
ISOURCE
−
500
−
mA
Peak Sink Current
DRV Low State,
VDRV = VCC (Note 1)
VCC = VCC(off) + 0.2 V,
CL = 1 nF
ISINK
−
500
−
mA
High State Voltage
(Low VCC Level)
VCC = 9 V, RDRV = 33 kW
DRV High State
VDRV(low)
8.8
−
−
V
High State Voltage
(High VCC Level)
VCC = VCC(OVP) – 0.2 V,
DRV High State and Unloaded
VDRV(clamp)
11.0
13.5
16.0
V
IBIAS
−
1
−
mA
CURRENT COMPARATOR
Input Pull-Up Current
VCS = 0.7 V
Maximum Internal Current Setpoint
TJ from −40°C to +125°C
(No OPP)
VLIMIT1
0.752
0.800
0.848
V
Abnormal Over-Current Fault Threshold
TJ = +25 °C (No OPP)
VLIMIT2
1.10
1.20
1.30
V
Default Internal Voltage Set Point for
Frequency Foldback Trip Point
~59% of VLIMIT
VFOLD(CS)
−
475
−
mV
Internal Peak Current Setpoint Freeze
~31% of VLIMIT
VFREEZE(CS)
−
250
−
mV
Propagation Delay from VLIMIT Detection to
Gate Off-State
DRV Output Unloaded
tDEL
−
50
100
ns
Leading Edge Blanking Duration
tLEB1
−
300
−
ns
Abnormal Over-Current Fault Blanking
Duration for VLIMIT3
tLEB2
−
120
−
ns
tCOUNT
−
4
−
tSS
−
8
−
Number of Clock Cycles before Fault
Confirmation
Internal Soft-Start Duration
Activated upon Start-Up or
Auto-Recovery
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of IBIAS and IOPP, thus at VHV = 125 V is observed the IBIAS only, because IOPC is switched off.
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NCP1239
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(For typical values TJ = 25°C, for min/max Values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Oscillation Frequency
(65-kHz Version)
fOSC
60
65
70
kHz
Oscillation Frequency
(100-kHz Version)
fOSC
92
100
108
kHz
INTERNAL OSCILLATOR
Maximum Duty-Cycle
Frequency Jittering
In Percentage of fOSC – Jitter is
Kept even in Foldback Mode
Swing Frequency
DMAX
76
80
84
%
fJITTER
−
±5
−
%
fSWING
−
240
−
Hz
FEEDBACK SECTION
Equivalent AC Resistor from FB to GND
(Note 1)
REQ
−
25
−
kW
Internal Pull-Up Voltage on FB Pin
FB open
VFB(ref)
4.1
4.3
−
V
KFB
−
4
−
VFREEZE
−
1.0
−
V
VFB to Current Setpoint Division Ratio
Feedback Voltage below which the Peak
Current is Frozen
FREQUENCY FOLDBACK
Frequency Foldback Level on FB Pin
≈ 59% of Maximum Peak
Current
VFOLD
−
1.90
−
V
Transition Frequency below which Skip-Cycle
Occurs
VFB = VSKIP + 0.5 V
fTRANS
22
26
30
kHz
End of Frequency Foldback Feedback Level
fSW = fMIN
VFOLD(end)
−
1.50
−
V
VSKIP
−
0.80
−
V
VSKIP(hyst)
−
30
−
mV
S65
S100
−
−
−29
−45
−
−
mV/ms
KOPP
−
0.54
−
mA/V
Skip-Cycle Level Voltage on FB Pin
Hysteresis on the Skip Comparator
(Note 1)
INTERNAL RAMP COMPENSATION
Compensation Ramp Slope
FSW = 65 kHz, RUP = 30 kW
FSW = 100 kHz, RUP = 30 kW
OVERPOWER COMPENSATION (OPP)
VHV to IOPP Conversion Ratio
Current Flowing Out of CS Pin
(Note 2)
VHV = 125 V
VHV = 162 V
VHV = 328 V
VHV = 365 V
IOPP(125)
IOPP(162)
IOPP(328)
IOPP(365)
−
−
−
105
0
20
110
130
−
−
−
150
mA
Percentage of Applied OPP Current
VFB < VFOLD
IOPP1
−
0
−
%
Percentage of Applied OPP Current
VFB > VFOLD + 0.7 V (VOPP)
IOPP2
−
100
−
%
Clamped OPP Current
VHV > 365 V
IOPP3
105
130
150
mA
tWD(OPP)
−
32
−
ms
Watchdog Timer for DC Operation
BROWN-OUT (BO)
Brown-Out Thresholds (A, B, C & E versions)
VHV Increasing
VBO(on)
100
110
120
V
Brown-Out Thresholds (A, B, C & E versions)
VHV Decreasing
VBO(off)
93
101
109
V
Brown-Out Thresholds (D version only)
VHV Increasing
VBO(on)
92
101
110
V
Brown-Out Thresholds (D version only)
VHV Decreasing
VBO(off)
87
95
103
V
Timer Duration
VHV Decreasing
tBO
54
68
82
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of IBIAS and IOPP, thus at VHV = 125 V is observed the IBIAS only, because IOPC is switched off.
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NCP1239
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(For typical values TJ = 25°C, for min/max Values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
FAULT INPUT (OTP/OVP)
Over-Voltage Protection Threshold
VFAULT Increasing
VFAULT(OVP)
2.8
3.0
3.2
V
Over-Temperature Protection Threshold
VFAULT Decreasing
VFAULT(OTP)
0.37
0.40
0.43
V
NTC Biasing Current
VFAULT = 0 V
IOTP
39
45
51
mA
Additional NTC Biasing Current during
Soft-Start Only
VFAULT = 0 V − During
Soft-Start Only
IOTP_boost
38
44
50
mA
Latch Clamping Voltage
IFAULT = 0 mA
VFAULT(clamp)0
1.1
1.35
1.6
V
Latch Clamping Voltage
IFAULT = 1 mA
VFAULT(clamp)1
2.2
2.7
3.2
V
Blanking Time after Drive Turn Off
tLATCH(blank)
−
1
−
ms
Number of Clock Cycles before Latch
Confirmation
tLATCH(count)
−
4
−
tOCP
51
64
77
ms
tAUTOREC
0.85
1
1.35
s
Latched Over Voltage Protection on VCC Pin
VCC(OVP)
24.0
25.5
27.0
V
Delay before OVP on VCC Confirmation
tOVP(delay)
−
20
−
ms
OVER-CURRENT PROTECTION (OCP)
Internal OCP Timer Duration
Auto-Recovery Timer
VCC OVER-VOLTAGE (VCC OVP)
THERMAL SHUTDOWN (TSD)
Temperature Shutdown
TJ Increasing (Note 1)
TSHDN
135
150
165
°C
Temperature Shutdown Hysteresis
TJ Decreasing (Note 1)
TSHDN(hys)
−
20
−
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Guaranteed by design
2. CS pin source current is a sum of IBIAS and IOPP, thus at VHV = 125 V is observed the IBIAS only, because IOPC is switched off.
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NCP1239
13.0
11.0
12.5
10.5
VCC(min) (V)
VCC(on) (V)
TYPICAL PERFORMANCE CHARACTERISTICS
12.0
11.5
11.0
−40
10.0
9.5
−20
0
20
40
60
80
100
9.0
−40
120
−20
0
20
40
60
80
100
120
Temperature (5C)
Temperature (5C)
Figure 3. VCC(on) vs. Junction Temperature
Figure 4. VCC(min) vs. Junction Temperature
1.7
1.5
VCC(inhibit) (V)
VCC(off) (V)
9.2
8.8
8.4
1.3
1.1
0.9
8.0
−40
−20
0
20
40
60
80
100
0.7
−40
120
−20
0
20
40
60
80
100
120
Temperature (5C)
Temperature (5C)
Figure 5. VCC(off) vs. Junction Temperature
Figure 6. VCC(inhibit) vs. Junction Temperature
4.0
3.0
3.6
ICC2 (mA)
ICC2 (mA)
2.6
2.2
3.2
2.8
2.4
1.8
2.0
1.4
−40
−20
0
20
40
60
80
100
1.6
−40
120
Temperature (5C)
−20
0
20
40
60
80
100
120
Temperature (5C)
Figure 7. ICC2 (65-kHz Version) vs. Junction
Temperature
Figure 8. ICC2 (100-kHz Version) vs. Junction
Temperature
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NCP1239
0.8
4.5
0.7
4.0
0.6
3.5
ISTART2 (mA)
ISTART1 (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.4
0.3
0.2
−40
3.0
2.5
2.0
−20
0
20
40
60
80
100
1.5
−40
120
−20
0
20
40
60
80
100
120
Temperature (5C)
Temperature (5C)
Figure 9. ISTART1 vs. Junction Temperature
Figure 10. ISTART2 vs. Junction Temperature
0.84
24
20
VLIMIT1 (V)
ILEAK1 (mA)
0.82
16
12
0.80
8
0.78
4
0
−40
−20
0
20
40
60
80
100
0.76
−40
120
−20
0
20
40
60
80
100
120
Temperature (5C)
Temperature (5C)
Figure 11. ILEAK1 vs. Junction Temperature
Figure 12. VLIMIT1 vs. Junction Temperature
40
1.30
35
30
tDEL (ns)
VLIMIT2 (V)
1.25
1.20
25
20
1.15
15
1.10
−40
−20
0
20
40
60
80
100
10
−40
120
Temperature (5C)
−20
0
20
40
60
80
100
Temperature (5C)
Figure 13. VLIMIT2 vs. Junction Temperature
Figure 14. tDEL vs. Junction Temperature
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120
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
380
120
340
100
tLEB2 (ns)
tLEB1 (ns)
300
260
80
220
60
180
140
−40
−20
0
20
40
60
80
100
40
−40
120
0
20
40
60
80
100
120
Temperature (5C)
Temperature (5C)
Figure 15. tLEB1 vs. Junction Temperature
Figure 16. tLEB2 vs. Junction Temperature
70
10
68
fOSC (kHz)
9
tSS (ms)
−20
8
66
64
7
62
−20
0
20
40
60
80
100
60
−40
120
0
20
40
60
80
100
120
Temperature (5C)
Figure 17. tSS vs. Junction Temperature
Figure 18. fOSC (65-kHz Version) vs. Junction
Temperature
108
84
104
82
100
96
92
−40
−20
Temperature (5C)
DMAX (%)
fOSC (kHz)
6
−40
80
78
−20
0
20
40
60
80
100
76
−40
120
Temperature (5C)
−20
0
20
40
60
80
100
120
Temperature (5C)
Figure 19. fOSC (100-kHz Version) vs. Junction
Temperature
Figure 20. DMAX vs. Junction Temperature
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10
NCP1239
TYPICAL PERFORMANCE CHARACTERISTICS
26
150
25
IOOP3 (mA)
REQ (kW)
140
24
23
120
22
21
−40
−20
0
20
40
60
80
100
110
−40
120
−20
0
20
40
60
80
100
120
Temperature (5C)
Temperature (5C)
Figure 21. REQ vs. Junction Temperature
Figure 22. IOOP3 vs. Junction Temperature
109
120
116
105
VBO(off) (V)
VBO(on) (V)
130
112
108
101
97
104
100
−40
−20
0
20
40
60
80
100
93
−40
120
−20
0
20
40
60
80
100
120
Temperature (5C)
Temperature (5C)
Figure 23. VBO(on) vs. Junction Temperature
Figure 24. VBO(off) vs. Junction Temperature
82
3.2
78
3.1
VFAULT(OVP) (V)
tBO (ms)
74
70
66
62
3.0
2.9
58
54
−40
−20
0
20
40
60
80
100
2.8
−40
120
−20
0
20
40
60
80
100
120
Temperature (5C)
Temperature (5C)
Figure 25. tBO vs. Junction Temperature
Figure 26. VFAULT(OVP) vs. Junction Temperature
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11
NCP1239
0.43
51
0.42
49
0.41
47
IOTP (mA)
VFAULT(OTP) (V)
TYPICAL PERFORMANCE CHARACTERISTICS
0.40
0.39
43
0.38
41
0.37
−40
−20
0
20
40
60
80
100
39
−40
120
−20
0
20
40
60
80
100
120
Temperature (5C)
Temperature (5C)
Figure 27. VFAULT(OTP) vs. Junction Temperature
Figure 28. IOTP vs. Junction Temperature
1.3
73
1.2
tAUTOREC (s)
69
tOCP (ms)
45
65
1.1
1.0
61
0.9
57
−40
−20
0
20
40
60
80
100
0.8
−40
120
20
40
60
80
100
120
Temperature (5C)
Figure 29. tOCP vs. Junction Temperature
Figure 30. tAUTOREC vs. Junction Temperature
26.5
VCC(OVP) (V)
0
Temperature (5C)
27.0
26.0
25.5
25.0
24.5
24.0
−40
−20
−20
0
20
40
60
80
100
120
Temperature (5C)
Figure 31. VCC(OVP) vs. Junction Temperature
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NCP1239
DEFINITION
General
this domain, the controller observes the feedback pin and
when it reaches a level of 1.9 V, the oscillator starts to reduce
its switching frequency as the feedback level continues to
decrease. When the feedback level reaches 1.5 V, the
frequency hits its lower stop at 26 kHz. When the feedback
pin goes further down and reaches 1.0 V, the peak current
setpoint is internally frozen. Below this point, if the power
continues to drop, the controller enters classical skip-cycle
mode at a 31% frozen peak current.
The NCP1239 implements a standard current mode
architecture where the switch-off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part-count and cost effectiveness are
the key parameters, particularly in low-cost ac-dc adapters,
open-frame power supplies etc. The NCP1239 packs all the
necessary components normally needed in today modern
power supply designs, bringing several enhancements such
as a non-dissipative over power protection (OPP),
a brown-out protection or HV start-up current source.
Internal Soft-Start
A soft-start precludes the main power switch from being
stressed upon start-up. In this controller, the soft-start is
internally fixed to 8 ms. Soft-start is activated when a new
start-up sequence occurs or during an auto-recovery hiccup.
Current-Mode Operation with Internal Ramp
Compensation
Implementing peak current mode control operating at a 65
or 100-kHz switching frequency, the NCP1239 offers
a fixed internal compensation ramp that can easily by
summed up to the sensed current. The controller can be used
in CCM applications with wide input voltage range thanks
to its fixed ramp compensation that prevents the appearance
of sub-harmonic oscillations
Fault Input
The NCP1239 includes a dedicated fault input accessible
via its fault pin (pin 1). It can be used to sense an
over-voltage condition on the adapter. The circuit can be
latched off by pulling the pin above the upper fault threshold,
VFAULT(OVP), typically 3.0 V. The controller is also disabled
if the fault pin voltage, VFAULT, is pulled below the lower
fault threshold, VFAULT(OTP), typically 0.4 V. The lower
threshold is normally used for detecting an over-temperature
fault (by the means of an NTC).
Internal Brown-Out Protection
A portion of the bulk voltage is internally sensed via the
high-voltage pin monitoring (pin 8). When the voltage on
this pin is too low, the part stops pulsing. No re-start attempt
is made until the controller senses that the voltage is back
within its normal range. When the brown-out comparator
senses the voltage is acceptable, de-latch occurs and the
controller authorizes a re-start synchronized with VCC(on).
OVP Protection on VCC
It is sometimes interesting to implement a circuit
protection by sensing the VCC level. This is what this
controller does by monitoring its VCC pin. When the voltage
on this pin exceeds 25.5 V typical, the pulses are
immediately stopped and the part enters in an endless hiccup
or auto-recovery mode depending on controller options.
Adjustable Overpower Compensation
The high input voltage sensed on the HV pin is converted
into a current. This current builds an offset superimposed on
the current sense voltage which is proportional to the input
voltage. By choosing the resistance value in series with the
CS pin, the amount of compensation can be adjusted to the
application.
Short-Circuit/Overload Protection
Short-circuit and especially overload protections are
difficult to implement when a strong leakage inductance
between auxiliary and power windings affects the
transformer (the aux winding level does not properly
collapse in presence of an output short). Here, every time the
internal 0.8-V maximum peak current limit is activated, an
error flag is asserted and a time period starts, thanks to the
64-ms timer. When the fault is validated, all pulses are
stopped and the controller enters an auto-recovery burst
mode, with a soft-start sequence at the beginning of each
cycle. An internal timer keeps the pulses off for 1 s typically
which, associated to the 64-ms pulsing re-try period, ensures
a duty-cycle in fault mode less than 10%, independent from
the line level. As soon as the fault disappears, the SMPS
resumes operation. Please note that some version offers an
auto-recovery mode (B, C, D and E versions) as we just
described, some do not and latch off in case of a short-circuit
(A versions).
High-Voltage Start-Up
Low standby power results cannot be obtained with the
classical resistive start-up network. In this part,
a high-voltage current-source provides the necessary
current at start-up and turns off afterwards.
EMI Jittering
An internal low-frequency modulation signal varies the
pace at which the oscillator frequency is modulated. This
helps spreading out energy in conducted noise analysis. To
improve the EMI signature at low power levels, the jittering
will not be disabled in frequency foldback mode (light load
conditions).
Frequency Foldback Capability
A continuous flow of pulses is not compatible with
no-load/light-load standby power requirements. To excel in
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13
NCP1239
HV CURRENT SOURCE PIN
• Over Power Protection: HV Pin Voltage is Sensed to
The NCP1239 HV circuitry provides three features:
• Start-Up Current Source to Charge the VCC Capacitor
•
Determine the Amount of OPP Current Flowing Out
the CS Pin
at Power On
Brown-Out Protection: when the HV Pin Voltage is
below 101 V for the 68-ms Blanking Time,
the NCP1239 Stops Operating and Recovers when
the HV Pin Voltage Exceeds 110 V (Typical Values)
The HV pin can be connected either to the bulk capacitor
or to the input line terminals through a diode. It is further
recommended to implement one or two resistors (in the
range of 2.2 kW) to reduce the noise that can be picked-up
by the HV pin.
START-UP SEQUENCE
• Charge from VCC(inhibit) to VCC(min):
The start-up time of a power supply largely depends on the
time necessary to charge the VCC capacitor to the controller
start-up threshold (VCC(on) which is 12 V typically). The
NCP1239 high-voltage current-source provides the
necessary current for a prompt start-up and turns off
afterwards. The delivered current (ISTART1) is reduced to
less than 0.5 mA when the VCC voltage is below VCC(inhibit)
(1.2 V typically). This feature reduces the die stress if the
VCC pin happens to be accidentally grounded. When VCC
exceeds VCC(inhibit), a 3-mA current (ISTART2) is provided
and charges the VCC capacitor. Please note that the internal
IC consumption is increased from few mA to 310 mA (ICC4)
when VCC crosses VCC(min) in order to have internal logic
wake-up when VCC reaches VCC(on).
The VCC charging time is then the total of the three
following durations:
• Charge from 0 V to VCC(inhibit):
t START1 +
V CC(inhibit) @ C V
CC
I START1 * ICC5
t START2 +
ǒVCC(min) * VCC(inhibit)Ǔ @ CV
CC
I START2 * ICC5
• Charge from VCC(min) to VCC(on):
t START3 +
ǒVCC(on) * VCC(min)Ǔ @ CV
CC
I START2 * ICC4
t START1 +
t START2 +
(eq. 1)
t START3 +
12 @ 22 u
500 u * 20 u
+ 55 ms
(10 * 1.2) @ 22 u
3 m * 20 u
(12 * 10) @ 22 u
3 m * 310 u
+ 65 ms
+ 16 ms
Vcc(on)
Vcc(min)
Vcc(inhibit)
tstart1
(eq. 3)
Assuming a 22-mF VCC capacitor is selected and replacing
ISTART1, ISTART2, ICC4, ICC5, VCC(inhibit) and VCC(on) by
their typical values, it comes:
t START + t START1 ) t START2 ) t START3 + 136 ms
vcc(t)
(eq. 2)
tstart2
tstart3
Figure 32. The VCC at Start-Up is Made of Two Segments Given the Short-Circuit Protection
Implemented on the HV Source
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14
(eq. 4)
(eq. 5)
(eq. 6)
(eq. 7)
NCP1239
If the VCC capacitor is first dimensioned to supply the
controller for the traditional 5 to 50 ms until the auxiliary
winding takes over, no-load standby requirements usually
cause it to be larger. The HV start-up current source is then
a key feature since it allows keeping short start-up times with
large VCC capacitors (the total start-up sequence duration is
often required to be less than 1 s).
BROWN-OUT CIRCUITRY
For the vast majority of controllers, input line sensing is
performed via a resistive network monitoring the bulk
voltage or the incoming ac signal. When in the quest of low
standby power, the external network adds a consumption
burden and deteriorates the power supply standby power
performance. Owing to its proprietary high-voltage
technology, ON Semiconductor now offers onboard line
sensing without using an external network. The system
includes a 90-MW resistive network that brings a minimum
start-up threshold and an auto-recovery brown-out
protection. Both levels are independent from the input
voltage ripple. The brown-out thresholds are fixed (see
levels in the electrical characteristics table), but they are
designed to fit most of standard ac-dc converter
applications. The simplified internal schematic appears in
Figure 33 while typical operating waveforms are drawn in
Figure 34 and Figure 35.
Vbulk
HV
N
Rbo_H
BO_OK
EMI
Filter
Rbo_L
L1
GND
VBO
Figure 33. A Simplified View of the Brown-Out Circuitry
When the HV pin voltage drops below the VBO(off)
threshold, the brown-out protection trips: the controller
stops generating DRV pulses once the 68-ms BO timer
elapses. VCC is discharged to VCC(min) by the controller
consumption itself. When this level is reached, the HV
current source is activated to lifts VCC up again. At new
VCC(on), BO signal is again sensed. If VHV > VBO(on), the
parts restarts. If the condition is not met, no drive pulse is
delivered and internal IC consumption brings VCC down
again. As a result, VCC operates in hiccup mode during a BO
event.
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15
NCP1239
BO_OK = "0"
è Drive pulse stops
vcc(t)
Vcc(on)
Vcc(min)
Vcc hiccup waiting
BO signal
Vcc(off)
vDRV(t)
No pulse area
t
BO(t)
BO_OK = "1"
BO_OK = "1"
BO_OK = "0"
t
Figure 34. BO Event during Normal Operation
vcc(t)
BO no OK
è No drive pulse
First drive pulse
Vcc(on)
Vcc(min)
Vcc(off)
Vcc hiccup waiting
BO signal
BO_OK = "1"
è Wait the next Vcc(on) for
fresh start-up sequence
Vcc(inhibit)
t
BO(t)
BO_OK = "1"
BO_OK = "0"
t
Figure 35. BO Event before Start-Up
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16
NCP1239
OVER POWER PROTECTION
Over Power Protection (OPP) is a known means to limit
the output power runaway at high mains. Several elements
such as propagation delays and operating mode explain why
a converter operated at high line delivers more power than
at low line. NCP1239 senses the input voltage via HV pin.
This line voltage is transformed into a current information
further applied to the current sense pin (CS). A resistor
Vbulk
placed in series from the sense resistor to the CS pin will
create an offset voltage proportional to the input voltage
variation. An added current sink will ensure a zero OPP
current at low line (125 V dc), leaving the converter power
capability intact in the lowest operating voltage. Figure 36
presents the internal simplified architecture of this OPP
circuitry.
HV
HV detection
& sampling
N
HV sample
EMI
Filter
L1
OPP current
generation
Vfb
Iopp
ROPP
CS
To CS
comparator
offset
Rsense
Figure 36. Over Power Protection is Provided via the Bulk Voltage Present on HV Pin
The HV voltage will be transformed into a current equal
to 67.5 mA when the HV pin is biased to 125 V. However,
there is an internal fixed sink of 67.5 mA. Therefore, the net
current flowing into ROPP is 0 at this low-voltage input
(≤ 125 V dc), ensuring an almost non-compensated
converter at low line: at a 115-V rms input (162 V dc), the
current from the OTA block will induce a 87.5-mA current,
turning into a 20-mA offset current flowing into ROPP. Now,
assume a 260-V rms input voltage (365 V dc), the controller
will generate an offset current of:
365 @ 0.54 u * 67.5 u + 130 mA
250 m
130 u
+ 192 kW
(eq. 9)
A small 100−220-pF capacitor closely connected between
the CS and GND pins will form an effective noise filter and
nicely improves the converter immunity. Now, with this
1.92-kW resistance, the low-line 20-mA offset current will
incur a 38-mV drop, which, in relationship to a 800-mV
maximum peak, generates a small 5% reduction. Assuming
a full DCM operation, the power would be reduced by 0.952
or 9.75% only. Please note that the OPP current is clamped
for a HV pin voltage greater than 365 V dc. Should you lift
the pin above this voltage, there will be no increase of the
OPP current.
The offset voltage can affect the standby power
performance by reducing the peak current setpoint in
light-load conditions. For this reason, it is desirable to cancel
(eq. 8)
Assume we need to reduce the maximum peak current
setpoint by 250 mV to limit the maximum power at the
considered 260-V rms input. In that case, we will need to
generate a 250-mV offset across ROPP. With a 130-mA
current, ROPP should be equal to:
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NCP1239
its action as soon as frequency folback occurs. A typical
curve variation is shown in Figure 37. At low power, below
the frequency folback starting point, 100% of the OPP
current is internally absorbed and no offset is created
through the CS pin. When feedback increases again and
reaches the frequency foldback point, as the frequency goes
up, OPP starts to build up and reaches its full value at
VFOLD + 0.7 V.
vFB(t)
max
Fsw
increases
Fsw
decreases
+ 0.7 V
Vfold
t
IOPP(%)
100
0
t
Figure 37. The OPP Current is Applied when the Feedback Voltage Exceeds the Folback Point. It is 0 below it
FAULT INPUT
where VZ is the Zener diode Voltage.
The NCP1239 includes a dedicated fault input accessible
via the fault pin. Figure 38 shows the architecture of the fault
input. The controller can be latched by pulling up the pin
above the upper fault threshold, VFAULT(OVP), typically
3.0 V. An active clamp prevents the Fault pin voltage from
reaching the VFAULT(OVP) if the pin is open. To reach the
upper threshold, the external pull-up current has to be higher
than the pull-down capability of the clamp.
V FAULT(OVP) * V FAULT(clamp)
R FAULT(clamp)
+
3 V * 1.35 V
1.35 kW
,
The controller can also be latched off if the fault pin
voltage, VFAULT, is pulled below the lower fault threshold,
VFAULT(OTP), typically 0.4 V. This capability is normally
used for detecting an over-temperature fault by means of an
NTC thermistor. A pull up current source IOTP, (typically
45 mA) generates a voltage drop across the thermistor. The
resistance of the NTC thermistor decreases at higher
temperatures resulting in a lower voltage across the
thermistor. The controller detects a fault once the thermistor
voltage drops below VFAULT(OTP).
The circuit detects an over-temperature situation when:
(eq. 10)
i.e. approximately 1.2 mA
R NTC @ I OTP + V FAULT(OTP)
This function is typically used to detect a VCC or auxiliary
winding over-voltage by means of a Zener diode generally
in series with a small resistor (see Figure 38).
Neglecting the resistor voltage drop, the OVP threshold is
then:
V AUX(OVP) + V Z ) V FAULT(OVP)
(eq. 12)
Hence, the OTP protection trips when
R NTC +
(eq. 11)
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18
V FAULT(OTP)
I OTP
+ 8.9 kW (Typically)
(eq. 13)
NCP1239
The controller bias current is reduced during power up by
disabling most of the circuit blocks including IFAULT(OTP).
This current source is enabled once VCC reaches VCC(min).
A bypass capacitor is usually connected between the Fault
and GND pins. It will take some time for VFAULT to reach
its steady state value once IOTP is enabled. Therefore, the
lower fault comparator (i.e. over-temperature detection) is
ignored during soft-start. In addition, in order to speed up
this fault pin capacitor, OTP current is doubled during the
soft-start period.
Vaux
600 ns
Time constant
1 ms
Blanking Time
DRV
Falling edge
IOTP
Fault
NTC
4
RST
VFault(OVP)
Vdd
Up counter
Latch
S
Q
Q
OVP/OTP gone
R
Rfault(clamp)
Vfault(clamp)
Power on
reset
VFault(OTP)
Figure 38. Fault Detection Schematic
OVP/OTP events occurred for 4 successive drive clock
pulses before actually latching the part.
When the part is latched-off, the drive is immediately
turned off and VCC goes in endless hiccup mode. The power
supply needs to be un-plugged to reset the part (VCC(reset) or
BO event). Please note that this protection on the Fault pin
is autorecovery for the E version.
As a matter of fact, the controller operates normally while
the fault pin voltage is maintained within the upper and
lower fault thresholds. Upper and lower fault detectors have
blanking delays to prevent noise from triggering them. Both
OVP and OTP comparator output are validated only if its
high-state duration lasts a minimum of 600 ns. Below this
value, the event is ignored. Then, a counter ensures that
AUTO-RECOVERY SHORT-CIRCUIT PROTECTION
In case of output short-circuit or if the power supply
experiences a severe overloading situation, an internal error
flag is raised and starts a countdown timer. If the flag is
asserted longer than the timer’s programmed value (64 ms
typical), the driving pulses are stopped and a 1-s
auto-recovery timer starts. If VCC voltage is below
VCC(min), HV current source is activated to build up the
voltage to VCC(on). On the contrary, if VCC voltage is above
VCC(min), HV current source is not activated, VCC falls
down as the auxiliary pulses are missing and the controller
waits that VCC(min) is crossed to enable the stat-up current
source. During the timer count down, the controller
purposely ignores the re-start when VCC crosses VCC(on) and
waits for another VCC cycle. By lowering the duty cycle in
fault condition, it naturally reduces the average input power
and the rms current in the output cable. Illustration of such
principle appears in Figure 39. Please note that soft-start is
activated upon re-start attempt.
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NCP1239
vcc(t)
Overload on the
output voltage
Vcc(on)
Vcc(min)
OCP timer
OCP timer
Autorecovery timer
Autorecovery timer
Vcc(off)
t
vDRV(t)
No pulse area
t
Figure 39. An Auto-Recovery Hiccup Mode is Entered in Case a Faulty Event Longer than 64 ms
is Acknowledged by the Controller
The hiccup is operating regardless of the brown-out level.
However, when the internal comparator toggles indicating
that the controller recovers from a brown-out situation (the
input line was ok, then too low and back again to normal),
the hiccup is interrupted and the controller re-starts to the
next available VCC(on). Figure 40 displays the resulting
waveform: the controller is protecting the converter against
an overload. The mains suddenly went down, and then back
again at a normal level. Right at this moment, the hiccup
logic receives a reset signal and ignores the next hiccup to
immediately initiate a re-start signal.
vcc(t)
Overload on the
output voltage
Vcc(on)
Vcc(min)
OCP timer
Autorecovery timer
Vcc(off)
t
vDRV(t)
No pulse area
t
BO(t)
BO_OK = "1"
BO_OK = "1"
BO_OK = "0"
Figure 40. BO Event in Auto-Recovery or Latch Mode
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20
t
NCP1239
LATCHED SHORT CIRCUIT PROTECTION WITH PRE-SHORT
maximum power is asked to increase VOUT, the error flag is
temporarily raised until regulation is met. If during the time
the flag is raised an UVLO event is detected, the part latches
off immediately. When latched, VCC hiccups between the
two levels, VCC(on) and VCC(min) until a reset occurs
(Brown-out event or VCC cycled down below VCC(reset)). In
normal operation, if a UVLO event is detected for any
reason while the error flag is not asserted, the controller will
naturally resume operations. Please also note that this
pre-short protection is activated only during start-up
sequence. In normal operation, even if an UVLO event
occurs while the error flag is asserted, the controller will
enters in auto-recovery mode. Details of this behavior are
given in Figure 41.
In some applications, the controller must be fully latched
in case of an output short circuit presence. In that case, you
would select options A in the controller list. When the error
flag is asserted, meaning the controller is asked to deliver its
full peak current, upon timer completion, the controller
latches off: all pulses are immediately stopped and VCC
hiccups between the two levels, VCC(on) and VCC(min).
However, in presence of a small VCC capacitor, it can very
well be the case where the stored energy does not give
enough time to let the timer elapse before VCC touches the
VCC(off). When this happens, the latch is not acknowledged
since the timer countdown has been prematurely aborted. To
avoid this problem, NCP1239 combines the error flag
assertion together with the UVLO flag: upon start up, as
vcc(t)
latched reset
Fb
OK
resumed
Vcc(on)
Vcc(min)
Vcc(off)
New sequence
vDRV(t)
UVLO
AND
OCP flag
at start−up
Glitch or
overload
t
t
1
OCP flag
0
t
Figure 41. UVLO Event during Start-Up Sequence and in Normal Operation
LATCHING OR AUTO-RECOVERY MODE
The B and C versions are auto-recovery. When an
overload fault is detected, they stop generating drive pulses
and VCC hiccups between VCC(min) and VCC(on) during the
auto-recovery timer before initiate a fresh start-up sequence
with soft-start.
The A versions latch off when they detect an overload
situation. In this condition, the circuit stops generating drive
pulses and let VCC drop down. When VCC has reached
10-VCC(min) level, the circuit charged up VCC to VCC(on).
The controller enters in an endless hiccup mode. The device
cannot recover operation until VCC drops below VCC(reset)
or brownout recovery signal is applied. Practically, the
power supply must be unplugged to be reset
(VCC < VCC(reset)). Please note that the controller always
enters in auto-recovery mode when the UVLO event occurs
without internal error flag signal (ie: without overload).
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21
NCP1239
FREQUENCY FOLDBACK
1.5 V, the frequency is fixed and cannot go further down.
The peak current setpoint is free to follow the feedback
voltage from 3.2 V (full power) down to 1 V. At 1 V, as both
frequency and peak current are frozen (250 mV or ≈31% of
the maximum 0.8-V setpoint) the only way to further reduce
the transmitted power is to enter skip cycle. This is what
happens when the feedback voltage drops below 0.8 V
typically. Figure 42 depicts the adopted scheme for the part.
The reduction of no-load standby power associated with
the need for improving the efficiency, requires to change the
traditional fixed-frequency type of operation. This
controller implements a switching frequency folback when
the feedback voltage passes below a certain level, VFOLD,
set at 1.9 V. At this point, the oscillator turns into
a Voltage-Controlled Oscillator (VCO) and reduces
switching frequency down to a feedback voltage of 1.5 V
where switching frequency is 26 kHz typically. Below
Frequency
Peak current setpoint
FSW
VCS
Vfold(end)
FB
max
65 kHz
max
0.8 V
[0.47 V
min
26 kHz
[0.25 V
skip
0.8 V 1.5 V
1.9 V
Vskip
Vfold
3.2 V
VFB
min
0.8 V
1.0 V
Vskip Vfreeze
1.9 V
3.2 V
VFB
Vfold
Figure 42. By Observing the Voltage on the Feedback Pin, the Controller Reduces its Switching Frequency for an
Improved Performance at Light Load
SLOPE COMPENSATION
Slope compensation is a known means to fight
sub-harmonic oscillations in peak-current mode controlled
power converters (flyback in our case). By adding an
artificial ramp to the current sense information or
subtracting it from the feedback voltage, you implement
slope compensation. How much compensation do you need?
The simplest way is to consider the primary-side inductor
downslope and apply 50% of its value for slope
compensation. For instance, assume a 65-kHz/19-V output
flyback converter whose transformer turns ratio 1:N is
1:0.25. The primary inductor is 600 mH. As such, assuming
a 1-V forward drop of the output rectifier, the downslope is
evaluated to:
S OFF +
V OUT ) V f
NL p
+
19 ) 1
0.25 @ 600 u
+
If we have a 0.33-W sense resistor, then the current
downslope turns into a voltage downslope whose value is
simply:
S ȀOFF + S OFF @ R SENSE +
(eq. 15)
+ 133 m @ 0.33 [ 44 mVńms
50% of this value is 22 mV/ms. The internal slope
compensation level is typically 29 mV/ms (for the 65-kHz
version) so it will nicely compensate this design example.
What if my converter is under compensated? You can still
add compensation ramp via a simple RC arrangement
showed in Figure 43. Please look at AND8029 available
from www.onsemi.com regarding calculation details of this
configuration.
(eq. 14)
+ 133 kAńs or 133 mAńms
www.onsemi.com
22
NCP1239
DRV
D1
1N4148
R1
C1
R4
CS
R3
Rsense
Figure 43. An Easy Means to Add Slope Compensation is by Using an Extra RC Network Building a Ramp
from the Drive Signal
A 2ND OVER-CURRENT COMPARATOR FOR ABNORMAL OVER-CURRENT FAULT DETECTION
threshold of the comparator, VILIM2, typically 1.2 V, is set
50 % higher than VLIMIT1, to avoid interference with normal
operation. Four consecutive abnormal over-current faults
cause the controller to enter latch mode. The count to 4
provides noise immunity during surge testing. The counter
is reset each time a DRV pulse occurs without activating the
Fault Over-Current Comparator.
Please note that like timer-based short-circuit protection,
A versions are latching off compared to B and C versions
that are auto-recovery.
A severe fault like a winding short-circuit can cause the
switch current to increase very rapidly during the on-time.
The current sense signal significantly exceeds VILIM1. But,
because the current sense signal is blanked by the LEB
circuit during the switch turn on, the power switch current
can become huge causing system damage.
The NCP1239 protects against this fault by adding an
additional comparator for abnormal over-current fault
detection. The current sense signal is blanked with a shorter
LEB duration, tLEB2, typically 120 ns, before applying it to
the abnormal over-current fault comparator. The voltage
OVER-VOLTAGE PROTECTION ON VCC PIN
latching-off versions, the part can be reset by cycling down
its VCC, for instance by pulling off the power plug but also
if a brown-out recovery is sensed by the controller. This
technique offers a simple and cheap means to protect the
converter against optocoupler.
The NCP1239 hosts a dedicated comparator on the VCC
pin. When the voltage on this pin exceeds 25.5 V typically
for more than 20 ms, a signal is sent to the internal latch and
the controller immediately stops the driving pulses while
remaining in a lockout state. Depending controller options,
this OVP on VCC pin can be auto-recovery or latched. For
PROTECTING FROM A FAILURE OF THE CURRENT SENSING
the 64-ms OCP timer is activated. If the timer elapses,
the controller enters in auto-recovery or endless hiccup
mode depending on the controller option. This unexpected
operation can lead to deep CCM with destructive
consequences.
A 1-mA (typically) pull-up current source, ICS, pulls up the
CS pin to disable the controller if the pin is left open.
In addition the maximum duty ratio limit (80% typically)
avoids that the MOSFET stays permanently on if the switch
current cannot reach the setpoint when for instance, the input
voltage is low or if the CS pin is grounded. In this case,
www.onsemi.com
23
NCP1239
SOFT-START
gradual increase of the power switch current during start-up.
The soft-start duration (that is, the time necessary for the
ramp to reach the VILIM1 steady state current limit), tSSTART,
is typically 8 ms.
Soft-start is achieved by ramping up an internal reference,
VSSTART, and comparing it to current sense signal. VSSTART
ramps up from 0 V once the controller powers up. The
setpoint rise is then limited by the VSSTART ramp so that a
DRIVER
The NCP1239 maximum supply voltage, VCC(max), is
25.5 V. Typical high-voltage MOSFETs have a maximum
gate-source voltage rating of 20 V. The DRV pin
incorporates an active voltage clamp to limit the gate voltage
on the external MOSFETs. The DRV voltage clamp,
VDRV(high) is typically 13.5 V with a maximum limit of 16 V.
THERMAL SHUTDOWN
temperature drops below below TSHDN by the thermal
shutdown hysteresis, TSHDN(HYS), typically 20_C.
The thermal shutdown is also cleared if VCC drops below
VCC(reset) or a brown-out fault is detected. A new power up
sequences commences at the next VCC(on) once all the faults
are removed.
An internal thermal shutdown circuit monitors the
junction temperature of the IC. The controller is disabled if
the junction temperature exceeds the thermal shutdown
threshold, TSHDN, typically 150_C. A continuous VCC
hiccup is initiated after a thermal shutdown fault is detected.
The controller restarts at the next VCC(on) once the IC
Table 5. ORDERING INFORMATION
Device
Marking
Freq.
OCP
Protection
VCC OVP
Protection
Fault Pin
Protection
BO
Levels
NCP1239AD65R2G
1239A065
65 kHz
Latch
Latch
Latch
110/101
NCP1239BD65R2G
1239B065
65 kHz
Auto-Recovery
Latch
Latch
110/101
NCP1239CD65R2G
1239C065
65 kHz
Auto-Recovery
Auto-Recovery
Latch
110/101
NCP1239DD65R2G
1239D065
65 kHz
Auto-Recovery
Latch
Latch
101/95
NCP1239ED65R2G
1239E065
65 kHz
Auto-Recovery
Auto-Recovery
Auto-Recovery
110/101
NCP1239AD100R2G
1239A100
100 kHz
Latch
Latch
Latch
110/101
NCP1239BD100R2G
1239B100
100 kHz
Auto-Recovery
Latch
Latch
110/101
Package
Shipping†
SOIC−7
(Pb-Free)
2500 /
Tape &
Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
www.onsemi.com
24
NCP1239
PACKAGE DIMENSIONS
SOIC−7
CASE 751U
ISSUE E
−A−
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5
−B− S
0.25 (0.010)
B
M
M
1
4
DIM
A
B
C
D
G
H
J
K
M
N
S
G
C
R
X 45 _
J
−T−
SEATING
PLANE
H
0.25 (0.010)
K
M
D 7 PL
M
T B
S
A
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_
8_
0.010 0.020
0.228 0.244
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
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25
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
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NCP1239/D