TI CDC857 2.5-/3.3-v phase-lock loop clock driver Datasheet

CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
D
D
D
D
D
D
Phase-Lock Loop Clock Distribution for
Double Data Rate Synchronous DRAM
Applications
Distributes One Differential Clock Input to
Ten Differential Outputs
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Clock Input
Operates at VCC = 2.5 V and AVCC = 3.3 V
Packaged in Plastic 48-Pin (DGG) Thin
Shrink Small-Outline Package (TSSOP)
Spread Spectrum Clocking Tracking
Capability to Reduce EMI
description
The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop
(PLL) clock driver. They use a PLL to precisely
align, in both frequency and phase, the feedback
(FBOUT) output to the clock (CLK) input signal.
The CDC857-3 operates at 3.3 V (PLL) and 2.5 V
(output buffer). The CDC857-2 operates at
2.5 V (PLL and output buffer).
DGG PACKAGE
(TOP VIEW)
GND
Y0
Y0
VCC
Y1
Y1
GND
GND
Y2
Y2
VCC
VCC
CLK
CLK
VCC
AVCC
AGND
GND
Y3
Y3
VCC
Y4
Y4
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
GND
Y5
Y5
VCC
Y6
Y6
GND
GND
Y7
Y7
VCC
G
FBIN
FBIN
VCC
FBOUT
FBOUT
GND
Y8
Y8
VCC
Y9
Y9
GND
One bank of ten inverting and noninverting
23
26
outputs provide ten low-skew, low-jitter copies of
24
25
CLK. Output signal duty cycles are adjusted to
50%, independent of the duty cycle at CLK.
All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs
switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to high impedance
state (3-state).
Unlike many products containing PLLs, the CDC857 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuity, the CDC857 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. If AVCC is at GND
and VCC = ON, 2 falling edges on G cause the PLL to run with FBOUT being enabled and all other outputs being
disabled, after AVCC ramps up to its specified VCC value, with G being kept low. The CDC857 is characterized
for operation from 0°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
FUNCTION TABLE
INPUTS
G
CLK
OUTPUTS
CLK
Y
Y
FBOUT
FBOUT
PLL
L
X
X
Z
Z
Z
Z
OFF
H
L
H
L
H
L
H
RUN
H
H
L
H
L
H
L
RUN
H
< 20 MHz
< 20 MHz
Z
Z
Z
Z
OFF
logic symbol
Test
Mode
Logic
G
Y0
Y0
AVCC
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Clk
Y7
Clk
Y7
Y8
PLL
Y8
FBIN
Y9
FBIN
Y9
AVCC = 3.3 V
FBOUT
FBOUT
NOTE A: All outputs are connected to VCC = 2.5 V.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
SPECIAL TEST MODES
INPUTS
OUTPUTS
VCC
ON
AVCC
0V
G
ON
0V
ON
0V
ON
0V
UP‡
UP‡
ON
ON
CLK†
Y
Y
L
L
Z
L
H
Z
H
L
L
H
↓§
↓§
H
L
H
COMMENTS
FBOUT
FBOUT
Z
Z
Z
Z
Z
Z
Clock Mode
H
L
H
Clock Mode
H
L
H
L
Clock Mode
Z
Z
L
H
PLL Mode
Z
Z
H
L
PLL Mode
Clock Mode
† Only one signal shown for this differential input.
‡ AVCC ramped up after two (2) high-to-low transitions on G input & G being low.
§ At least two (2) high-to-low transitions during AVCC = 0.
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
17
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
AVCC
16
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs. During disable (G = 0), the PLL is powered down.
CLK
CLK
13
14
I
Clock input, CLK provides the clock signal to be distributed by the CDC857 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase
lock the feedback signal to its reference signal.
FBIN
FBIN
36
35
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired
to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
FBOUT
FBOUT
32
33
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
G
37
I
Output bank enable. G is the output enable for outputs Y and Y. When G is low outputs Y are disabled
to a high-impedance state. When G is high, all outputs Y are enabled and switch at the same
frequency as CLK.
GND
1, 7, 8, 18,
24, 25, 31,
41, 42, 48
Ground
Ground
VCC
4, 11, 12,
15, 21, 28,
34, 38, 45
Power
Power supply
Y0, Y1, Y2,
Y3, Y4, Y5,
Y6, Y7, Y8,
Y9
3, 5, 10,
20, 22, 46,
44, 39, 29,
27
O
Clock outputs. These outputs provide low-skew copies of CLK.
Y0, Y1, Y2,
Y3, Y4, Y5,
Y6, Y7, Y8,
Y9
2, 6, 9,
19, 23, 47,
43, 40, 30,
26
O
Clock outputs. These outputs provide low-skew copies of CLK.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC or AVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC +0.5 V
Output voltage range, VO, (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC +0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Output clamp current, IOK (VO < 0 or VO > VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous total output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
Supply voltage, VCC
CDC857–2
voltage AVCC
Analog supply voltage,
CDC857–3
V
2.7
V
3.6
V
0.3 × VCC
V
3
DC input signal voltage (see Note 5)
CLK, FBIN
–0.3
dc
CLK, FBIN
0.35
ac
CLK, FBIN
Differential cross-point input voltage (see Note 7)
0.7 × VCC
V
0.7
VCC/2–0.2
High-level output current, IOH
Low-level output current, IOL
VCC/2
VCC+0.3
VCC+0.6
V
VCC+0.6
VCC/2+0.2
–12
V
12
Input slew rate, SR
UNIT
2.3
G input
G input
MAX
2.7
Low–level input voltage, VIL(G)
High–level input voltage, VIH(G)
Differential input signal
g
voltage,
g , VID
(see Note 6)
NOM
2.3
1
V
V
mA
mA
V/ns
Operating free-air temperature, TA
0
85
°C
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.
5. DC input signal voltage specifies the allowable dc execution of differential input.
6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level (see figure 3).
7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input voltage
All input pins
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
IOH
IOL
High-level output current
VO
Output voltage swing
Low-level output current
G
CLK, FBIN
II
Input current
IOZ
High impedance output current
High-impedance
VOC
Output crossing point voltage‡
ICCZ
Supply current, disabled
lCC
Supply current on VCC
(see Figure 7)
AICC
Su ly current on
Supply
AVCC
CDC857–2
CDC857–3
VCC = 2.3 V,
II = –18 mA
VCC = min to max, IOH= –1 mA
VCC = 2.3 V,
IOH = –12 mA
VCC = min to max, IOL = 1 mA
VCC = 2.3 V,
IOL = 12 mA
VCC = 2.3 V,
VO = 1 V
VCC = 2.3 V,
VO = 1.2 V
For load condition see Figure 3
VCC = 2.7 V,
VCC = 2.7 V,
VI = 0 V to 2.7 V
VI = 0 V to 2.7 V
VCC = 2
2.7
7 V,
VO = VCC or GND
MIN
TYP†
MAX
UNIT
–1.2
V
VCC–0.1
1.7
V
0.1
0.6
V
–18
–32
mA
26
35
mA
1.1
VCC–0.4
±10
±10
±10
(VCC/2)–
0.1
V
µA
µA
VCC/2
(VCC/2)+
0.1
V
AVCC and VCC = max,
G = L or no input CLK signal
500
800
µA
VCC = 2.7 V,
fO = 167 MHz,
All outputs switching 16 pF in 60 Ω
environment,
See Figure 3
235
300
mA
9
12
15
19
AVCC = 2.7 V,
AVCC = 3.6 V,
fO = 167 MHz
fO = 167 MHz
mA
CI
Input capacitance
VCC = 2.5 V,
VI = VCC or GND
2
pF
CO
Output capacitance
VCC = 2.5 V,VO = VCC or GND
3
pF
† All typical values are at respective nominal VCC.
‡ The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input
signal voltage and VCP is the complementary input signal voltage (see Figure 3).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
timing requirements over recommended ranges or supply voltage and operating free–air
temperature
PARAMETER
fC
TEST CONDITIONS
MIN
MAX
UNIT
66
167
MHz
40%
60%
Clock frequency
Input clock duty cycle
Stabilization time†
0.1
ms
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed–frequency, fixed–phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay,
skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation
under SSC application.
switching characteristics
TEST CONDITIONS
MIN
NOM
MAX
tPLH‡
Low–to high level propagation delay time
(see Figure 5)
PARAMETER
CLK mode/CLK to any output
1.5
3.5
6
ns
tPHL‡
High–to low level propagation delay time
(see Figure 5)
CLK mode/CLK to any output
1.5
3.5
6
ns
ten
tdis
Output enable time
CLK mode/G to any Y output
3
Output disable time
CLK mode/G to any Y output
3
t(jitter)
(jitt )
Jitter (peak-to–peak)
(peak to peak)
t(jitter)
(jitt )
Jitter (cycle
(cycle-to-cycle)
to cycle)
t(phase error)
tskew(0)
Phase error (see Figure 4)
tskew(p)
Pulse skew
Output skew (see Figure 4)
Duty cycle§ (see Figure 6)
66 MHz
110
100/125/133/167 MHz
66 MHz to 100 MHz
101 MHz to 167 MHz
ns
75
66 MHz
All differential input
in ut and out
output
ut terminals are terminated with 120 Ω/
16 pF
F as shown
h
in
i Figure
Fi
2
ns
120
100/125/133/167 MHz
65
–150
UNIT
ps
ps
150
ps
100
ps
100
ps
49.5%
50.5%
49%
51%
tr, tf
Output rise and fall times (20% – 80%)
Load = 120 Ω/16 pF
650
800
950
ps
‡ Refers to transition of noninverting output.
§ While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty
cycle = twH/tc, were the cycle time (tc) decreases as the frequency goes up.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
APPLICATION EXAMPLE
Table 1. Clock Structure and SDRAM Loads per Clock
CLOCK
STRUCTURE
NUMBER of
SDRAM LOADS
PER CLOCK
1
2
CAPACITIVE LOADING ON
THE PLL OUTPUTS (pF)
MIN
MAX
2
5
8
4
10
16
≈ 2.5”
≈ 0.6” (Split to Terminator)
SDRAM represents
a capacitive load
SDRAM
VTR
120 Ω
CLK
16 pF
120 Ω
VCP
PLL
SDRAM
CLK
0.3”
FBIN
16 pF
120 Ω
FBIN
Figure 1. Clock Structure #1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
APPLICATION EXAMPLE
≈ 2.5”
≈ 0.6” (Split to Terminator)
SDRAM represents
SDRAM
Stack
a capacitive load
CLK
120 Ω
16 pF
PLL
VTR
120 Ω
VCP
CLK
FBIN
SDRAM
Stack
120 Ω
16 pF
FBIN
0.3”
Figure 2. Clock Structure #2
differential clock signals
Figure 3 shows the differential clocks are directly terminated by a 120-Ω resistor.
VCC
Device
Under
Test
OUT
VCC
60 Ω
VTR
RT = 120 Ω
OUT
60 Ω
VCP
Receiver
Figure 3. Differential Signal Using Direct Termination Resistor
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
CLKIN
FBIN
t(phase error)
FBOUT
Yx
tsk(o)
Yx
Yx
tsk(o)
Figure 4. Phase Error and Skew Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
CLKIN
Yx or FBIN
tpd
Figure 5. Propagation Delay Time; tPLH, tPHL
Yx
Yx
tWH
tc
NOTE A: Duty cycle = tWH/tc
Figure 6. Output Duty Cycle
Yx
tc (n)
tc (n+1)
NOTE A: Cycle-to-cycle jitter = |tc(n) – tc(n+1)| over 2000 consecutive cycles.
Figure 7. Cycle-to-Cycle Jitter
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CDC857-2, CDC857-3
2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
SCAS627A – SEPTEMBER 1999 – DECEMBER 1999
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated