optical networking, optical power monitor(ing), laser diode control, optical amplifier control, EDFA control, Erbium Doped Fiber Amplifie ® LOG100 Precision LOGARITHMIC AND LOG RATIO AMPLIFIER FEATURES APPLICATIONS ● ACCURACY 0.37% FSO max Total Error Over 5 Decades ● LINEARITY 0.1% max Log Conformity Over 5 Decades ● EASY TO USE Pin-selectable Gains Internal Laser-trimmed Resistors ● WIDE INPUT DYNAMIC RANGE 6 Decades, 1nA to 1mA ● HERMETIC CERAMIC DIP ● LOG, LOG RATIO AND ANTILOG COMPUTATIONS ● ABSORBANCE MEASUREMENTS ● DATA COMPRESSION ● OPTICAL DENSITY MEASUREMENTS ● DATA LINEARIZATION DESCRIPTION resistors. The resistors are laser-trimmed for maximum precision. FET input transistors are used for the amplifiers whose low bias currents (1pA typical) permit signal currents as low as 1nA while maintaining guaranteed total errors of 0.37% FSO maximum. ● CURRENT AND VOLTAGE INPUTS The LOG100 uses advanced integrated circuit technologies to achieve high accuracy, ease of use, low cost, and small size. It is the logical choice for your logarithmic-type computations. The amplifier has guaranteed maximum error specifications over the full sixdecade input range (1nA to 1mA) and for all possible combinations of I1 and I2. Total error is guaranteed so that involved error computations are not necessary. The circuit uses a specially designed compatible thinfilm monolithic integrated circuit which contains amplifiers, logging transistors, and low drift thin-film Q1 9 Because scaling resistors are self-contained, scale factors of 1V, 3V or 5V per decade are obtained simply by pin selections. No other resistors are required for log ratio applications. The LOG100 will meet its guaranteed accuracy with no user trimming. Provisions are made for simple adjustments of scale factor, offset voltage, and bias current if enhanced performance is desired. Q2 –VCC 7 A2 1 I1 VOUT 3 A1 K=1 4 K=3 I2 14 7.5kΩ 270Ω 10 VOUT = K LOG I1 I2 220Ω International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1981 Burr-Brown Corporation SBFS014 K=5 24kΩ 6 +VCC Com 5 39kΩ Scale Factor 2 Trim Resistor values nominal only; laser-trimmed for precision gain. • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-437E Printed in U.S.A. January, 1995 SPECIFICATIONS ELECTRICAL TA = +25°C and ±VCC = ±15V, after 15 minute warm-up, unless otherwise specified. LOG100JP PARAMETER CONDITIONS TRANSFER FUNCTION Log Conformity Error(1) Initial Over Temperature MIN Either I1 or I2 1nA to 100µA (5 decades) 1nA to 1mA (6 decades) 1nA to 100µA (5 decades) 1nA to 1mA (6 decades) 0.04 0.15 0.002 0.001 1, 3, 5 0.3 0.03 K Range(2) Accuracy Temperature Coefficient ACCURACY Total Error(3) Initial TYP MAX UNITS 0.1 0.25 % % %/°C %/°C V/decade % %/°C ±55 ±30 ±25 ±20 ±25 ±30 ±37 mV mV mV mV mV mV mV VOUT = K Log (I1/I2) K = 1,(4) Current Input Operation I1, I2 = 1mA I1, I2 = 100µA I1, I2 = 10µA I1, I2 = 1µA I1, I2 = 100nA I1, I2 = 10nA I1, I2 = 1nA vs Temperature I1, I2 = 1mA I1, I2 = 100µA I1, I2 = 10µA I1, I2 = 1µA I1, I2 = 100nA I1, I2 = 10nA I1, I2 = 1nA ±0.20 ±0.37 ±0.28 ±0.033 ±0.28 ±0.51 ±1.26 mV/°C mV/°C mV/°C mV/°C mV/°C mV/°C mV/°C vs Supply I1, I2 = 1mA I1, I2 = 100µA I1, I2 = 10µA I1, I2 = 1µA I1, I2 = 100nA I1, I2 = 10nA I1, I2 = 1nA ±4.3 ±1.5 ±0.37 ±0.11 ±0.61 ±0.91 ±2.6 mV/V mV/V mV/V mV/V mV/V mV/V mV/V INPUT CHARACTERISTICS (of Amplifiers A1 and A2) Offset Voltage Initial vs Temperature Bias Current Initial vs Temperature Voltage Noise 10Hz to 10kHz, RTI Current Noise 10Hz to 10kHz, RTI AC PERFORMANCE 3dB Response(6), I2 = 10µA 1nA 1µA 10µA 1mA Step Response(6) Increasing 1µA to 1mA 100nA to 1µA 10nA to 100nA Decreasing 1mA to 1µA 1µA to 100nA 100nA to 10nA OUTPUT CHARACTERISTICS Full Scale Output (FSO) Rated Output Voltage Current Current Limit Positive Negative Impedance CC = 4500pF CC = 150pF CC = 150pF CC = 50pF ±5 mV µV/°C 1 Doubles Every 10°C 3 0.5 5(5) pA kHz kHz kHz kHz 11 7 110 µs µs µs 45 20 550 µs µs µs CC = 150pF IOUT = ±5mA VOUT = ±10V ±10 V ±10 ±5 V mA 12.5 15 0.05 2 µVrms pArms 0.11 38 27 45 CC = 150pF ® LOG100 ±0.7 ±80 mA mA Ω SPECIFICATIONS (CONT) ELECTRICAL TA = +25°C and ±VCC = ±15V, after 15 minute warm-up, unless otherwise specified. LOG100JP PARAMETER POWER SUPPLY REQUIREMENTS Rated Voltage Operating Range Quiescent Current AMBIENT TEMPERATURE RANGE Specification Operating Range Storage CONDITIONS MIN Derated Performance ±12 TYP ±15 ±7 0 –25 –40 Derated Performance MAX UNITS ±18 ±9 VDC VDC mA +70 +85 +85 °C °C °C NOTES: (1) Log Conformity Error is the peak deviation from the best-fit straight line of the VOUT vs Log IIN curve expressed as a percent of peak-to-peak full scale output. (2) May be trimmed to other values. See Applications section. (3) The worst-case Total Error for any ratio of I1/I2 is the largest of the two errors when I1 and I2 are considered separately. (4) Total Error at other values of K is K times Total Error for K = 1. (5) Guaranteed by design. Not directly measurable due to amplifier’s committed configuration. (6) 3dB and transient response are a function of both the compensation capacitor and the level of input current. See Typical Performance Curves. PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Supply ................................................................................................ ±18V Internal Power Dissipation .............................................................. 600mV Input Current ..................................................................................... 10mA Input Voltage Range .......................................................................... ±18V Storage Temperature Range ........................................... –40°C to +85°C Lead Temperature (soldering, 10s) ............................................... +300°C Output Short-circuit Duration .................................. Continuous to ground Junction Temperature ...................................................................... 175°C Bottom View I2 Input 14 1 I1 Input NC 13 2 Scale Factor Trim NC 12 3 K=1 NC 11 4 K=3 Common 10 5 K=5 –VCC 9 6 +VCC NC 8 7 Output SCALE FACTOR PIN CONNECTIONS K, V/DECADE CONNECTIONS 5 3 1.9 1 0.85 0.77 0.68 5 to 7 4 to 7 4 and 5 to 7 3 to 7 3 and 5 to 7 3 and 4 to 7 3 and 4 and 5 to 7 NC = No Connection ELECTROSTATIC DISCHARGE SENSITIVITY FREQUENCY COMPENSATION Any integral circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. 9 7 1 LOG100 14 10 6 5 4 ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. 3 CC PACKAGE INFORMATION ORDERING INFORMATION MODEL LOG100JP PACKAGE SPECIFIED TEMPERATURE RANGE 14-Pin Hermetic Ceramic DIP 0°C to +70°C MODEL LOG100JP PACKAGE PACKAGE DRAWING NUMBER(1) 14-Pin Hermetic Ceramic DIP 148(2) NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. (2) During 1994, the package was changed from plastic to hermetic ceramic. Pinout, model number, and specifications remained unchanged. The metal lid of the new package is internally connected to common, pin 10. ® 3 LOG100 TYPICAL PERFORMANCE CURVES TA = +25°C, VCC = ±15VDC, unless otherwise noted. ONE CYCLE OF NORMALIZED TRANSFER FUNCTION NORMALIZED TRANSFER FUNCTION 3 (K) Normalized Output Voltage (V) Normalized Output Voltage (V) 1 (K) I1 VOUT = K Log I2 2 (K) 1 (K) 0 (K) –1 (K) –2 (K) –3 (K) 0.9 (K) 0.8 (K) 0.7 (K) 0.6 (K) 0.5 (K) 0.4 (K) 0.3 (K) 0.2 (K) 0.1 (K) 0 0.01 0.001 0.1 1 10 100 1 1000 2 8 6 TOTAL ERROR vs INPUT CURRENT TRIMMED OUTPUT ERROR vs INPUT CURRENT 60 Trimmed Output Error (mV) 50 ±25 40 –60 Gain Error and Offset Error Trimmed to Zero –50 –40 30 I2 20 –30 I1 ±50 10 0 0 10 –20 100nA 10µA 20 1mA 1nA 100nA Input Current ( I1 or I2) 10µA 1mA Input Current (I1 or I2) 3dB FREQUENCY RESPONSE MINIMUM VALUE OF COMPENSATION CAPACITOR 1M 1M 10µA I1 = 1nA Select CC for I1 min and I2 max 100k 3dB Frequency Response (Hz) Compensation Capacitor, CC (pF) –20 –10 –10 0 1nA 10 I Current Ratio, 1 I2 ±75 Maximum Total Error (mV) 4 3 I Current Ratio, 1 I2 I1 = 10nA 10k I1 = 100nA Values below 2pF may be ignored. 1k I1 = 1µA 100 I1 = 10µA 10 I1 = 100µA to 1mA 10k 1k 10nA 100nA 1µA 10µA 100µA CC 1nA =1 I1 = 1nA LOG100 4 100nA 10nA F 0p 0 CC 0 =1 I1 = 1nA CC 10nA 100nA 1µA I2 ® 1µA 1mA to 10µA 10nA 10 1nA 1mA Input Current, I2 A 1µ to µA 10 10nA F 0p 100µA 100µA 100 1 100µA 100µA 1mA I1 = 1mA 1µA 0.1 1 1nA 100k = F 1µ 10µA 100µA 1mA THEORY OF OPERATION The base-emitter voltage of a bipolar transistor is IC KT VBE = VT l n where: VT = q IS It should be noted that the temperature dependance associated with VT = KT/q is compensated by making R1 a temperature sensitive resistor with the required positive temperature coefficient. (1) K = Boltzman’s constant = 1.381 x 10–23 DEFINITION OF TERMS T = Absolute temperature in degrees Kelvin q = Electron charge = 1.602 x 10–19 Coulombs TRANSFER FUNCTION IC = Collector current The ideal transfer function is VOUT = K log IS = Reverse saturation current where: From the circuit in Figure 1, we see that (2) Substituting (1) into (2) yields I1 I1 – VT2 l n VOUT' = VT1 l n IS1 IS2 I1 = numerator input current I2 = denominator input current. (3) ACCURACY If the transistors are matched and isothermal and VT1 = VT2, then (3) becomes: I1 I2 VOUT' = VT [ l n – ln ] (4) IS IS I1 VOUT' = VT l n and since (5) I2 ln x = 2.3 log10 x Accuracy considerations for a log ratio amplifier are somewhat more complicated than for other amplifiers. The reason is that the transfer function is nonlinear and has two inputs, each of which can vary over a wide dynamic range. The accuracy for any combination of inputs is determined from the total error specification. (6) I1 (7) I2 VOUT (V) R1 + R2 R1 or VOUT = K log (9) R1 K=1 4 (8) R1 + R2 2 1nA 10nA 100nA I1 0 1µA –2 –4 I1 n VT log (10) I2 VOUT = K LOG Fixed value of I2. Q2 – I1 1 VBE I2 = 1µA 6 + VBE I2 = 10nA 8 I2 A2 VOUT A1 I1 VOUT = K LOG I2 I2 I2 = 100µA 4 2 VOUT (V) – + I1 I2 FIGURE 2. Transfer Function with Varying K and I1. (11) I2 1mA I2 = 1µA –8 –10 I1 Q1 10µA 100µA –6 10 I1 K=3 6 also = K=5 10 8 where n = 2.3 VOUT = VOUT' I2 K = the scale factor with units of volts/decade VOUT' = VBE1 – VBE2 VOUT' = n VT log I1 R2 2 1nA 10nA 100nA 1µA 10µA 100µA 1mA I1 0 –2 VOUT –4 R1 –6 –8 –10 VOUT = K LOG I1 I2 K=3 Fixed value of K. FIGURE 3. Transfer Function with Varying I2 and I1. FIGURE 1. Simplified Model of Log Amplifier. ® 5 LOG100 TOTAL ERROR Log conformity is defined as the peak deviation from the best-fit straight line of the VOUT versus log (I1/I2) curve. This is expressed as a percent of peak-to-peak full scale output. Thus, the nonlinearity error expressed in volts over m decades is The total error is the deviation (expressed in mV) of the actual output from the ideal output of VOUT = K log (I1/I2). Thus, VOUT (ACTUAL) = VOUT (IDEAL) ± Total Error. VOUT (NONLIN) = K 2Nm V It represents the sum of all the individual components of error normally associated with the log amp when operated in the current input mode. The worst-case error for any given ratio of I1/I2 is the largest of the two errors when I1 and I2 are considered separately. where N is the log conformity error, in percent. INDIVIDUAL ERROR COMPONENTS The ideal transfer function with current input is Example: VOUT = K Log I1 varies over a range of 10nA to 1µA and I2 varies from 100nA to 10µA. What is the maximum error? I2 (maximum error)(1) I1 (maximum error)(1) 100nA (25mV) 1µA (20mV) 100nA (25mV) 0.1 (30mV) 1 (25mV) 10 (25mV) 1µA (20mV) 0.01 (30mV) 0.1 (25mV) 1 (20mV) 10µA (25mV) 0.001 (30mV) 0.01 (25mV) 0.1 (25mV) I1 (13) I2 The actual transfer function with the major components of error is I1 – IB1 VOUT = K (1 ± ∆K) log ±K 2Nm ± VOS OUT (14) I2 – IB2 Table I shows the maximum errors for each decade combination of I1 and I2. 10nA (30mV) (12) The individual component of error is ∆K = scale factor error (0.3%, typ) IB1 = bias current of A1 (1pA, typ) IB2 = bias current of A2 (1pA, typ) N = log conformity error ( 0.05%, 0.1%, typ) VOS OUT = output offset voltage (1mV, typ) m = number of decades over which N is specified: 0.05% for m = 5, 0.1% for m = 6 NOTE: (1) Maximum errors are in parenthesis. Example: what is the error with K = 3 when TABLE I. I1/I2 and Maximum Errors. I1 = 1µA and I2 = 100nA VOUT = 3(1 ± 0.003) log Since the largest value of I1/I2 is 10 and the smallest is 0.001, K is set at 3V per decade so the output will range from +3V to –9V. The maximum total error occurs when I1 = 10nA and is equal to K x 30mV. This represents a 0.75% of peak-topeak FSO error 3 x 0.030/12 x 100% = 0.75% where the full scale output is 12V (from +3V to –9V). ≈ 3.009 log ERRORS RTO AND RTI As with any transfer function, errors generated by the function itself may be Referred-to-Output (RTO) or Referred-to-Input (RTI). In this respect, log amps have a unique property: 10–6 + 0.015 + 0.001 10–7 (16) = 3.009 (1) + 0.015 + 0.001 (17) = 3.025V (18) Since the ideal output is 3.000V, the error as a percent of reading is % error = 0.025 x 100% = 0.83% 3 (19) For the case of voltage inputs, the actual transfer function is Given some error voltage at the log amp’s output, that error corresponds to a constant percent of the input regardless of the actual input level. V1 Refer to: Yu Jen Wong and William E. Ott, “Function Circuits: Design & Applications”, McGraw-Hill Book, 1976. VOUT = K(1 ± ∆K) log R1 V2 R2 LOG CONFORMITY Log conformity corresponds to linearity when VOUT is plotted versus I1/I2 on a semilog scale. In many applications, log conformity is the most important specification. This is true because bias current errors are negligible (1pA compared to input currents of 1nA and above) and the scale factor and offset errors may be trimmed to zero or removed by system calibration. This leaves log conformity as the major source of error. – IB1 ± – IB2 ± EOS1 R1 EOS2 ±K 2Nm ±VOS OUT R2 (20) FREQUENCY RESPONSE The 3dB frequency response of the LOG100 is a function of the magnitude of the input current levels and of the value of the frequency compensation capacitor. See Typical Performance Curves for details. ® LOG100 10–6 –10–12 ±3(2)(0.0005)5±1mV 10–7 –10–12 (15) 6 A voltage divider may be used to reduce the value of the resistor. When this is done, one must be aware of possible errors caused by the amplifier’s input offset voltage. This is shown in Figure 5. The frequency response curves are shown for constant DC I1 and I2 with a small signal AC current on one of them. The transient response of the LOG100 is different for increasing and decreasing signals. This is due to the fact that a log amp is a nonlinear gain element and has different gains at different levels of input signals. Frequency response decreases as the gain increases. In this case the voltage at pin 14 is not exactly zero, but is equal to the value of the input offset voltage of A1, which ranges from zero to ±5mV. VT must be kept much larger than 5mV in order to make this effect negligible. This concept also applies to pin 1. GENERAL INFORMATION INPUT CURRENT RANGE The stated input range of 1nA to 1mA is the range for specified accuracy. Smaller or larger input currents may be applied with decreased accuracy. Currents larger than 1mA result in increased nonlinearity. The 10mA absolute maximum is a conservative value to limit the power dissipation in the output stage of A1 and the logging transistor. Currents below 1nA will result in increased errors due to the input bias currents of A1 and A2 (1pA typical). These errors may be nulled. See Optional Adjustments section. VT R1 14 VREF A1 IREF R2 FIGURE 5. “T” Network for Reference Current. OPTIONAL ADJUSTMENTS FREQUENCY COMPENSATION Frequency compensation for the LOG100 is obtained by connecting a capacitor between pins 7 and 14. The size of the capacitor is a function of the input currents as shown in the Typical Performance Curves. For any given application, the smallest value of the capacitor which may be used is determined by the maximum value at I2 and the minimum value of I1. Larger values of CC will make the LOG100 more stable, but will reduce the frequency response. The LOG100 will meet its specified accuracy with no user adjustments. If improved performance is desired, the following optional adjustments may be made. INPUT BIAS CURRENT The circuit in Figure 6 may be used to compensate for the input bias currents of A1 and A2. Since the amplifiers have FET inputs with the characteristic bias current doubling every 10°C, this nulling technique is practical only where the temperature is fairly stable. SETTING THE REFERENCE CURRENT When the LOG100 is used as a straight log amplifier I2 is constant and becomes the reference current in the expression I1 VOUT = K log (21) IREF R2 10kΩ –VCC +VCC R1 1kMΩ IREF can be derived from an external current source (such as shown in Figure 4), or it may be derived from a voltage source with one or more resistors. 9 1 7 + I1 LOG100 When a single resistor is used, the value may be quite large when IREF is small. If IREF is 10nA and +15V is used RREF = VOS + – R3 VOUT 14 15V = 1500MΩ. 10nA I2 R1' 1kMΩ 10 6 5 4 – 3 CC –VCC IREF 2N2905 3.6kΩ 2N2905 6V IN834 +VCC FIGURE 6. Bias Current Nulling. RREF +15V R2' 10kΩ –15V IREF OUTPUT OFFSET The output offset may be nulled with the circuit in Figure 7. I1 and I2 are set equal at some convenient value in the range of 100nA to 100µA. R1 is then adjusted for zero output voltage. 6V = RREF FIGURE 4. Temperature-Compensated Current Reference. ® 7 LOG100 –VCC 10kΩ +VCC –VCC –VCC R1 100kΩ 9 2 9 1 7 LOG100 + I1 LOG100 VOUT 14 10 6 I2 5 4 6 – 3 +VCC CC FIGURE 8. Reverse Polarity Protection. I1 = I2 +VCC techniques should be used to avoid damage caused by low energy electrostatic discharge (ESD). FIGURE 7. Output Offset Nulling. LOG RATIO One of the more common uses of log ratio amplifiers is to measure absorbance. A typical application is shown in Figure 9. ADJUSTMENTS OF SCALE FACTOR K The value of K may be changed by increasing or decreasing the voltage divider resistor normally connected to the output, pin 7. To increase K put resistance in series between pin 7 and the appropriate scaling resistor pin (3, 4 or 5). To decrease K place a parallel resistor between pin 2 and either pin 3, 4 or 5. Absorbance of the sample is A = log λ1' (22) λ1 If λ2 = λ1 and D1 and D2 are matched A ∝ K log APPLICATION INFORMATION WIRING PRECAUTIONS In order to prevent frequency instability due to lead inductance of the power supply lines, each power supply should be bypassed. This should be done by connecting a 10µF tantalum capacitor in parallel with a 1000pF ceramic capacitor from the +VCC and –VCC pins to the power supply common. The connection of these capacitors should be as close to the LOG100 as practical. I2 . (23) –VCC I1 9 1 7 + Sample λ1 D1 LOG100 λ1 I2 Light λ 2 Source CAPACITIVE LOADS Stable operation is maintained with capacitive loads of up to 100pF, typically. Higher capacitive loads can be driven if a 22Ω carbon resistor is connected in series with the LOG100’s output. This resistor will, of course, form a voltage divider with other resistive loads. D2 VOUT 14 10 6 5 4 – 3 CC +VCC FIGURE 9. Absorbance Measurement. CIRCUIT PROTECTION The LOG100 can be protected against accidental power supply reversal by putting a diode (1N4001 type) in series with each power supply line as shown in Figure 8. This precaution is necessary only in power systems that momentarily reverse polarity during turn-on or turn-off. If this protection circuit is used, the accuracy of the LOG100 will be degraded slightly by the voltage drops across the diodes as determined by the power supply sensitivity specification. DATA COMPRESSION In many applications the compressive effects of the logarithmic transfer function is useful. For example, a LOG100 preceding an 8-bit analog-to-digital converter can produce equivalent 20-bit converter operation. SELECTING OPTIMUM VALUES OF I2 AND K In straight log applications (as opposed to log ratio), both K and I2 are selected by the designer. In order to minimize errors due to output offset and noise, it is normally best to The LOG100 uses small geometry FET transistors to achieve the low input bias currents. Normal FET handling ® LOG100 I1 8 scale the log amp to use as much of the ±10V output range as possible. Thus, with the range of I1 from I1 MIN to I1 MAX ; For I1 MAX For I1 MIN + 10V = K log I1 MAX /I2 – 10V = K log I1 MIN /I2 QA IIN QB National LM394 (24) D1 (25) D2 Addition of these two equations and solving for I2 shows that its optimum value, I2 OPT, is the geometric mean of I1 MAX and I1 MIN. I2 OPT = I1 MAX x I1 MIN KOPT = log 10 I1 MAX IOUT (26) (27) FIGURE 10. Current Inverter. I2 OPT ANTILOG CONFIGURATION (an implicit technique) Since K is selectable in discrete steps, use the largest value of K available which does not exceed KOPT. –VCC 9 NEGATIVE INPUT CURRENTS The LOG100 will function only with positive input currents (conventional current flow into pins 1 and 14). Some current sources (such as photomultiplier tubes) provide negative input currents. In such situations, the circuit in Figure 10 may be used.(1) 1 7 + IREF LOG100 VOUT 14 – 10 6 5 4 3 R VOLTAGE INPUTS The LOG100 gives the best performance with current inputs. Voltage inputs may be handled directly with series resistors, but the dynamic input range is limited to approximately three decades of input voltage by voltage noise and offsets. The transfer function of equation (20) applies to this configuration. +VCC CC = 0.01µF VIN VOUT = IREF R Antilog – VIN K K = 1 when VIN connected to pin 3. K = 3 when VIN connected to pin 4. K = 5 when VIN connected to pin 5. FIGURE 11. Connections for Antilog Function. NOTE: (1) More detailed information may be found in “Properly Designed Log Amplifiers Process Bipolar Input Signals” by Larry McDonald, EDN, 5 Oct. 80, pp 99–102. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 9 LOG100 PACKAGE OPTION ADDENDUM www.ti.com 16-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty LOG100JP NRND CDIP BB JDE 14 TBD Call TI Call TI LOG100JP-2 NRND CDIP BB JDE 14 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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