Oxford OX12PCI840 Integrated parallel port and pci interface Datasheet

OX12PCI840
Integrated Parallel Port
and PCI interface
FEATURE
•
•
•
IEEE1284 SPP/EPP/ECP parallel port
Single function target PCI controller, fully PCI 2.2 and
PCI Power Management 1.0 compliant
2 multi-purpose IO pins which can be configured as
interrupt input pins
•
•
•
Can be reconfigured using optional non-volatile
configuration memory (EEPROM)
5.0V operation
100 pin PQFP package
DESCRIPTION
The OX12PCI840 is a single chip solution for PCI-based
parallel expansion add-in cards. It is a single function PCI
device.
version 1.0 of PCI Power Management Specification. For
full flexibility, all the default register values can be
overwritten using an optional MicrowireTM serial EEPROM.
For legacy applications the PCI resources are arranged so
that the parallel port can be located at standard I/O
addresses.
The OX12PCI840 provides an IEEE1284 EPP/ECP parallel
port which fully supports the existing Centronics interface.
The efficient 32-bit, 33MHz target-only PCI interface is
compliant with version 2.2 of the PCI Bus Specification and
Oxford Semiconductor Ltd.
External—Free Release
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900
Fax: +44(0)1235 821141
© Oxford Semiconductor 2005
OX12PCI840 DS-0021 – Jun 2005
Part No. OX12PCI840-PQC-A
OXFORD SEMICONDUCTOR LTD.
OX12PCI840
CONTENTS
1
PIN INFORMATION ............................................................................................................................... 4
2
PIN DESCRIPTIONS.............................................................................................................................. 5
3
CONFIGURATION & OPERATION ....................................................................................................... 8
4
PCI TARGET CONTROLLER................................................................................................................ 9
4.1
4.2
4.2.1
4.3
4.3.1
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.5
4.6
4.6.1
5
OPERATION ....................................................................................................................................................................... 9
CONFIGURATION SPACE ................................................................................................................................................. 9
PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................ 10
ACCESSING LOGICAL FUNCTIONS .............................................................................................................................. 11
PCI ACCESS TO PARALLEL PORT ............................................................................................................................ 11
ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 12
LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 12
MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 13
LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): .................................................................. 13
LOCAL BUS TIMING PARAMETER/BAR SIZING REGISTER 2 ‘LT2’ (OFFSET 0X0C): ............................................ 14
GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X10)................................................ 15
PCI INTERRUPTS............................................................................................................................................................. 16
POWER MANAGEMENT .................................................................................................................................................. 17
POWER MANAGEMENT USING MIO.......................................................................................................................... 17
BI-DIRECTIONAL PARALLEL PORT ................................................................................................. 18
5.1
OPERATION AND MODE SELECTION ........................................................................................................................... 18
5.1.1
SPP MODE ................................................................................................................................................................... 18
5.1.2
PS2 MODE.................................................................................................................................................................... 18
5.1.3
EPP MODE ................................................................................................................................................................... 18
5.1.4
ECP MODE ................................................................................................................................................................... 18
5.2
PARALLEL PORT INTERRUPT ....................................................................................................................................... 18
5.3
REGISTER DESCRIPTION............................................................................................................................................... 19
5.3.1
PARALLEL PORT DATA REGISTER ‘PDR’ ................................................................................................................. 19
5.3.2
ECP FIFO ADDRESS / RLE ......................................................................................................................................... 19
5.3.3
DEVICE STATUS REGISTER ‘DSR’ ............................................................................................................................ 19
5.3.4
DEVICE CONTROL REGISTER ‘DCR’......................................................................................................................... 20
5.3.5
EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................. 20
5.3.6
EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................. 20
5.3.7
ECP DATA FIFO ........................................................................................................................................................... 20
5.3.8
TEST FIFO .................................................................................................................................................................... 20
5.3.9
CONFIGURATION A REGISTER ................................................................................................................................. 20
5.3.10
CONFIGURATION B REGISTER ................................................................................................................................. 21
5.3.11
EXTENDED CONTROL REGISTER ‘ECR’................................................................................................................... 21
6
SERIAL EEPROM................................................................................................................................ 22
7
OPERATING CONDITIONS................................................................................................................. 26
8
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 26
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
8.1
SPECIFICATION ............................................................................................................................................................... 22
EEPROM DATA ORGANISATION ................................................................................................................................... 22
ZONE0: HEADER ......................................................................................................................................................... 22
ZONE1: LOCAL CONFIGURATION REGISTERS........................................................................................................ 23
ZONE2: IDENTIFICATION REGISTERS ...................................................................................................................... 23
ZONE3: PCI CONFIGURATION REGISTERS ............................................................................................................. 23
ZONE4: FUNCTION ACCESS ...................................................................................................................................... 25
NON-PCI I/O BUFFERS.................................................................................................................................................... 26
DS-0021 Jun 05
Page 2
OXFORD SEMICONDUCTOR LTD.
8.2
9
OX12PCI840
PCI I/O BUFFERS ............................................................................................................................................................. 27
AC ELECTRICAL CHARACTERISTICS ............................................................................................. 28
9.1
PCI BUS ............................................................................................................................................................................ 28
10
TIMING WAVEFORMS..................................................................................................................... 29
11
PACKAGE DETAILS ....................................................................................................................... 30
12
ORDERING INFORMATION ............................................................................................................ 31
13
NOTES ............................................................................................................................................. 32
14
CONTACT DETAILS........................................................................................................................ 33
REVISION HISTORY
REV
Jun 2005
DATE
14/6/2005
DS-0021 Jun 05
REASON FOR CHANGE / SUMMARY OF CHANGE
Revision for additional green order code for 100-pin PQFP package
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
1
PIN INFORMATION
75
70
65
60
PD7
55
MIO0
PD6
PD5
GND ac
PD4
VDD ac
PD3
PD2
PD1
GND ac
PE
PD0
SLCT
BUSY
GND dc
ERR#
VDD dc
PD_EN
NC
ACK#
GND ac
INIT#
SLIN#
STB
80
51
81
50
85
45
90
40
95
35
100
31
DS-0021 Jun 05
VDD ac
GND ac
AD13
AD14
30
AD15
PAR
Z_CBE1
Z_SERR
Z_PERR
GND ac
25
Z_STOP
Z_TRDY
Z_DEVSEL
Z_IRDY
20
VDD dc
GND dc
Z_FRAME
AD16
Z_CBE2
15
AD17
AD18
AD19
VDD ac
GND ac
10
AD20
AD22
GND ac
5
AD23
IDSEL
1
AD21
EE_SK
MIO1
Z_INTA
Z_RESET
GND dc
PCI_CLK
VDD dc
Z_PME
AD31
AD30
AD29
GND ac
AD28
AD27
AD26
GND ac
VDD ac
AD25
AD24
Z_CBE3
AFD#
TEST
EE_CS
EE_DI
EE_DO
100 pin QFP
Page 4
AD0
AD1
GND ac
AD2
AD3
VDD dc
GND dc
AD4
AD5
GND ac
VDD ac
AD6
AD7
Z_CBE0
AD8
GND ac
AD9
AD10
AD11
AD12
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
2
PIN DESCRIPTIONS
Pin Numbers
PCI interface
89,90,91,93,94,95,98,99,2,4,5,6,9,
10,11,12,26,27,28,31,32,33,34,36,
38,39,42,43,46,47,49,50
100,13,25,37
86
14
19
17
18
21
24
23
22
1
84
83
88
DS-0021 Jun 05
Dir1
Name
Description
P_I/O
AD[31:0]
Multiplexed PCI Address/Data bus
P_I
P_I
P_I
P_O
P_I
P_O
P_O
P_I/O
P_O
P_I/O
P_I
P_I
P_OD
P_OD
C/BE[3:0]#
CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA#
PME#
PCI Command/Byte enable
PCI system clock
Cycle Frame
Device Select
Initiator ready
Target ready
Target Stop request
Parity
System error
Parity error
Initialisation device select
PCI system reset
PCI interrupt
Power management event
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
Pin Numbers
Dir1
Name
Description
I
ACK#
Acknowledge (SPP mode). ACK# is asserted (low) by the
peripheral to indicate that a successful data transfer has
taken place.
I
I
I
INTR#
PE
BUSY
Identical function to ACK# (EPP mode).
Paper Empty. Activated by printer when it runs out of paper.
Busy (SPP mode). BUSY is asserted (high) by the peripheral
when it is not ready to accept data
I
WAIT#
OD
SLIN#
Wait (EPP mode). Handshake signal for interlocked IEEE
1284 compliant EPP cycles.
Select (SPP mode). Asserted by host to select the peripheral
O
ADDRSTB#
65
68
74
I
I
OD
SLCT
ERR#
INIT#
Address strobe (EPP mode) provides address read and write
strobe
Peripheral selected. Asserted by peripheral when selected.
Error. Held low by the peripheral during an error condition.
Initialise (SPP mode). Commands the peripheral to initialise.
75
O
OD
INIT#
AFD#
Initialise (EPP mode). Identical function to SPP mode.
Auto Feed (SPP mode, open-drain)
76
O
OD
DATASTB#
STB#
Data strobe (EPP mode) provides data read and write strobe
Strobe (SPP mode). Used by peripheral to latch data
currently available on PD[7:0]
O
WRITE#
I/O
PD[7:0]
Write (EPP mode). Indicates a write cycle when low and a
read cycle when high
Parallel data bus
Parallel port
71
63
64
73
52,53,54,57,
58,59,60,62
DS-0021 Jun 05
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
Pin Numbers
Dir1
Name
Description
MIO[1:0]
Multi-purpose I/O pins. Can drive high or low, or assert a PCI
interrupt
O
O
IU
EE_CK
EE_CS
EE_DI
79
Miscellaneous pins
77
Power and ground2
8,30,40,56,97
16,45,67,87
O
EE_DO
EEPROM clock
EEPROM active-high Chip Select
EEPROM data in. When the serial EEPROM is connected,
this pin should be pulled up using 1-10k resistor. When the
EEPROM is not used the internal pull-up is sufficient.
EEPROM data out.
I
TEST
Test Pin : should be held low at all times
V
V
AC VDD
DC VDD
3,7,20,29,35,41,48,55,61,72,92,96
15,44,66,85
G
G
AC GND
DC GND
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
Supplies GND to output buffers in switching (AC) state
Ground (0 volts). Supplies GND to core logic, input buffers
and output buffers in steady state
Multi-purpose & External interrupt pins
82, 51
I/O
EEPROM pins
81
78
80
Table 1: Pin Descriptions
Note 1: Direction key:
I
ID
O
I/O
OD
NC
Z
Input
Input with internal pull-down
Output
Bi-directional
Open drain
No connect
High impedance
P_I
P_O
P_I/O
P_OD
PCI input
PCI output
PCI bi-directional
PCI open drain
G
V
Ground
5.0V power
Note 2: Power & Ground
There are two GND and two VDD rails internally. One set of rails supply power and ground to output buffers while in switching
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail).
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF
radiation from the chip. Further precaution is taken by segmenting the GND and VDD AC rails to isolate the PCI and Local Bus
pins.
DS-0021 Jun 05
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OXFORD SEMICONDUCTOR LTD.
3
OX12PCI840
CONFIGURATION & OPERATION
The OX12PCI840 is a single function, target-only PCI
device, compliant with the PCI Local Bus Specification,
Revision 2.2 and PCI Power Management Specification,
Revision 1.0.
The OX12PCI840 is configured by system start-up
software during the bootstrap process that follows bus
reset. The system scans the bus and reads the vendor and
device identification codes from any devices it finds. It then
loads device-driver software according to this information
and configures the I/O, memory and interrupt resources.
Device drivers can then access the functions at the
assigned addresses in the usual fashion, with the improved
data throughput provided by PCI.
DS-0021 Jun 05
There are a set of Local configuration registers that can be
used to enable signals and interrupts, and configure
timings. These can be set up by drivers or from the
EEPROM.
All registers default after reset to suitable values for typical
applications. However, all identification, control and timing
registers can be redefined using an optional serial
EEPROM. As an additional enhancement, the EEPROM
can be used to program the parallel port, allowing preconfiguration, without requiring driver changes.
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
4
4.1
PCI TARGET CONTROLLER
Operation
The OX12PCI840 responds to the following PCI
transactions:•
•
•
•
Configuration access: The OX12PCI840 responds to
type 0 configuration reads and writes if the IDSEL
signal is asserted and the bus address is selecting the
configuration registers for function 0. The device will
respond to the configuration transaction by asserting
DEVSEL#. Data transfer then follows. Any other
configuration transaction will be ignored by the
OX12PCI840.
IO reads/writes: The address is compared with the
addresses reserved in the I/O Base Address Registers
(BARs). If the address falls within one of the assigned
ranges, the device will respond to the IO transaction
by asserting DEVSEL#. Data transfer follows this
address phase. Only byte accesses are possible to
the function BARs (excluding the local configuration
registers for which WORD, DWORD access is
supported). For IO accesses to these regions, the
controller compares AD[1:0] with the byte-enable
signals as defined in the PCI specification. The access
is always completed; however if the correct BE signal
is not present the transaction will have no effect.
Memory reads/writes: These are treated in the same
way as I/O transactions, except that the memory
ranges are used. Memory access to single-byte
regions is always expanded to DWORDs in the
OX12PCI840. In other words, OX12PCI840 reserves
a DWORD per byte in single-byte regions. The device
allows the user to define the active byte lane using
LCC[4:3] so that in Big-Endian systems the hardware
can swap the byte lane automatically. For Memory
mapped access in single-byte regions, the
OX12PCI840 compares the asserted byte-enable with
the selected byte-lane in LCC[4:3] and completes the
operation if a match occurs, otherwise the access will
complete normally on the PCI bus, but it will have no
effect on either the parallel port or the local bus
controller.
All other cycles (64-bit, special cycles, reserved
encoding etc.) are ignored.
DS-0021 Jun 05
The OX12PCI840 will complete all transactions as
disconnect-with-data, i.e. the device will assert the STOP#
signal alongside TRDY#, to ensure that the Bus Master
does not continue with a burst access. The exception to
this is Retry, which will be signalled in response to any
access while the OX12PCI840 is reading from the serial
EEPROM.
The OX12PCI840 performs medium-speed address
decoding as defined by the PCI specification. It asserts the
DEVSEL# bus signal two clocks after FRAME# is first
sampled low on all bus transaction frames which address
the chip. Fast back-to-back transactions are supported by
the OX12PCI840 as a target, so a bus master can perform
faster sequences of write transactions to the parallel port
when an inter-frame turn-around cycle is not required.
The device supports any combination of byte-enables to
the PCI Configuration Registers and the Local
Configuration registers (see Base Address 2 and 3). If a
byte-enable is not asserted, that byte is unaffected by a
write operation and undefined data is returned upon a read.
The OX12PCI840 performs parity generation and checking
on all PCI bus transactions as defined by the standard. If a
parity error occurs during the PCI bus address phase, the
device will report the error in the standard way by asserting
the SERR# bus signal. However if that address/command
combination is decoded as a valid access, it will still
complete the transaction as though the parity check was
correct.
The OX12PCI840 does not support any kind of caching or
data buffering, other than that in the parallel port interface
itself.
4.2
Configuration space
The OX12PCI840 is a single function device, with one
configuration space. All required fields in the standard
header are implemented, plus the Power Management
Extended Capability register set. The format of the
configuration space is shown in Table 2 overleaf.
In general, writes to any registers that are not implemented
are ignored, and all reads from unimplemented registers
return 0.
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
4.2.1
PCI Configuration Space Register map
Configuration Register Description
31
16
15
Device ID
Status
0
Vendor ID
Command
Class Code
Revision ID
Header Type
Reserved
Reserved
Base Address Register 0 (BAR0) - Function in I/O space
Base Address Register 1 (BAR 1) - Function in I/O space
Base Address Register 2 (BAR 2) – Local Configuration Registers in IO space
Base Address Register 3 (BAR3) – Local Configuration Registers in Memory space
Base Address Register 4 (BAR4) – Function in Memory Space
Reserved
Reserved
Subsystem ID
Subsystem Vendor ID
Reserved
Reserved
Cap_Ptr
Reserved
Reserved
Reserved
Interrupt Pin
Interrupt Line
Power Management Capabilities (PMC)
Next Ptr
Cap_ID
Reserved
Reserved
PMC Control/Status Register (PMCSR)
BIST1
Offset
Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
Table 2: PCI Configuration space
Register name
Reset value
Vendor ID
Device ID
Command
Status
Revision ID
Class code
Header type
BAR 0
BAR 1
BAR 2
BAR 3
BAR 4
Subsystem VID
0x1415
0x8403
0x0000
0x0290
0x00
0x070103
0x00
0x00000001
0x00000001
0x00000001
0x00000000
Reserved
0x1415
Subsystem ID
Cap ptr.
Interrupt line
Interrupt pin
Cap ID
Next ptr.
PM capabilities
PMC control/ status register
0x0001
0x40
0x00
0x01
0x01
0x00
0x6C01
0x0000
Program read/write
EEPROM
PCI
W
R
W
R
R/W
W(bit 4)
R/W
R
W
R
R
R/W
R/W
R/W
R/W
R/W
W
R
W
W
W
-
R
R
R/W
R
R
R
R
R/W
Table 3: PCI configuration space default values
DS-0021 Jun 05
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
4.3
Accessing logical functions
Access to the parallel port is achieved via standard I/O and memory mapping, at addresses defined by the Base Address
Registers (BARs) in configuration space. The BARs are configured by the system to allocate blocks of I/O and memory space to
the logical function, according to the size required by the function. The addresses allocated can then be used to access the
function. The mapping of these BARs is shown in Table 4.
BAR
0
1
2
3
4
5
Mapping
Parallel port base registers (I/O mapped)
Parallel port extended registers (I/O mapped)
Local configuration registers (I/O mapped
Local configuration registers (memory mapped)
Unused
Unused
Table 4: Base Address Register definition
4.3.1
PCI access to parallel port
Access to the port works with two I/O BARs corresponding
to the two sets of registers defined to operate an IEEE1284
ECP/EPP and bi-directional Parallel Port.
The user can change the I/O space block size of BAR0 or
BAR by over-writing the default values using the serial
EEPROM (see section 4.4).
DS-0021 Jun 05
Legacy parallel ports expect the upper register set to be
mapped 0x400 above the base block, therefore if the BARs
are fixed with this relationship, generic parallel port drivers
can be used to operate the device in all modes.
Example: BAR0 = 0x00000379 (8 bytes at address 0x378)
BAR1 = 0x00000779 (8 bytes at address 0x778)
If this relationship is not used, custom drivers will be
needed.
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
4.4
Accessing Local configuration registers
The local configuration registers are a set of device specific registers which can always be accessed. They are mapped to the
I/O and memory addresses set up in BAR2 and BAR3, with the offsets defined for each register. I/O or memory accesses can be
byte, word or dword accessed, however on little-endian systems such as Intel 80x86 the byte order will be reversed.
4.4.1
Local Configuration and Control register ‘LCC’ (Offset 0x00)
This register defines control of ancillary functions such as Power Management, endian selection and the serial EEPROM. The
individual bits are described below.
Bits
2:0
4:3
7:5
10:8
22:11
23
24
25
26
27
28
29
30
31
Description
Reserved
Endian Byte-Lane Select for memory access to parallel port
00 = Select Data[7:0]
10 = Select Data[23:16]
01 = Select Data[15:8]
11 = Select Data[31:24]
Memory access to OX12PCI840 is always DWORD aligned. When
accessing the parallel port, this option selects the active byte lane. As
both PCI and PC architectures are little endian, the default value will be
used by systems, however, some non-PC architectures may need to
select the byte lane.
Power-down filter time. These bits define a value of an internal filter time
for power-down interrupt request in power management circuitry in
Function0. Once Function0 is ready to go into power down mode,
OX12PCI840 will wait for the specified filter time and if Function0 is still
in power-down request mode, it can assert a PCI interrupt (see section
4.6).
000 = power-down request disabled
010 = 129 seconds
001 = 4 seconds
011 = 518 seconds
1XX = Immediate
Reserved: Power management test bits. The device driver must write
zero to these bits
Reserved.
Parallel port Input (glitch) filters. Enabled when ‘1’
EEPROM Clock. For PCI read or write to the EEPROM , toggle this bit to
generate an EEPROM clock (EE_CK pin).
EEPROM Chip Select. When 1 the EEPROM chip-select pin EE_CS is
activated (high). When 0 EE_CS is de-active (low).
EEPROM Data Out. For writes to the EEPROM, this output bit is the
input-data of the EEPROM. This bit is output on EE_DO and clocked into
the EEPROM by EE_CK.
EEPROM Data In. For reads from the EEPROM, this input bit is the
output-data of the EEPROM connected to EE_DI pin.
EEPROM Valid. A 1 indicates that a valid EEPROM program is present
Reload configuration from EEPROM. Writing a 1 to this bit re-loads the
configuration from EEPROM. This bit is self-clearing after EEPROM read
Reserved
Reserved
DS-0021 Jun 05
Read/Write
Reset
EEPROM
PCI
W
RW
000
00
W
RW
000
-
R
000
W
-
R
RW
RW
0000h
0
0
-
RW
0
-
RW
0
-
R
X
-
R
RW
X
0
-
R
R
0
0
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
4.4.2
Multi-purpose I/O Configuration register ‘MIC’ (Offset 0x04)
This register configures the operation of the multi-purpose I/O pins ‘MIO[1:0] as follows.
Bits
Description
Read/Write
EEPROM
Reset
1:0
MIO0 Configuration Register
00 -> MIO0 is a non-inverting input pin
01 -> MIO0 is an inverting input pin
10 -> MIO0 is an output pin driving ‘0’
11 -> MIO0 is an output pin driving ‘1’
W
PCI
RW
3:2
MIO1 Configuration Register
00 -> MIO1 is a non-inverting input pin
01 -> MIO1 is an inverting input pin
10 -> MIO1 is an output pin driving ‘0’
11 -> MIO1 is an output pin driving ‘1’
W
RW
00
4
MIO0_PME Enable. A value of ‘1’ enables MIO0 pin to set the
PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO0 from setting the PME_Status bit.
MIO1_PME Enable. A value of ‘1’ enables MIO1 pin to set the
PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO1 from setting the PME_Status bit.
MIO0 Power Down Request: A ‘1’ enables MIO0 to control the power
down request filter.
MIO1 Power Down Request: A ‘1’ enables MIO1 to control the power
down request filter.
Reserved
W
RW
0
W
RW
0
W
RW
0
W
RW
0
-
R
00
5
6
7
31:8
4.4.3
00
Local Bus Timing Parameter register 1 ‘LT1’ (Offset 0x08):
The Local Bus Timing Parameter registers (LT1 and LT2) define the operation and timing parameters used by the internal local
bus (that connects to the parallel port). It is envisaged that these should not need to be changed by the user. The timing
parameters are programmed in 4-bit registers to define the assertion/de-assertion of the Local Bus control signals. The values
programmed in these registers defines the number of PCI clock cycles after a Reference Cycle when the events occur, where
the reference Cycle is defined as two clock cycles after the master asserts the IRDY# signal. The timings refer to I/O or Memory
mapped accesses.
Bits
Description
Read/Write
EEPROM
3:0
7:4
11:8
15:12
19:16
23:20
27:24
31:28
Note 1:
Read Cycle start
Read Cycle end
Write Cycle start
Write Cycle end
Read Assertion
Read De-assertion
Write Assertion
Write De-assertion
W
W
W
W
W
W
W
W
Reset
PCI
RW
RW
RW
RW
RW
RW
RW
RW
0h
2h
0h
2h
1h
2h
1h
2h
Only values in the range of 0h to Ah (0-10 decimal) are valid. Other values are reserved. See notes in the following page.
DS-0021 Jun 05
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OX12PCI840
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4.4.4
Bits
Local Bus Timing Parameter/Bar sizing register 2 ‘LT2’ (Offset 0x0C):
Description
Read/Write
EEPROM
3:0
7:4
11:8
15:12
19:16
22:20
23
26:24
28::27
29
31:30
Reserved: 0h must be written to this location
Reserved: Fh must be written to this location
Reserved: 2h must be written to this location
Reserved: 0h must be written to this location
Reserved.
IO Space Block Size of BAR0
000 = Reserved
100 = 32 Bytes
001 = 4 Bytes
101 = 64 Bytes
010 = 8 Bytes
110 = 128 Bytes
011 = 16 Bytes
111 = 256 Bytes
Reserved
IO Space Block Size of BAR1
000 = Reserved
100 = 32 Bytes
001 = 4 Bytes
101 = 64 Bytes
010 = 8 Bytes
110 = 128 Bytes
011 = 16 Bytes
111 = 256 Bytes
Reserved
Reserved:0 must be written to this location
Reserved:00 must be written to this location
DS-0021 Jun 05
Reset
W
W
W
W
W
PCI
RW
RW
RW
RW
R
R
0h
Fh
2h
0h
0h
‘010’
W
R
R
0h
‘001’
W
R
RW
RW
000
0
00
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
4.4.5
Bits
Global Interrupt Status and Control Register ‘GIS’ (Offset 0x10)
Description
Read/Write
EEPROM
1:0
2
3
17-4
18
Reserved
MIO0 This bit reflects the state of the internal MIO[0]. The internal MIO[0]
reflects the non-inverted or inverted state of MIO0 pin.
MIO1 This bit reflects the state of the internal MIO[0]. The internal MIO[0]
reflects the non-inverted or inverted state of MIO0 pin.
Reserved
MIO0 INTA enable
When set (1) allows MIO0 to assert a PCI interrupt on the INTA line. State of
MIO0 that causes an interrupt is dependant upon the polarity set by MIC(1:0)
Reset
-
PCI
R
R
-
R
X
W
R
RW
0
0
0x0h
X
19
MIO1 INTA enable
When set (1) allows MIO1 to assert a PCI interrupt on the INTA line. State of
MIO1 that causes an interrupt is dependant upon the polarity set by MIC(3:2)
W
RW
0
20
-
R
X
W
RW
0
22
23
Power-down Interrupt This is a sticky bit. When set, it indicates a power-down
request issued and would normally have asserted a PCI interrupt if bit 21 was
set (see section 7.9). Reading this bit clears it.
Power-down interrupt enable. When ‘1’ a power down request is allowed to
generate an interrupt.
Parallel port interrupt status
Parallel port interrupt enable
W
R
RW
0
1
31:24
Reserved
-
R
000h
21
DS-0021 Jun 05
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
4.5
PCI Interrupts
Interrupts in PCI systems are level-sensitive and can be
shared. There are three sources of interrupt in the
OX12PCI840, two from Multi-Purpose IO pins (MIO1 to
MIO0) and one from the parallel port.
All interrupts are routed to the PCI interrupt pin INTA#. The
default routing asserts Function0 interrupts on INTA#. This
default routing may be modified (to disable interrupts) by
writing to the Interrupt Pin field in the configuration
registers using the serial EEPROM facility. The Interrupt
Pin field is normally considered a hard-wired read-only
value in PCI. It indicates to system software which PCI
interrupt pin (if any) is used by a function. The interrupt pin
may only be modified using the serial EEPROM facility,
and card developers must not set any value which violates
the PCI specification. Note that OX12PCI840 only has one
PCI interrupt pin - INTA#. If in doubt, the default routings
should be used. Table 5 relates the Interrupt Pin field to the
device pin used.
Interrupt Pin
0
1
2 to 255
Device Pin used
None
INTA#
Reserved
Table 5: ‘Interrupt pin’ definition
During the system initialisation process and PCI device
configuration, system-specific software reads the interrupt
pin field to determine which (if any) interrupt pin is used by
the function. It programmes the system interrupt router to
logically connect this PCI interrupt pin to a system-specific
interrupt vector (IRQ). It then writes this routing information
to the Interrupt Line field in the function’s PCI configuration
space. Device driver software must then hook the interrupt
using the information in the Interrupt Line field.
Interrupt status for all sources of interrupt is available using
the GIS register in the Local Configuration Register set,
which can be accessed using I/O or Memory accesses.
All interrupts can be enabled / disabled individually using
the GIS register set in the Local configuration registers.
When an MIO pin is enabled, an external device can assert
a PCI interrupt by driving that pin. The sense of the MIO
external interrupt pins (active-high or active-low) is defined
in the MIC register. The parallel port can also assert an
interrupt.
DS-0021 Jun 05
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OXFORD SEMICONDUCTOR LTD.
4.6
Power Management
The OX12PCI840 is compliant with PCI Power
Management Specification Revision 1.0. The function
implements its own set of Power Management registers
and supports the power states D0, D2 and D3. Power
management is accomplished by power-down and powerup requests, asserted via interrupts and the PME# pin
respectively. The PME# pin is de-asserted when the sticky
PME_Status bit is cleared.
Power-down request is not defined by Power Management
1.0. It is a device-specific feature and requires a bespoke
device driver implementation. The device driver can either
implement the power-down itself or use a special interrupt
and power-down features offered by the device to
determine when the device is ready for power-down.
The PME# pin can, in certain cases, activate the PME#
signal when power is removed from the device, which will
cause the PC to wake up from Low-power state D3(cold).
To ensure full cross-compatibility with system board
implementations, use of an isolator FET is recommended.
If Power Management capabilities are not required, the
PME# pin can be treated as no-connect.
4.6.1
Power Management using MIO
The power-down request for the Parallel port
is
application-dependent. Provided that the necessary
enables have been set in the local registers, the multipurpose I/O pins MIO(1:0) can be used to generate a
DS-0021 Jun 05
powerdown request. The MIO state that governs
powerdown is the inverse of the MIO state that asserts the
INTA line (if that option were to be enabled). This means
that when the external device is not interrupting it will begin
the powerdown cycle. For greater flexibility in the
generation of the power down request,, a powerdown filter
is also available to ensure that the relevant MIO pins
remain stable for a selectable period before a powerdown
request is issued.
Function0 implements the PCI Power Management powerstates D0, D2 and D3. Whenever the device driver
changes the power-state to state D2 or D3, Function0
takes the following actions:•
•
The PCI interrupt for Function0 is disabled.
Access to I/O or Memory BARs of Function0 is
disabled.
However, access to the configuration space is still enabled.
The device driver can optionally assert/de-assert any of its
selected (design dependent) MIO pins to switch off VCC,
disable other external clocks, or activate shut-down modes
to any external devices.
Function0 can issue a wake up request by using the MIO
pins. When MIC[7] or MIC[6] is set, rising or falling edge of
the relevant MIO pin will cause Function0 to issue a wake
up request by setting PME_Status = (PMCSR[15]), if it is
enabled by PMCSR[8] of Function0. PME_Status is a
sticky bit which will be cleared by writing a ‘1’ to it. After a
wake up event is signalled, the device driver is expected to
return the function to the D0 power-state.
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OXFORD SEMICONDUCTOR LTD.
5
5.1
BI-DIRECTIONAL PARALLEL PORT
Operation and Mode selection
The OX12PCI840 offers a compact, low power, IEEE-1284
compliant host-interface parallel port, designed to interface
to many peripherals such as printers, scanners and
external drives. It supports compatibility modes, SPP,
NIBBLE, PS2, EPP and ECP modes. The register set is
compatible with the Microsoft® register definition. The
system can access the parallel port via two blocks of I/O
space; BAR0 (8 bytes) contains the address of the basic
parallel port registers, BAR1 (4 bytes) contains the address
of the upper registers. These are referred to as the ‘lower
block’ and ‘upper block’ in this section. If the upper block is
located at an address 0x400 above the lower block,
generic PC device drivers can be used to configure the
port, as the addressable registers of legacy parallel ports
always have this relationship. If not, a custom driver will be
needed.
5.1.1
SPP mode
SPP (output-only) is the standard implementation of a
simple parallel port. In this mode, the PD lines always drive
the value in the PDR register. All transfers are done under
software control. Input must be performed in nibble mode.
Generic device driver-software may use the address in I/O
space encoded in BAR0 of function 1 to access the parallel
port. The default configuration allocates 8 bytes to BAR0 in
I/O space.
5.1.2
PS2 mode
This mode is also referred to as bi-directional or compatible
parallel port. In this mode, directional control of the PD
lines is possible by setting & clearing DCR[5]. Otherwise
operation is similar to SPP mode.
5.1.3
EPP mode
To use the Enhanced Parallel Port ‘EPP’ the mode bits
(ECR[7:5]) must be set to ‘100’. The EPP address and data
port registers are compatible with the IEEE 1284 definition.
A write or read to one of the EPP port registers is passed
through the parallel port to access the external peripheral.
In EPP mode, the STB#, INIT#, AFD# AND SLIN# pins
change from open-drain outputs to active push-pull (totem
pole) drivers (as required by IEEE 1284) and the pins
ACK#, AFD#, BUSY, SLIN# and STB# are redefined as
DS-0021 Jun 05
INTR#, DATASTB#, WAIT#, ADDRSTB# and WRITE#
respectively.
An EPP port access begins with the host reading or writing
to one of the EPP port registers. The device automatically
buffers the data between the I/O registers and the parallel
port depending on whether it is a read or a write cycle.
When the peripheral is ready to complete the transfer it
takes the WAIT# status line high. This allows the host to
complete the EPP cycle.
If a faulty or disconnected peripheral failed to respond to an
EPP cycle the host would never see a rising edge on
WAIT#, and subsequently lock up. A built-in time-out facility
is provided in order to prevent this from happening. It uses
an internal timer which aborts the EPP cycle and sets a
flag in the PSR register to indicate the condition. When the
parallel port is not in EPP mode the timer is switched off to
reduce current consumption. The host time-out period is
10μs as specified with the IEEE-1284 specification.
The register set is compatible with the Microsoft® register
definition. Assuming that the upper block is located 400h
above the lower block, the registers are found at offset
000-007h and 400-402h.
5.1.4
ECP mode
The Extended Capabilities Port ‘ECP’ mode is entered
when ECR[7:5] is set to ‘011’. ECP mode is compatible
with Microsoft® register definition of ECP, and IEEE-1284
bus protocol and timing. This implementation of the ECP
port supports the optional decompression of received
compressed data, but does not compress transmit data.
Assuming that the upper block is located 400h above the
lower block, the registers are found at offset 000-007h and
400-402h.
5.2
Parallel port interrupt
The parallel port interrupt is asserted on INTA#. It is
enabled by setting DCR[4]. When DCR[4] is set, an
interrupt is asserted on the rising edge of the ACK#
(INTR#) pin and held until the status register is read, which
resets the INT# status bit (DSR[2]).
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5.3
Register Description
The parallel port registers are described below. (NB it is assumed that the upper block is placed 400h above the lower block).
Register
Name
Address
Offset
R/W
PDR
ecpAFifo
DSR
000h
000h
001h
R/W
R/W
R
(Other modes)
001h
002h
003h
004h
005h
006h
007h
400h
400h
400h
401h
402h
403h
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
-
(EPP mode)
DCR
EPPA 1
EPPD1 1
EPPD2 1
EPPD3 1
EPPD4 1
EcpDFifo
TFifo
CnfgA
CnfgB
ECR
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SPP (Compatibility Mode) Registers
Parallel Port Data Register
ECP FIFO : Address / RLE
nBUSY
ACK#
PE
SLCT
ERR#
INT#
nBUSY
0
ACK#
0
0
int
Mode[2:0]
PE
DIR
SLCT
ERR#
INT#
INT_EN nSLIN#
INIT#
EPP Address Register
EPP Data 1 Register
EPP Data 2 Register
EPP Data 3 Register
EPP Data 4 Register
ECP Data FIFO
Test FIFO
Configuration A Register – always 90h
‘000000’
Must write ‘00001’
Reserved
Bit 1
Bit 0
1
Timeout
1
nAFD#
1
nSTB#
Table 6: Parallel port register set
Note 1 : These registers are only available in EPP mode.
Note 2 : Prefix ‘n’ denotes that a signal is inverted at the connector. Suffix ‘#’ denotes active-low signalling
The reset state of PDR, EPPA and EPPD1-4 is not determinable (i.e. 0xXX). The reset value of DSR is ‘XXXXX111’. DCR and
ECR are reset to ‘0000XXXX’ and ‘00000001’ respectively.
5.3.1
Parallel port data register ‘PDR’
PDR is located at offset 000h in the lower block. It is the
standard parallel port data register. Writing to this register
in mode 000 will drive data onto the parallel port data lines.
In all other modes the drivers may be tri-stated by setting
the direction bit in the DCR. Reads from this register return
the value on the data lines.
5.3.2
ECP FIFO Address / RLE
A data byte written to this address will be interpreted as an
address if bit(7) is set, otherwise an RLE count for the next
data byte. Count = bit(6:0) + 1.
5.3.3
Device status register ‘DSR’
DSR is located at offset 001h in the lower block. It is a read
only register showing the current state of control signals
from the peripheral. Additionally in EPP mode, bit 0 is set
to ‘1’ when an operation times out (see section 5.1.3)
DSR[0]:
EPP mode: Timeout
logic 0 ⇒Timeout has not occurred.
logic 1 ⇒Timeout has occurred (Reading this bit clears it).
Other modes: Unused
This bit is permanently set to 1.
DSR[1]: Unused
This bit is permanently set to 1.
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
DSR[2]: INT#
logic 0 ⇒ A parallel port interrupt is pending.
logic 1 ⇒ No parallel port interrupt is pending.
DCR[3]: nSLIN#
logic 0 ⇒ Set SLIN# output to high (inactive).
logic 1 ⇒ Set SLIN# output to low (active).
This bit is activated (set low) on a rising edge of the ACK#
pin. It is de-activated (set high) after reading the DSR.
During an EPP address or data cycle the ADDRSTB# pin is
driven by the EPP controller, otherwise it is inactive.
DSR[3]: ERR#
logic 0 ⇒ The ERR# input is low.
logic 1 ⇒ The ERR# input is high.
DCR[4]: ACK Interrupt Enable
logic 0 ⇒ ACK interrupt is disabled.
logic 1 ⇒ ACK interrupt is enabled.
DSR[4]: SLCT
logic 0 ⇒ The SLCT input is low.
logic 1 ⇒ The SLCT input is high.
DCR[5]: DIR
logic 0 ⇒ PD port is output.
logic 1 ⇒ PD port is input.
DSR[5]: PE
logic 0 ⇒The PE input is low.
logic 1 ⇒The PE input is high.
This bit is overridden during an EPP address or data cycle,
when the direction of the port is controlled by the bus
access (read/write)
DSR[6]: ACK#
logic 0 ⇒ The ACK# input is low.
logic 1 ⇒ The ACK# input is high.
DCR[7:6]: Reserved
These bits are reserved and always set to “00”.
DSR[7]: nBUSY
logic 0 ⇒ The BUSY input is high.
logic 1 ⇒ The BUSY input is low.
5.3.4
Device control register ‘DCR’
DCR is located at offset 002h in the lower block. It is a
read-write register which controls the state of the peripheral
inputs and enables the peripheral interrupt. When reading
this register, bits 0 to 3 reflect the actual state of STB#,
AFD#, INIT# and SLIN# pins respectively. When in EPP
mode, the WRITE#, DATASTB# AND ADDRSTB# pins are
driven by the EPP controller, although writes to this register
will override the state of the respective lines.
5.3.5
EPP address register ‘EPPA’
EPPA is located at offset 003h in lower block, and is only
used in EPP mode. A byte written to this register will be
transferred to the peripheral as an EPP address by the
hardware. A read from this register will transfer an address
from the peripheral under hardware control.
5.3.6
EPP data registers ‘EPPD1-4’
The EPPD registers are located at offset 004h-007h of the
lower block, and are only used in EPP mode. Data written
or read from these registers is transferred to/from the
peripheral under hardware control.
5.3.7
ECP Data FIFO
DCR[0]: nSTB#
logic 0 ⇒ Set STB# output to high (inactive).
logic 1 ⇒ Set STB# output to low (active).
Hardware transfers data from this 16 bytes deep FIFO to
the peripheral when DCR(5) = ‘0’. When DCR(5) = ‘1’
hardware transfers data from the peripheral to this FIFO.
During an EPP address or data cycle the WRITE# pin is
driven by the EPP controller, otherwise it is inactive.
5.3.8
DCR[1]: nAFD#
logic 0 ⇒ Set AFD# output to high (inactive).
logic 1 ⇒ Set AFD# output to low (active).
During an EPP address or data cycle the DATASTB# pin is
driven by the EPP controller, otherwise it is inactive.
DCR[2]: INIT#
logic 0 ⇒ Set INIT# output to low (active).
logic 1 ⇒ Set INIT# output to high (inactive).
DS-0021 Jun 05
Test FIFO
Used by the software in conjunction with the full and empty
flags to determine the depth of the FIFO and interrupt
levels.
5.3.9
Configuration A register
ECR[7:5] must be set to ‘111’ to access this register.
Interrupts generated will always be level, and the ECP port
only supports an impID of ‘001’.
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5.3.10 Configuration B register
ECR[7:5] must be set to ‘111’ to access this register. Read
only, all bits will be set to 0, except for bit[6] which will
reflect the state of the interrupt.
5.3.11 Extended control register ‘ECR’
The Extended control register is located at offset 002h in
upper block. It is used to configure the operation of the
parallel port.
ECR[4:0]: Reserved - write
These bits are reserved and must always be set to
“00001”.
ECR[0]: Empty - read
When DCR[5} = ‘0’
logic 0 ⇒ FIFO contains at least one byte
logic 1 ⇒ FIFO completely empty
When DCR[5} = ‘1’
logic 0 ⇒ FIFO contains at least one byte
logic 1 ⇒ FIFO contains less than one byte
ECR[1]: Full - read
When DCR[5} = ‘0’
DS-0021 Jun 05
OX12PCI840
logic 0 ⇒ FIFO has at least one free byte
FIFO completely full
When DCR[5} = ‘1’
logic 0 ⇒ FIFO has at least one free byte
logic 1 ⇒ FIFO full
ECR[2]: serviceIntr - read
When DCR[5} = ‘0’
logic 1 ⇒ writeIntrThreshold (8) free bytes or more in
FIFO
When DCR[5} = ‘1’
logic 1 ⇒ readIntrThreshold (8) bytes or more in FIFO
ECR[7:5]: Mode – read / write
These bits define the operational mode of the parallel port.
logic ‘000’
SPP
logic ‘001’
PS2
logic ‘010’
Reserved
logic ‘011’
ECR
logic ‘100’
EPP
logic ‘101’
Reserved
logic ‘110’
Test
logic ‘111’
Config
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6
6.1
SERIAL EEPROM
Specification
The OX12PCI840 can be configured using an optional
serial electrically-erasable programmable read only
memory (EEPROM). If the EEPROM is not present, the
device will remain in its default configuration after reset.
Although this may be adequate for some applications,
many will benefit from the degree of programmability
afforded by this feature. The EEPROM also allows
configuration accesses to the parallel port, which can be
useful for default set ups.
The EEPROM interface is based on the 93C46/56 serial
EEPROM devices which have a proprietary serial interface
known as MicrowireTM. The interface has four pins which
supply the memory device with a clock, a chip-select, and
serial data input and output lines. In order to read from
such a device, a controller has to output serially a read
command and address, then input serially the data. The
93C46/56 and compatible devices have a 16-bit data word
format but differ in memory size (and number of address
bits).
The OX12PCI840 incorporates a controller module which
reads data from the serial EEPROM and writes data into
the configuration register space. It performs this operation
in a sequence which starts immediately after a PCI bus
reset and ends either when the controller finds no
EEPROM is present or when it reaches the end of its data.
NOTE: that any attempted PCI access while data is being
downloaded from the serial EEPROM will result in a retry.
The operation of this controller is described below.
Following device configuration, driver software can access
the serial EEPROM through four bits in the device-specific
Local Configuration Register LCC[27:24]. Software can use
this register to manipulate the device pins in order to read
and modify the EEPROM contents.
Note that 93C46 and 93C56 EEPROM devices offer 128
and 256 bytes of programmable data respectively.
A Windows® based utility to program the EEPROM is
available. For further details please contact Oxford
Semiconductor (see back cover).
MicrowireTM is a trade mark of National Semiconductor. For
a description of MicrowireTM, please refer to National
Semiconductor data manuals.
DS-0021 Jun 05
6.2
EEPROM Data Organisation
The serial EEPROM data is divided in five zones. The size
of each zone is an exact multiple of 16-bit WORDs. Zone0
is allocated to the header. A valid EEPROM program must
contain a header. The EEPROM can be programmed from
the PCI bus. Once the programming is complete, the
device driver should either reset the PCI bus or set
LCC[29] to reload the OX12PCI840 registers from the
serial EEPROM. The general EEPROM data structure is
shown in Table 7.
DATA
Zone
0
1
2
3
4
Size (Words)
Description
One
One or more
One to four
Two or more
Multiples of 2
Header
Local Configuration Registers
Identification Registers
PCI Configuration Registers
Function Access
Table 7: EEPROM data format
6.2.1
Zone0: Header
The header identifies the EEPROM program as valid.
Bits
15:4
3
2
1
0
Description
These bits should return 0x840 to identify a valid
program. Once the OX12C840 reads 0x840 from
these bits, it sets LCC[28] to indicate that a valid
EEPROM program is present.
1 = Zone1 (Local Configuration) exists
0 = Zone1 does not exist
1 = Zone2 (Identification) exists
0 = Zone2 does not exist
1 = Zone3 (PCI Configuration) exists
0 = Zone3 does not exist
1 = Zone4 (Function Access) exists
0 = Zone4 does not exist
The programming data for each zone follows the
proceeding zone if it exists. For example a Header value of
0x840F indicates that all zones exist and they follow one
another in sequence, while 0x8405 indicates that only
Zones 2 and 4 exist where the header data is followed by
Zone2 WORDs, and since Zone3 is missing Zone2
WORDs are followed by Zone4 WORDs.
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OXFORD SEMICONDUCTOR LTD.
6.2.2
Zone1: Local Configuration Registers
The Zone1 region of EEPROM contains the program value
of the vendor-specific Local Configuration Registers using
one or more configuration WORDs. Registers are selected
using a 7-bit byte-offset field. This offset value is the offset
from Base Address Registers in I/O or memory space (see
section 4.4).
Bits
15
Note: Not all of the registers in the Local Configuration Register set are
writable by EEPROM. If bit3 of the header is set, Zone1
configuration WORDs follow the header declaration. The
format of configuration WORDs for the Local Configuration
Registers in Zone1 are described in Table 8.
14:8
7:0
Description
‘0’ = There are no more Configuration WORDs
to follow in Zone1. Move to the next available
zone or end EEPROM program if no more zones
are enabled in the Header.
‘1’ = There is another Configuration WORD to
follow for the Local Configuration Registers.
These seven bits define the byte-offset of the
Local configuration register to be programmed.
For example the byte-offset for LT2[23:16] is
0x0E.
8-bit value of the register to be programmed
Table 8: Zone 1 data format
6.2.3
Zone2: Identification Registers
The Zone2 region of EEPROM contains the program value
for Vendor ID and Subsystem Vendor ID. The format of
Device Identification configuration WORDs are described in
Table 9.
Bits
15
14:8
7:0
Description
‘0’ = There are no more Zone2 (Identification)
bytes to program. Move to the next available
zone or end EEPROM program if no more zones
are enabled in the Header.
‘1’ = There is another Zone2 (Identification) byte
to follow.
0x00 = Vendor ID bits [7:0].
0x01 = Vendor ID bits [15:8].
0x02 = Subsystem Vendor ID [7:0].
0x03 = Subsystem Vendor ID [15:8].
0x03 to 0x7F = Reserved.
8-bit value of the register to be programmed
Table 9: Zone 2 data format
DS-0021 Jun 05
6.2.4
Zone3: PCI Configuration Registers
The Zone3 region of EEPROM contains any changes
required to the PCI Configuration registers (with the
exception of Vendor ID and Subsystem Vendor ID which
are programmed in Zone2). This zone consists of a
function header WORD, and one or more configuration
WORDs for that function. The function header is described
in Table 10.
Bits
15
14:3
2:0
Description
‘0’ = End of Zone 3.
‘1’ = Define this function header.
Reserved. Write zeros.
Function number for the following configuration
WORD(s).
‘000’ = Function0
Other values = Reserved.
Table 10: Zone 3 data format (Function Header)
The subsequent WORDs for each function contain the
address offset and a byte of programming data for the PCI
Configuration Space belonging to the function number
selected by the proceeding Function-Header. The format of
configuration WORDs for the PCI Configuration Registers
are described below.
Page 23
OXFORD SEMICONDUCTOR LTD.
Bits
15
14:8
7:0
OX12PCI840
Description
‘0’ = This is the last configuration WORD in for
the selected function in the Function-Header.
‘1’ = There is another WORD to follow for this
function.
These seven bits define the byte-offset of the PCI
configuration register to be programmed. For
example the byte-offset of the Interrupt Pin
register is 0x3D. Offset values are tabulated in
section 4.2.
8-bit value of the register to be programmed
Table 11: Zone 3 data format (data)
Table 12 shows which PCI Configuration registers are
writable from the EEPROM for each function.
Offset
0x02
0x03
0x06
0x06
0x06
0x09
0x0A
0x0B
0x2E
0x2F
0x3D
0x42
Bits
7:0
7:0
3:0
4
7:5
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0x43
7:0
Description
Device ID bits 7 to 0.
Device ID bits 15 to 8.
Must be ‘0000’.
Extended Capabilities.
Must be ‘000’.
Class Code bits 7 to 0.
Class Code bits 15 to 8.
Class Code bits 23 to 16.
Subsystem ID bits 7 to 0.
Subsystem ID bits 15 to 8.
Interrupt pin.
Power Management Capabilities
bits 7 to 0.
Power Management Capabilities
bits 15 to 8.
Table 12: EEPROM-writable PCI configuration registers
DS-0021 Jun 05
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OXFORD SEMICONDUCTOR LTD.
6.2.5
OX12PCI840
Zone4: Function Access
Zone 4 allows the parallel port to be configured, prior to PCI access. This can be useful for patching designs to work with generic
drivers, enabling interrupts, etc. Each 8-bit (function) access is equivalent to accessing the function through I/O bars 0 and 1,
with the exception that a function read access does not return any data (discarded). Each entry in zone 4 comprises 2 16 bit
words. The format is as shown in Table 14.
1st WORD of FUNCTION ACCESS PAIR
Word
Bits
15
14:12
11
10:8
7:0
Description
‘1’ - another WORD to follow
BAR number to access
000 for BAR 0
001 for BAR 1
others reserved
‘0’ : Read access (data discarded)
‘1’ : Write access
Reserved – write 0’s
I/O address to access
This is the location (I/O offset from
the relevant Base Address) that
needs to be written/read.
2nd WORD of FUNCTION ACCESS PAIR
Word
Bits
15
14:8
7:0
DS-0021 Jun 05
Description
‘1’ – another function access
WORD pair to follow.
‘0’ – no more function access
pairs. End EEPROM program.
Reserved – write 0’s
Data to be written to location.
Field unused for function access
READS.
Page 25
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
7
OPERATING CONDITIONS
Symbol
VDD
VIN
IIN
TSTG
Parameter
DC supply voltage
DC input voltage
DC input current
Storage temperature
Min
-0.3
-0.3
-40
Max
7.0
VDD + 0.3
+/- 10
125
Units
V
V
mA
°C
Min
4.5
0
Max
5.5
70
Units
V
°C
Table 13: Absolute maximum ratings
Symbol
VDD
TC
Parameter
DC supply voltage
Temperature
Table 14: Recommended operating conditions
8
DC ELECTRICAL CHARACTERISTICS
8.1
Non-PCI I/O Buffers
Symbol
VDD
VIH
Parameter
Supply voltage
Input high voltage
VIL
Input low voltage
CIL
COL
IIH
IIL
VOH
VOH
VOL
VOL
IOZ
Cap of input buffers
Cap of output buffers
Input high leakage current
Input low leakage current
Output high voltage
Output high voltage
Output low voltage
Output low voltage
3-state output leakage current
Symbol
ICC
Condition
Commercial
TTL Interface 1
TTL Schmitt trig
TTL Interface 1
TTL Schmitt trig
Min
4.75
2.0
2.0
Vin = VDD
Vin = VSS
IOH = 1 μA
IOH = 4 mA 2
IOL = 1 μA
IOL = 4 mA 2
Parameter
-10
-10
Max
5.25
Units
V
V
0.8
0.8
5.0
10.0
10
10
V
VDD – 0.05
2.4
0.05
0.4
10
-10
Typical
Peak
Supply current in operating mode
38
178
Supply current when idle
13
23
pF
pF
μA
μA
V
V
V
V
μA
Units
mA
Table 15: Characteristics of non-PCI I/O buffers
Note 1:
Note 2:
All input buffers are TTL with the exception of PCI buffers
IOH and IOL are 12 mA for PD/LBDB[7:0] and other Parallel Port Outputs. They are 4 mA for all other non-PCI outputs
DS-0021 Jun 05
Page 26
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
8.2
PCI I/O Buffers
Symbol
Parameter
DC Specifications
VCC
Supply voltage
VIL
Input low voltage
VIH
Input high voltage
IIL
Input low leakage current
IIH
Input high leakage current
VOL
Output low voltage
VOH
Output low voltage
CIN
Input pin capacitance
CCLK
CLK pin capacitance
CIDSEL
IDSEL pin capacitance
LPIN
Pin inductance
AC Specifications
Switching current
IOH(AC)
high
(Test point)
Switching current
IOL(AC)
low
ICL
(Test point)
Low clamp current
IHL
High clamp current
SlewR
SlewF
Output rise slew rate
Output fall slew rate
Condition
VIN = 0.5V
VIN = 2.7V
IOUT = -2 mA
IOUT = 3 mA, 6mA
Min
Max
Unit
4.75
-0.5
2.0
5.25
0.8
VCC + 0.5
-70
70
0.55
V
V
V
μA
μA
V
V
pF
pF
pF
nH
2.4
5
-44
0 < VOUT ≤ 1.4
-44 (VOUT - 1.4)/0.024
1.4 < VOUT ≤ 2.4
mA
Eq. A
3.1 < VOUT ≤ VCC
VOUT = 3.1
-142
95
VOUT ≥ 2.2
2.2 > VOUT > 0.55
0.71 > VOUT > 0
VOUT = 0.71
-5 < VIN < -1
VCC+4 < VIN
VCC+1
0.4V to 2.4V
2.4V to 0.4V
10
12
8
10
VOUT / 0.023
mA
Eq. B
206
<
-25 + (VIN +1)/
0.015
25+ (VIN -VCC -1)/
0.015
1
1
mA
mA
5
5
V/nS
V/nS
Table 16: Characteristics of PCI I/O buffers
Eq. A :
Eq. B :
DS-0021 Jun 05
IOH = 11.9 * (VOUT - 5.25) * (VOUT + 2.45)
IOL = 78.5 * VOUT * (4.4 - VOUT )
for 3.1 < VOUT ≤ VCC
for 0.71 > VOUT > 0
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OXFORD SEMICONDUCTOR LTD.
9
9.1
OX12PCI840
AC ELECTRICAL CHARACTERISTICS
PCI Bus
The timings for PCI pins comply with PCI Specification for the 5.0 Volt signalling environment.
DS-0021 Jun 05
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
10 TIMING WAVEFORMS
CLK
1
2
3
4
FRAME#
AD[31:0]
Address
C/BE[3:0]#
Bus CMD
Data
Byte enable#
Data transfer
IRDY#
TRDY#
DEVSEL#
STOP#
Figure 1: PCI Read transaction from Local Configuration registers
CLK
1
2
3
4
FRAME#
Address
C/BE[3:0]#
Bus CMD
IRDY#
TRDY#
Data
Byte enable#
Data transfer
AD[31:0]
DEVSEL#
STOP#
Figure 2: PCI Write transaction to Local Configuration Registers
DS-0021 Jun 05
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OX12PCI840
OXFORD SEMICONDUCTOR LTD.
11 PACKAGE DETAILS
Figure 3: 100-pin QFP Package
DS-0021 Jun 05
Page 30
OXFORD SEMICONDUCTOR LTD.
OX12PCI840
Figure 4: Custom Marking on the 100-pin QFP Package
12 ORDERING INFORMATION
OX12PCI840-PQC60-A
Revision
Package Type – 100-pin PQFP
Note: the Oxford Semiconductor product OX12PCI840-PQC60-A, which has been supplied with the marking “OX12PCI840-TQC60-A” fully conforms to the
OX12PCI840-PQC60-A data sheet issued by Oxford Semiconductor.
The discrepancy is due to an error with the marking tool associated with this device, which has resulted in parts being marked “OX12PCI840-TQC60-A”.
However, the part is supplied in a PQFP package type as stated in the data sheet.
Oxford Semiconductor apologise for any confusion that this may cause or may have caused.
OX12PCI840-PQ A G
Green (RoHS compliant)
Revision
Package Type – 100-pin PQFP
DS-0021 Jun 05
Page 31
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
13 NOTES
This page has been intentionally left blank
DS-0021 Jun 05
Page 32
OXFORD SEMICONDUCTOR LTD.
OX12PCI840
14 CONTACT DETAILS
Oxford Semiconductor Ltd.
25 Milton Park
Abingdon
Oxfordshire
OX14 4SH
United Kingdom
Telephone:
Fax:
Sales e-mail:
Tech support e-mail:
Web site:
+44 (0)1235 824900
+44 (0)1235 821141
[email protected]
[email protected]
http://www.oxsemi.com
DISCLAIMER
Oxford Semiconductor believes the information contained in this document to be accurate and reliable. However, it is subject to
change without notice. No responsibility is assumed by Oxford Semiconductor for its use, nor for infringement of patents or other
rights of third parties. No part of this publication may be reproduced, or transmitted in any form or by any means without the prior
consent of Oxford Semiconductor Ltd. Oxford Semiconductor’s terms and conditions of sale apply at all times.
DS-0021 Jun 05
Page 33
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