Renesas M37544M2-XXXHP Single-chip 8-bit cmos microcomputer Datasheet

7544 Group
REJ03B0012-0104Z
Rev.1.04
2004.06.08
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
•
The 7544 Group is the 8-bit microcomputer based on the 740 family core technology.
The 7544 Group has a serial I/O, 8-bit timers, a 16-bit timer, and
an A/D converter, and is useful for control of home electric appliances and office automation equipment.
•
•
FEATURES
•
•
•
•
•
•
•
•
Basic machine-language instructions ...................................... 71
The minimum instruction execution time ......................... 0.25 µs
(at 8 MHz oscillation frequency, double-speed mode for the
shortest instruction)
Memory size ROM ......................................................... 8 K bytes
RAM ........................................................ 256 bytes
Programmable I/O ports ........................................................... 25
Interrupts ................................................. 12 sources, 12 vectors
Timers ............................................................................. 8-bit ✕ 2
...................................................................................... 16-bit ✕ 1
Serial I/O ...................... 8-bit ✕ 1 (UART or Clock-synchronized)
A/D converter ................................................. 8-bit ✕ 6 channels
•
•
Clock generating circuit ............................................. Built-in type
(low-power dissipation by an on-chip oscillator enabled)
(connect to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation)
Watchdog timer ............................................................ 16-bit ✕ 1
Power source voltage
XIN oscillation frequency at ceramic/quartz-crystal oscillation, in
double-speed mode
At 8 MHz .................................................................... 4.5 to 5.5 V
XIN oscillation frequency at ceramic/quartz-crystal oscillation, in
high-speed mode
At 8 MHz .................................................................... 4.0 to 5.5 V
XIN oscillation frequency at RC oscillation
At 4 MHz .................................................................... 4.0 to 5.5 V
Power dissipation ........................................... 22.5mW(standard)
Operating temperature range ................................... –20 to 85 °C
APPLICATION
Office automation equipment, factory automation equipment,
home electric appliances, consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
1
32
2
31
3
30
4
29
5
6
7
8
9
10
11
12
13
M37544M2-XXXSP
M37544G2SP
P12/SCLK
P13/SRDY
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
XIN
XOUT
VSS
28
27
26
25
24
23
22
21
20
14
19
15
18
16
17
Package type : 32P4B
Fig. 1 Pin configuration (32P4B type)
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REJ03B0012-0104Z
page 1 of 66
P11/TXD
P10/RXD
P07(LED7)
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
P37(LED13)/INT0
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
17
18
20
19
22
21
24
25
16
26
15
27
28
14
M37544M2-XXXGP
13
M37544G2GP
12
29
8
7
6
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
VSS
XOUT
XIN
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
5
9
3
10
32
4
11
31
1
30
2
P07(LED7)
P10/RXD
P11/TXD
P12/SCLK
P13/SRDY
P14/CNTR0
P20/AN0
P21/AN1
23
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
P37(LED13)/INT0
7544 Group
Package type : 32P6U-A
Fig. 2 Pin configuration (32P6U-A type)
1
42
2
41
3
40
4
39
5
38
6
37
7
36
8
9
10
11
12
13
14
M37544RSS
P14/CNTR0
NC
NC
P20/AN0
P21/AN1
NC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
NC
NC
NC
NC
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
35
34
33
32
31
30
29
15
28
16
27
17
26
18
25
19
24
20
23
21
22
Package type: 42S1M
Fig. 3 Pin configuration (42S1M type)
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REJ03B0012-0104Z
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P13/SRDY
P12/SCLK
P11/TXD
P10/RXD
P07(LED7)
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
NC
P37(LED13)/INT0
NC
NC
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
[N.C.]
P34(LED12)/INT1
P37(LED13)/INT0
P00(LED0)/CNTR1
P01(LED1)
P02(LED2)
P03(LED3)/TXOUT
P04(LED4)
P05(LED5)
7544 Group
27 26 25 24 23 22 21 20 19
P06(LED6)
28
18
[N.C.]
P07(LED7)
29
17
P33(LED11)
P10/RxD
30
16
P32(LED10)
P11/TxD
31
M37544M2-XXXHP 15
P31(LED9)
P12/SCLK
32
14
P30(LED8)
P13/SRDY
33
13
Vss
P14/CNTR0
34
12
XOUT
P20/AN0
35
11
XIN
P21/AN1
36
10
[N.C.]
M37544G2HP (Note)
Package type: 36PJW-A
Fig. 4 Pin configuration (36PJW-A type)
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REJ03B0012-0104Z
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9
[N.C.]
8
Vcc
7
CNVss
6
RESET
5
VREF
4
P25/AN5
3
P24/AN4
P23/AN3
2
P22/AN2
1
N.C.: Non Connection
Note: Only ES version
(MP: no plan)
Fig. 5 Functional block diagram (32P4B package)
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15
Clock output
X OUT
VREF
10
A/D
converter
(8)
Watchdog timer
Reset
Clock generating circuit
14
Clock input
X IN
I/O port P3
I/O port P2
9 8 7 6 5 4
22 21 20 19 18 17
0
0
PCH
P2(6)
INT
1
INT
ROM
P3(6)
RAM
13
16
CPU
VCC
VSS
SI/O(8)
PS
PCL
S
Y
X
A
P1(5)
I/O port
P1
3 2 1 32 31
11
Reset input
RESET
CNTR0
I/O port P0
TXOUT
Timer X (8)
Timer 1 (8)
30 29 28 27 26 25 24 23
P0(8)
CNTR1
Timer A (16)
Prescaler X (8)
Prescaler 1 (8)
12
CNVSS
Key-on wakeup
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
7544 Group
FUNCTIONAL BLOCK
Fig. 6 Functional block diagram (32P6U package)
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REJ03B0012-0104Z
page 5 of 66
VREF
5
A/D
converter
(8)
Watchdog timer
Reset
Clock generating circuit
0
PC H
I/O port P2
4 3 2 1 32 31
17 16 15 14 13 12
I/O port P3
P2(6)
INT0 INT1
ROM
P3(6)
RAM
CPU
8
11
A
SI/O(8)
PS
PC L
S
Y
X
P1(5)
I/O port P1
30 29 28 27 26
6
RESET
9
Reset input
VCC
VSS
X IN X OU
T
10
Clock input Clock output
TXOUT
P0(8)
I/O port P0
25 24 23 22 21 20 19 18
CNTR1
Timer A (16)
Timer X (8)
CNTR0
Timer 1 (8)
Prescaler X (8)
Prescaler 1 (8)
7
CNVSS
Key-on wakeup
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U)
7544 Group
Fig. 7 Functional block diagram (36PJW package)
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REJ03B0012-0104Z
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12
VREF
5
A/D
converter
(8)
Watchdog timer
Reset
Clock generating circuit
11
Clock input Clock output
X IN X OUT
I/O port P3
21 20 17 16 15 14
P3
(6)
RAM
1
INT0 INT
ROM
0
PC H
I/O port P2
4 3 2 1 36 35
P2
(6)
8
13
C P U
VCC
VSS
SI/
O(8)
PS
PC L
S
Y
X
A
P1(5)
I/O port
34 33 32 31 30
6
Reset input
RESET
Timer X (8)
Timer 1 (8)
1
I/O port P0
29 28 27 26 25 24 23 22
P0(8)
0
CNTR
TXou
t
CNTR
Timer A (16)
Prescaler X (8)
Prescaler 1 (8)
7
CNVSS
Key-on wakeup
FUNCTIONAL BLOCK DIAGRAM (Package: 36PJW)
7544 Group
7544 Group
PIN DESCRIPTION
Table 1 Pin description
Pin
Name
Function
Function expect a port function
Vcc, Vss
Power source
•Apply voltage of 4.0 to 5.5 V to Vcc, and 0 V to Vss.
VREF
Analog reference •Reference voltage input pin for A/D converter
voltage
CNVss
______
RESET
CNVss
Reset input
•Chip operating mode control pin, which is always connected to Vss.
XIN
Clock input
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins.
XOUT
Clock output
•For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.
•Reset input pin for active “L”
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• When the on-chip oscillator is selected as the main clock, connect XIN pin to VCC and leave XOUT open.
P00/CNTR1
P01
P02
P03/TXOUT
P04–P07
I/O port P0
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
• Key-input (key-on wake up
interrupt input) pins
• Timer X and timer A function
pin
•CMOS 3-state output structure
•P0 can output a large current for driving LED.
•Whether a built-in pull-up resistor is to be used or not can be determined by program.
P10/RxD
P11/TxD
I/O port P1
CLK
P12/S
____
P13/SRDY
•5-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
• Serial I/O function pin
•CMOS compatible input level
P14/CNTR0
•CMOS 3-state output structure
• Timer X function pin
•CMOS/TTL level can be switched for P10 and P12
P20/AN0–P25/AN5 I/O port P2
•6-bit I/O port having almost the same function as P0
P30–P33
•CMOS compatible input level
•CMOS 3-state output structure
•6-bit I/O port
I/O port P3
• Input pins for A/D converter
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched for P34 and P37).
•CMOS 3-state output structure
•P3 can output a large current for driving LED.
P34/INT1
P37/INT0
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REJ03B0012-0104Z
•Whether a built-in pull-up resistor is to be used or not can be determined by program.
page 7 of 66
• Interrupt input pins
7544 Group
GROUP EXPANSION
Memory size
ROM/PROM size .............................................................. 8 K bytes
RAM size ......................................................................... 256 bytes
We are planning to expand the 7544 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and
Emulator MCU .
Package
32P4B .................................................. 32-pin plastic molded SDIP
32P6U-A ...................... 0.8 mm-pitch 32-pin plastic molded LQFP
36PJW-A ...................... 0.5 mm-pitch 36-pin plastic molded SSOP
42S1M .................................... 42-pin shrink ceramic PIGGY BACK
ROM size
(bytes)
M37544M2
8K
M37544G2
0
RAM size
(bytes)
256
Fig. 8 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
Part number
(P) ROM size (bytes) RAM size
ROM size for User ()
(bytes)
M37544M2-XXXSP
8192
M37544M2-XXXGP
(8062)
256
M37544M2-XXXHP
Package
Remarks
32P4B
Mask ROM version
32P6U-A
Mask ROM version
36PJW-A
Mask ROM version
M37544G2SP
32P4B
One Time PROM version (blank)
M37544G2GP
M37544G2HP
32P6U-A
36PJW-A
One Time PROM version (blank)
One Time PROM version (blank)
(Note)
M37544RSS
256
Note: Only ES version (MP: no plan)
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REJ03B0012-0104Z
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42S1M
Emulator MCU
7544 Group
FUNCTIONAL DESCRIPTION
Stack pointer (S)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are
shown in Fig. 10.
Index register X (X), Index register Y (Y)
Program counter (PC)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real
address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine-language
instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL
for details on each instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
This instruction cannot be used while CPU operates by an on-chip
oscillator.
Accumulator (A)
b7
b0
Accumulator
A
b7
b0
Index Register X
X
b7
b0
Index Register Y
Y
b7
b0
Stack Pointer
S
b15
b7
PCH
b0
Program Counter
PCL
b7
b0
N V T B D I Z C Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 9 740 Family CPU register structure
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7544 Group
On-going Routine
Interrupt request
(Note)
M (S)
(PCH)
(S)
(S – 1)
M (S)
(PCL)
(S)
(S – 1)
M (S)
(PS)
(S)
(S – 1)
Execute JSR
M (S)
Store Return Address
on Stack
(S)
M (S)
(S)
(PCH)
(S – 1)
(PCL)
(S – 1)
Subroutine
Restore Return
Address
(PCL)
M (S)
(S + 1)
(PCH)
M (S)
I Flag “0” to “1”
Fetch the Jump Vector
Execute RTI
(S + 1)
(S)
Store Contents of Processor
Status Register on Stack
Interrupt
Service Routine
Execute RTS
(S)
Store Return Address
on Stack
Note : The condition to enable the interrupt
(S)
(S + 1)
(PS)
M (S)
(S)
(S + 1)
(PCL)
M (S)
(S)
(S + 1)
(PCH)
M (S)
Restore Contents of
Processor Status Register
Restore Return
Address
Interrupt enable bit is “1”
Interrupt disable flag is “0”
Fig. 10 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
Processor status register
PHP
PLA
PLP
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7544 Group
Processor status register (PS)
The processor status register is an 8-bit register consisting of
flags which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)
flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction. Interrupts are disabled when the I flag is
“1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status
register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the
stack with the break flag set to “1”. The saved processor status is
the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed between accumulator and memory, e.g. the results of an operation
between two memory locations is stored in the accumulator. When
the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory
and memory, memory and I/O, and I/O and I/O. In this case, the
result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1.
The address of memory location 1 is specified by index register X,
and the address of memory location 2 is specified by normal addressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte of
signed data. It is set if the result exceeds +127 to -128. When the
BIT instruction is executed, bit 6 of the memory location operated
on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored in
the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
N flag
Set instruction
SEC
–
SEI
SED
–
SET
–
–
Clear instruction
CLC
–
CLI
CLD
–
CLT
CLV
–
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7544 Group
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM: address 003B16, initial value: 8016)
Processor mode bits (Note 1)
b1 b0
0 0 Single-chip mode
0 1
Not available
1 0
1 1
Stack page selection bit
0 : 0 page
1 : 1 page
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method.
On-chip oscillator oscillation control bit
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
XIN oscillation control bit
0 : Ceramic/quartz-crystal or RC oscillation enabled
1 : Ceramic/quartz-crystal or RC oscillation stop
Oscillation mode selection bit (Note 1)
0 : Ceramic/quartz-crystal oscillation
1 : RC oscillation
Clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(XIN)/2 (High-speed mode)
0 1 : f(φ) = f(XIN)/8 (Middle-speed mode)
1 0 : applied from on-chip oscillator
1 1 : f(φ) = f(XIN) (Double-speed mode)(Note 2)
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37544RSS”.)
2: These bits are used only when a ceramic/quartz-crystal oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 11 Structure of CPU mode register
After releasing reset
Switch the oscillation mode
selection bit (bit 5 of CPUM)
Wait by on-chip oscillator operation
until establishment of oscillator clock
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Main routine
Fig. 12 Switching method of CPU mode register
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Start with an on-chip oscillator
An initial value is set as a ceramic/quartz-crystal
oscillation mode. When it is switched to an RC
oscillation, its oscillation starts.
When using a ceramic/quartz-crystal oscillation, wait
until establlishment of oscillation from oscillation starts.
When using an RC oscillation, wait time is not required
basically (time to execute the instruction to switch from
an on-chip oscillator meets the requirement).
Select 1/1, 1/2, 1/8 or on-chip oscillator.
7544 Group
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as
I/O ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF 16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page
addressing mode.
■ Note on use
The content of RAM is undefined when the microcomputer is reset. The initial values must be surely set before you use it.
000016
SFR area
Zero page
004016
RAM
010016
RAM area
RAM capacity
(bytes)
address
XXXX16
256
013F16
XXXX16
Reserved area
044016
Disable
YYYY16
Reserved ROM area
(128 bytes)
ZZZZ16
ROM
FF0016
ROM area
ROM capacity
(bytes)
address
YYYY16
address
ZZZZ16
8192
E00016
E08016
Interrupt vector area
FFFE16
FFFF16
Fig. 13 Memory map diagram
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Special page
FFDC16
Reserved ROM area
7544 Group
Port P0 (P0)
002016
Reserved
000116
Port P0 direction register (P0D)
002116
Reserved
000216
Port P1 (P1)
002216
Reserved
000316
Port P1 direction register (P1D)
002316
Reserved
000416
Port P2 (P2)
002416
Reserved
000516
Port P2 direction register (P2D)
002516
Reserved
000616
Port P3 (P3)
002616
Reserved
000716
Port P3 direction register (P3D)
002716
Reserved
000816
Reserved
002816
Prescaler 1 (PRE1)
000916
Reserved
002916
Timer 1 (T1)
000A16
Reserved
002A16
Reserved
000B16
Reserved
002B16
Timer X mode register (TXM)
000C16
Reserved
002C16
Prescaler X (PREX)
000D16
Reserved
002D16
Timer X (TX)
000E16
Reserved
002E16
Timer count source set register1 (TCSS1)
000F16
Reserved
002F16
Timer count source set register2 (TCSS2)
001016
Reserved
003016
Reserved
001116
Reserved
003116
Reserved
001216
Reserved
003216
Reserved
001316
Reserved
003316
Reserved
001416
Reserved
003416
A/D control register (ADCON)
001516
Reserved
003516
A/D register (AD)
001616
Pull-up control register (PULL)
003616
Reserved
001716
Port P1P3 control register (P1P3C)
003716
Reserved
001816
Transmit/Receive buffer register (TB/RB)
003816
MISRG
001916
Serial I/O status register (SIOSTS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O control register (SIOCON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
Timer A mode register (TAM)
003D16
Interrupt request register 2 (IREQ2)
000016
001E16
Timer A (low-order) (TAL)
003E16
Interrupt control register 1 (ICON1)
001F16
Timer A (high-order) (TAH)
003F16
Interrupt control register 2 (ICON2)
Note : Do not access to the SFR area including nothing.
Fig. 14 Memory map of special function register (SFR)
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7544 Group
I/O Ports
[Pull-up control register] PULL
By setting the pull-up control register (address 001616), ports P0
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes
an output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
b7
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 001716 ), a
CMOS input level or a TTL input level can be selected for ports
P10, P12, P34, and P37 by program.
b0
Pull-up control register
(PULL: address 001616, initial value: 0016)
P00 pull-up control bit
P01 pull-up control bit
P02, P03 pull-up control bit
P04 – P07 pull-up control bit
P30 – P33 pull-up control bit
P34 pull-up control bit
Disable
0 : Pull-up Off
1 : Pull-up On
P37 pull-up control bit
Note : Pins set to output ports are disconnected from pull-up control.
Fig. 15 Structure of pull-up control register
b7
b0
Port P1P3 control register
(P1P3C: address 001716, initial value: 0016)
P37/INT0 input level selection bit
0 : CMOS level
1 : TTL level
P34/INT1 input level selection bit
0 : CMOS level
1 : TTL level
P10,P12 input level selection bit
0 : CMOS level
1 : TTL level
Disable
Fig. 16 Structure of port P1P3 control register
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7544 Group
Table 5 I/O port function table
Pin
Name
Input/output
I/O format
P00/CNTR1
P01
P02
P03/TXOUT
P04–P07
I/O port P0 I/O individual •CMOS compatible
bits
input level
P10/RxD
P11/TxD
P12/S
CLK
____
P13/SRDY
I/O port P1
•CMOS 3-state output
(Note)
P14/CNTR0
P20/AN0–
P25/AN5
I/O port P2
P30–P33
I/O port P3
Note : Ports P10, P12, P34, and P37 are CMOS/TTL level.
page 16 of 66
Related SFRs
Diagram No.
Pull-up control register
Timer X mode register
Timer A mode register
Interrupt edge selection
register
(1)
(2)
(3)
Serial I/O function
input/output
Serial I/O control register
Port P1,P3 control register
(4)
(5)
(6)
(7)
Timer X function input/output
Timer X mode register
(8)
A/D conversion input
A/D control register
(9)
Pull-up control register
(10)
Interrupt edge selection
register
Pull-up control register
Port P1,P3 control register
(11)
External interrupt input
P34/INT1
P37/INT0
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Non-port function
Key input interrupt
Timer X function output
Timer A function input
7544 Group
(1)Port P00
(2)Ports P01,P02,P04–P07
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
CNTR1 interrupt input
To key input interrupt
generating circuit
To key input interrupt
generating circuit
P00 key-on wakeup
selection bit
(4)Port P10
(3)Port P03
Pull-up control
Serial I/O enable bit
Receive enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
P10, P12
input level
selection bit
Timer output
P03/TXOUT
output valid
Serial I/O input
*
To key input interrupt
generating circuit
(6)Port P12
(5)Port P11
P11/TxD P-channel output disable bit
Serial I/O enable bit
Transmit enable bit
Direction
register
Data bus
Port latch
Serial I/O synchronous
clock selection bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Direction
register
Data bus
Port latch
P10, P12
input level
selection bit
Serial I/O output
Serial I/O clock output
Serial I/O clock input
*
*
P10, P12, P34, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 17 Block diagram of ports (1)
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7544 Group
(7) Port P13
(8) Port P14
Direction
register
Serial I/O mode selection bit
Serial I/O enable bit
SRDY output enable bit
Direction
register
Data bus
Data bus
Port latch
Port latch
Pulse output mode
Timer output
CNTR0 interrupt input
Serial I/O ready output
(10) Ports P30–P33
(9) Ports P20–P25
Direction
register
Pull-up control
Direction
register
Data bus
Port latch
Data bus
Port latch
A/D converter input
Analog input pin
selection bit
(11) Ports P34, P37
Pull-up control
Direction
register
Data bus
Port latch
P3 input level
selection bit
INT interrupt input
*
*
P10, P12, P34, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 18 Block diagram of ports (2)
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7544 Group
Interrupts
Interrupts occur by 12 different sources : 5 external sources, 6 internal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by
the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to “1” and the interrupt disable flag is set
to “0”, an interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the
interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
[Interrupt edge selection register] INTEDGE
The valid edge of external interrupt INT0 and INT1 can be selected
by the interrupt edge selection bit, respectively.
By the key-on wakeup selection bit, enable/disable of a key-on
wakeup of P00 pin can be selected.
■ Notes on use
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A16)
Timer X mode register (address 2B16)
Timer A mode register (address 1D16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit) to “1”.
➂ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
Table 6 Interrupt vector address and priority
Interrupt source Priority
Vector addresses (Note 1)
High-order
Low-order
Interrupt request generating conditions
Remarks
Reset (Note 2)
1
FFFD16
FFFC16
At reset input
Serial I/O receive
Serial I/O transmit
2
3
FFFB16
FFFA16
FFF916
FFF816
At completion of serial I/O data receive
At completion of serial I/O transmit shift or
when transmit buffer is empty
INT0
4
FFF716
FFF616
At detection of either rising or falling edge of
INT0 input
External interrupt
(active edge selectable)
INT1
5
FFF516
FFF416
At detection of either rising or falling edge of
INT1 input
External interrupt
(active edge selectable)
Key-on wake-up
6
FFF316
FFF216
At falling of conjunction of input logical level
for port P0 (at input)
External interrupt (valid at falling)
CNTR0
7
FFF116
FFF016
At detection of either rising or falling edge of
CNTR0 input
External interrupt
(active edge selectable)
CNTR1
8
FFEF16
FFEE16
External interrupt
(active edge selectable)
Timer X
9
FFED16
FFEC16
At detection of either rising or falling edge of
CNTR1 input
At timer X underflow
Reserved area
—
FFEB16
FFEA16
Not available
Reserved area
—
FFE816
Not available
Timer A
10
FFE916
FFE716
At timer A underflow
Reserved area
—
FFE516
FFE616
FFE416
A/D conversion
Timer 1
11
12
FFE316
FFE216
FFE116
FFE016
At completion of A/D conversion
At timer 1 underflow
Reserved area
—
FFDF16
FFDE16
Not available
BRK instruction
13
FFDD16
FFDC16
At BRK instruction execution
Not available
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
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Non-maskable
STP release timer underflow
Non-maskable software interrupt
7544 Group
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 19 Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16, initial value : 0016)
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT1 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Disable (returns “0” when read)
P00 key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16, initial value : 0016)
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
INT0 interrupt request bit
INT1 interrupt request bit
Key-on wake up interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Timer X interrupt request bit
b7
b0 Interrupt request register 2
(IREQ2 : address 003D16, initial value : 0016)
Disable (returns “0” when read)
Disable (returns “0” when read)
Timer A interrupt request bit
Disable (returns “0” when read)
A/D conversion interrupt request bit
Timer 1 interrupt request bit
Disable (returns “0” when read)
b7
0 : Interrupts disabled
1 : Interrupts enabled
b0 Interrupt control register 2
(ICON2 : address 003F16, initial value : 0016)
Disable (returns “0” when read)
Disable (returns “0” when read)
Timer A interrupt enable bit
Disable (returns “0” when read)
A/D conversion interrupt enable bit
Timer 1 interrupt enable bit
Disable (returns “0” when read)
(Do not write “1” to this bit)
Fig. 20 Structure of Interrupt-related registers
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0 : No interrupt request issued
1 : Interrupt request issued
b0 Interrupt control register 1
(ICON1 : address 003E16, initial value : 0016)
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
INT0 interrupt enable bit
INT1 interrupt enable bit
Key-on wake up interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Timer X interrupt enable bit
b7
0 : No interrupt request issued
1 : Interrupt request issued
page 20 of 66
0 : Interrupts disabled
1 : Interrupts enabled
7544 Group
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L”
level to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes
from “1” to “0”. An example of using a key input interrupt is shown
in Figure 21, where an interrupt request is generated by pressing
one of the keys provided as an active-low key matrix which uses
ports P00 to P03 as input ports.
Port PXx
“L” level output
PULL register
bit 3 = “0”
*
**
P07 output
Port P07
Direction register = “1”
Key input interrupt request
Port P07
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P06 output
Port P06
Direction register = “1”
Port P06
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P05 output
Port P05
Direction register = “1”
Port P05
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P04 output
Port P04
Direction register = “1”
Port P04
latch
Falling edge
detection
PULL register
bit 2 = “1”
*
**
P03 input
Port P03
Direction register = “0”
Port P03
latch
Falling edge
detection
PULL register
bit 2 = “1”
*
**
P02 input
Port P02
Direction register = “0”
Port P02
latch
Falling edge
detection
PULL register
bit 1 = “1”
*
**
P01 input
Port P01
Direction register = “0”
Port P01
latch
Falling edge
detection
PULL register
bit 0 = “1”
*
**
P00 input
Port P00
Direction register = “0”
Port P00
latch
Falling edge
detection
Port P00 key-on wakeup
selection bit
* P-channel transistor for pull-up
** CMOS output buffer
Fig. 21 Connection example when using key input interrupt and port P0 block diagram
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page 21 of 66
Port P0
Input read circuit
7544 Group
Timers
●Timer A
The 7544 Group has 3 timers: timer 1, timer A and timer X.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding
timer latch is reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to each timer is set to “1”.
Timer A is a 16-bit timer and counts the signal selected by the
timer A count source selection bit. When Timer A underflows, the
timer A interrupt request bit is set to “1”.
Timer A consists of the low-order of Timer A (TAL) and the high-order of Timer A (TAH).
Timer A has the timer A latch to retain the reload value. The value
of timer A latch is set to Timer A at the timing shown below.
• When Timer A undeflows.
• When an active edge is input from CNTR1 pin (valid only when
period measurement mode and pulse width HL continuously measurement mode).
When writing to both the low-order of Timer A (TAL) and the highorder of Timer A (TAH) is executed, the value is written to both the
timer A latch and Timer A.
When reading from the low-order of Timer A (TAL) and the high-order of Timer A (TAH) is executed, the following values are read out
according to the operating mode.
• In timer mode, event counter mode:
The count value of Timer A is read out.
• In period measurement mode, pulse width HL continuously measurement mode:
The measured value is read out.
●Timer 1
Timer 1 is an 8-bit timer and counts the prescaler output.
When Timer 1 underflows, the timer 1 interrupt request bit is set to
“1”.
Prescaler 1 is an 8-bit prescaler and counts the signal selected by
the timer 1 count source selection bit.
Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows. The value of timer 1 latch is set to Timer 1 when Timer
1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is written to both the prescaler 1 latch and Prescaler 1.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is executed, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the signal selected by the timer 1 count source
selection bit. Each time the count clock is input, the contents of
Prescaler 1 is decremented by 1. When the contents of Prescaler
1 reach “00 16”, an underflow occurs at the next count clock, and
the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1
reach “0016”, an underflow occurs at the next count clock, and the
timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer
1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is
1/((n+1)✕(m+1)) provided that the value of Prescaler 1 is n and
the value of Timer 1 is m.
Timer 1 cannot stop counting by software.
Be sure to write to/read out the low-order of Timer A (TAL) and the
high-order of Timer A (TAH) in the following order;
Read
Read the high-order of Timer A (TAH) first, and the low-order of
Timer A (TAL) next and be sure to read out both TAH and TAL.
Write
Write to the low-order of Timer A (TAL) first, and the high-order of
Timer A (TAH) next and be sure to write to both TAL and TAH.
Timer A can be selected in one of 4 operating modes by setting
the timer A mode register.
(1) Timer mode
Timer A counts the selected by the timer A count source selection
bit. Each time the count clock is input, the contents of Timer A is
decremented by 1. When the contents of Timer A reach “000016”,
an underflow occurs at the next count clock, and the timer A latch
is reloaded into Timer A. The division ratio of Timer A is 1/(n+1)
provided that the value of Timer A is n.
(2) Period measurement mode
In the period measurement mode, the pulse period input from the
P00/CNTR1 pin is measured.
CNTR 1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in the timer A
latch is reloaded in Timer A and count continues. The active edge
of CNTR1 pin input signal can be selected from rising or falling by
the CNTR1 active edge switch bit .The count value when trigger
input from CNTR1 pin is accepted is retained until Timer A is read
once.
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7544 Group
(3) Event counter mode
Timer A counts signals input from the P00/CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR 1 pin input signal can be selected from
rising or falling by the CNTR1 active edge switch bit .
b7
b0
Timer A mode register
(TAM : address 001D16, initial value: 0016)
Disable (return “0” when read)
Timer A operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
(4) Pulse width HL continuously measurement mode
In the pulse width HL continuously measurement mode, the pulse
width (“H” and “L” levels) input to the P00/CNTR1 pin is measured.
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
The count value when trigger input from the CNTR 1 pin is accepted is retained until Timer A is read once.
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge period in period
measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR1 interrupt
Timer A can stop counting by setting “1” to the timer A count stop
bit in any mode.
Also, when Timer A underflows, the timer A interrupt request bit is
set to “1”.
Timer A count stop bit
0 : Count start
1 : Count stop
Fig. 22 Structure of timer A mode register
Note on Timer A is described below;
■ Note on Timer A
CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit.
When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit is set to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR 1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
b7
b0
Timer count source set register 2
(TCSS2 : address 002F16, initial value: 0016)
Timer 1 count source selection bits
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : On-chip oscillator output
1 1 : Disable
Timer A count source selection bits
b3 b2
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : On-chip oscillator output
1 1 : Disable
Disable (return “0” when read)
Note : System operates using an on-chip oscillator as a count source
by setting the on-chip oscillator to oscillation enabled by bit 3
of CPUM.
Fig. 23 Timer count source set register 2
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7544 Group
●Timer X
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to “1”.
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows. The value of timer X latch is set to Timer X when
Timer X underflows.
When writing to Prescaler X (PREX) and Timer X (TX) is executed, writing to “latch only” or “latch and prescaler (timer)” can
be selected by the setting value of the timer X write control bit.
When reading from Prescaler X (PREX) and Timer X (TX) is executed, each count value is read out.
Timer X can be selected in one of 4 operating modes by setting
the timer X operating mode bits of the timer X mode register.
(1) Timer mode
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach “0016”, an underflow occurs at the next count
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X
reach “0016”, an underflow occurs at the next count clock, and the
timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1)✕(m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR0 pin.
The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is “0”,
the output of CNTR0 pin is started at “H” level. When this bit is “1”,
the output is started at “L” level.
Also, the inverted waveform of pulse output from CNTR0 pin can
be output from TXOUT pin by setting “1” to the P03/TXOUT output
valid bit.
When using a timer in this mode, set the port P14 and P03 direction registers to output mode.
(3) Event counter mode
The timer A counts signals input from the P14/CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR 0 pin input signal can be selected from
rising or falling by the CNTR0 active edge switch bit .
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(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR0 pin is measured.
The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR0 pin is “H”. The count is stopped while the
pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR0 pin is “L”. The count
is stopped while the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
■ Note on Timer X
CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR 0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
7544 Group
b7
b0
Timer X mode register
(TXM : address 002B16, initial value: 0016)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X count stop bit
0 : Count start
1 : Count stop
P03/TXOUT output valid bit
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR0 output)
Disable (return “0” when read)
Fig. 24 Structure of timer X mode register
b7
b0
Timer count source set register 1
(TCSS1 : address 002E16, initial value: 0016)
Timer X count source selection bits
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : f(XIN) (Note)
1 1 : Not available
Disable (return “0” when read)
Note : f(XIN) can be used as timer X count source when using
a ceramic resonator or on-chip oscillator.
Do not use it at RC oscillation.
Fig. 25 Timer count source set register 1
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7544 Group
Data bus
Prescaler 1 latch (8)
f(XIN)/16
f(XIN)/2
On-chip oscillator clock RING
Timer 1 latch (8)
Prescaler 1 (8)
Timer 1 interrupt
request bit
Timer 1 (8)
Pulse width HL
continuously
measurement mode
Rising edge detected
Period measurement mode
Falling edge detected
CNTR1 active
edge switch bit
P00/CNTR1
Data bus
Timer A (low-order) latch (8)
Timer A (low-order) (8)
f(XIN)/16
f(XIN)/2
On-chip oscillator clock RING
Timer A operation mode bit
Timer A (high-order) latch (8)
Timer A interrupt
request bit
Timer A (high-order) (8)
Timer A count
stop bit
Fig. 26 Block diagram of timer 1 and timer A
Data bus
f(XIN)/16
f(XIN)/2
f(XIN)
Timer X count
source selection bits
CNTR0 active
edge switch bit
“0”
P14/CNTR0
Prescaler X latch (8)
Timer X latch (8)
Prescaler X (8)
Timer X (8)
Pulse width
Timer mode
measurement Pulse output
mode
mode
Event
counter
mode
Timer X
interrupt
request bit
Timer X count stop bit
CNTR0
interrupt
request bit
“1”
CNTR0 active “1”
edge switch bit
Q
Q
Port P14
latch
Port P14 direction
register
Pulse output mode
P03/TXOUT
Port P03 latch
P03/TXOUT output valid
Port P03
direction
register
Fig. 27 Block diagram of timer X
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“0”
Toggle flip-flop T
R
Timer X write control bit
Writing to timer X latch
Pulse output mode
7544 Group
Serial I/O
●Serial I/O
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register (bit 6)
to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Data bus
Serial I/O control register
Address 001816
Receive buffer register
Receive shift register
P10/RXD
Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Shift clock
Clock control circuit
P12/SCLK
XIN
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
1/4
Address 001C16
BRG count source selection bit
1/4
P13/SRDY
F/F
Clock control circuit
Falling-edge detector
Shift clock
P11/TXD
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O status register
Data bus
Fig. 28 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY
Write pulse to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 29 Operation of clock synchronous serial I/O function
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7544 Group
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
Data bus
Address 001816
Serial I/O control register Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
OE
Character length selection bit
P10/RXD
ST detector
7 bits
Receive shift register
1/16
8 bits
PE FE
UART control register
Address 001B16
SP detector
Clock control circuit
Serial I/O synchronous clock selection bit
P12/SCLK
XIN
BRG count source selection bit Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
Transmit shift completion flag (TSC)
1/16
P11/TXD
Transmit shift register
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Serial I/O status register Address 001916
Transmit buffer register
Address 001816
Data bus
Fig. 30 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TSC=1 ✽
TBE=1
ST
D0
D1
SP
ST
D0
Receive buffer read
signal
SP
D1
✽
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Generated at 2nd bit in 2-stop-bit mode
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 31 Operation of UART serial I/O function
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7544 Group
[Transmit buffer register/receive buffer register (TB/RB)]
001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O status register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit of the serial I/O control register
has been set to “1”, the transmit shift completion flag (bit 2) and
the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O control register (SIOCON)] 001A16
The serial I/O control register consists of eight control bits for the
serial I/O function.
[UART control register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P11/TXD pin.
[Baud rate generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
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■ Notes on serial I/O
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission enabled, take the following sequence.
➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O is enabled.
The functions of P12 and P13 are switched with the setting values
of a serial I/O mode selection bit and a serial I/O synchronous
clock selection bit as follows.
(1) Serial I/O mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY output pin.
(2) Serial I/O mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
7544 Group
b7
b0
Serial I/O status register
(SIOSTS : address 0019 16, initial value: 00 16)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Disable (returns “1” when read)
b7
b0
UART control register
(UARTCON : address 001B 16, initial value: E0 16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P1 1/T XD 1 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Disable (return “1” when read)
Fig. 32 Structure of serial I/O-related registers
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b7
b0
Serial I/O control register
(SIOCON : address 001A 16, initial value: 00 16)
BRG count source selection bit (CSS)
0: f(X IN)
1: f(X IN)/4
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
S RDY output enable bit (SRDY)
0: P1 3 pin operates as ordinary I/O pin
1: P1 3 pin operates as S RDY output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P1 0 to P1 3 operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P1 0 to P1 3 operate as serial I/O pins)
7544 Group
A/D Converter
b7
b0
A/D control register
(ADCON : address 003416, initial value: 1016)
The functional blocks of the A/D converter are described below.
Analog input pin selection bits
000 : P20/AN0
001 : P21/AN1
010 : P22/AN2
011 : P23/AN3
100 : P24/AN4
101 : P25/AN5
110 : Disable
111 : Disable
Disable (returns “0” when read)
[A/D conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an A/
D conversion.
[A/D control register] ADCON
The A/D control register controls the A/D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at “0” during A/D conversion,
and changes to “1” at completion of A/D conversion.
A/D conversion is started by setting this bit to “0”.
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Disable (returns “0” when read)
Fig. 33 Structure of A/D control register
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
■ Notes on A/D converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is 500 kHz or more during A/D conversion.
As for AD translation accuracy, on the following operating conditions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when V REF voltage is set up lower than Vcc
voltage, accuracy may become low rather than the case
where VREF voltage and Vcc voltage are set up to the same
value..
(2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the
low temperature may become extremely low compared with
that at room temperature. When the system would be used at
low temperature, the use at V REF=3.0 V or more is recommended.
[Channel selector]
The channel selector selects one of ports P25/AN 5 to P20/AN 0,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A/D
conversion register. When A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”. Because the comparator is constructed
linked to a capacitor, set f(XIN) to 500 kHz or more during A/D conversion.
Data bus
b7
b0
A/D control register
(Address 003416)
3
A/D interrupt request
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
Channel selector
A/D control circuit
P20/AN0
Comparator
A/D conversion register (low-order)
10
Resistor ladder
VREF
Fig. 34 Block diagram of A/D converter
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VSS
(Address 003516)
7544 Group
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control register (address 0039 16) is not set after reset. Writing an optional
value to the watchdog timer control register (address 0039 16)
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register
(address 003916) can be set before an underflow occurs.
When the watchdog timer control register (address 0039 16) is
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction disable bit and watchdog timer H count source selection bit are read.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow signal. The detection time is 131.072 ms at f(XIN)=8 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 512 µs at f(XIN)=8 MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can
be disabled by bit 6 of the watchdog timer control register (address 003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (address 0039 16 ), the watchdog timer H is set to “FF 16” and the
watchdog timer L is set to “FF16”.
Data bus
Write “FF16” to the
watchdog timer
control register
Watchdog timer L (8)
1/16
XIN
“0”
“1”
Watchdog timer H (8)
Write "FF16" to the
watchdog timer
control register
Watchdog timer H count
source selection bit
STP Instruction disable bit
STP Instruction
Reset
circuit
RESET
Internal
reset
Fig. 35 Block diagram of watchdog timer
b7
b0
Watchdog timer control register
(WDTCON: address 003916, initial value: 3F16)
Watchdog timer H (read only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16
Fig. 36 Structure of watchdog timer control register
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7544 Group
Reset Circuit
Poweron
The microcomputer is put into a reset status by holding the RESET pin at the “L” level for 2 µs or more when the power source
voltage is 4.5 to 5.5 V and XIN is in stable oscillation. ______
After that, this reset status is released by returning the RESET pin
to the “H” level. The program starts from the address having the
contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address.
In the case of f(φ) ≤ 8 MHz, the reset input voltage must be 0.9 V
or less when the power source voltage passes 4.5 V.
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2 VCC
Note : Reset release voltage Vcc 4.5V
RESET
VCC
Power source
voltage
detection circuit
Fig. 37 Example of reset circuit
Clock from
on-chip oscillator
RING
φ
RESET
RESETOUT
SYNC
Address
?
Data
?
?
8-13 clock cycles
Fig. 38 Timing diagram at reset
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?
?
?
?
FFFC
?
?
?
FFFD
ADL
ADH,ADL
ADH
Reset address from the
vector table
Notes 1 : An on-chip oscillator applies about RING•2 MHz, φ•250 kHz frequency clock
at average of Vcc = 5 V.
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET.
7544 Group
Address
Register contents
0016
(1)
Port P0 direction register
000116
(2)
Port P1 direction register
000316
X
X
X
0
0
0
0
0
(3)
Port P2 direction register
000516
X
X
0
0
0
0
0
0
(4)
Port P3 direction register
000716
0
X
X
0
0
0
0
0
(5)
Pull-up control register
001616
0016
(6)
Port P1P3 control register
001716
0016
(7)
Serial I/O status register
001916
0
0
0
(8)
Serial I/O control register
001A16
(9)
UART control registe
001B16
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
X
X
1
0
0
0
0
0016
1
1
1
0
0
(10) Timer A mode register
001D16
0016
(11) Timer A (low-order)
001E16
FF16
(12) Timer A (high-order)
001F16
FF16
(13) Prescaler 1
002816
FF16
(14) Timer 1
002916
(15) Timer X mode register
002B16
0016
(16) Prescaler X
002C16
FF16
(17) Timer X
002D16
FF16
(18) Timer count source set register 1
002E16
0016
(19) Timer count source set register 2
002F16
0016
(20) A/D control register
003416
(21) MISRG
003816
(22) Watchdog timer control register
003916
(23) Interrupt edge selection register
003A16
(24) CPU mode register
003B16
(25) Interrupt request register 1
003C16
0016
(26) Interrupt request register 2
003D16
0016
(27) Interrupt control register 1
003E16
0016
(28) Interrupt control register 2
003F16
0016
(29) Processor status register
(30) Program counter
(PS)
0
0
0
0
0
0
0
1
0
0
0016
0
0
1
1
1
0016
1
X
0
X
0
X
0
X
0
X
(PCH)
Contents of address FFFD16
(PCL)
Contents of address FFFC16
X : Undefined
The content of other registers is undefined when the microcomputer is reset.
The initial values must be surely set bifore you use it.
Fig. 39 Internal status of microcomputer at reset
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7544 Group
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed
by connecting a resistor and a capacitor.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values.
M37544
XIN
(1) On-chip oscillator operation
When the MCU operates by the on-chip oscillator for the main
clock, connect XIN pin to VCC and leave XOUT pin open.
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
(2) Ceramic resonator and quartz-crystal oscillator
When the ceramic resonator and quartz-crystal oscillator is used
for the main clock, connect the ceramic/quartz-crystal oscillator
and the external circuit to pins X IN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT.
(3) RC oscillation
When the RC oscillation is used for the main clock, connect the
XIN pin and XOUT pin to the external circuit of resistor R and the
capacitor C at the shortest distance.
The frequency is affected by a capacitor, a resistor and a microcomputer.
So, set the constants within the range of the frequency limits.
Note: The clock frequency of the
on-chip oscillator depends
on the supply voltage and
the operation temperature
range.
Be careful that variable freXOUT
quencies and obtain the
sufficient margin.
Open
Fig. 40 Processing of XIN and XOUT pins at on-chip oscillator operation
Note: Externally connect a
damping resistor Rd
depending on the oscillation frequency.
(A feedback resistor is
built-in.)
Use the resonator
manufacturer’s recommended value because
constants such as capacitance depend on
the resonator.
M37544
XIN
XOUT
Rd
COUT
CIN
Fig. 41 External circuit of ceramic resonator and quartz-crystal
oscillator
(4) External clock
When the external signal clock is used for the main clock, connect
the XIN pin to the clock source and leave XOUT pin open.
Note:
M37544
XIN
XOUT
R
C
Connect the external
circuit of resistor R
and the capacitor C at
the shortest distance.
The frequency is affected by a capacitor,
a resistor and a microcomputer.
So, set the constants
within the range of the
frequency limits.
Fig. 42 External circuit of RC oscillation
M37544
XIN
External oscillation
circuit
VCC
VSS
Fig. 43 External clock input circuit
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REJ03B0012-0104Z
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XOUT
Open
7544 Group
(1) Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the XIN oscillator stops. At this time, timer 1 is set
to “0116” and prescaler 1 is set to “FF16” when the oscillation stabilization time set bit after release of the STP instruction is “0”. On
the other hand, timer 1 and prescaler 1 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used. Single selected by
the timer 1 count source selection bit is connected to the input of
prescaler 1. When an external interrupt is accepted, oscillation is
restarted but the internal clock φ remains at “H” until timer 1
underflows. As soon as timer 1 underflows, the internal clock φ is
supplied. This is because when a ceramic/quartz-crystal oscillator
is used, some time is required until a start of oscillation. In case
oscillation is restarted______
by reset, no wait time is generated. So apply an “L” level to the RESET pin while oscillation becomes stable.
Also, the STP instruction cannot be used while CPU is operating
by an on-chip oscillator.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to “1” before the STP or WIT instruction is executed.
■ Notes on clock generating circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Switch of ceramic/quartz-crystal and RC oscillations
After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic/quartz-crystal oscillation or an RC
oscillation is selected by setting bit 5 of the CPU mode register.
• Double-speed mode
When a ceramic/quartz-crystal oscillation is selected, a doublespeed mode can be used. Do not use it when an RC oscillation is
selected.
• CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37544RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
Rev.1.04 2004.06.08
REJ03B0012-0104Z
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• Clock division ratio, XIN oscillation control, on-chip oscillator control
The state transition shown in Fig. 48 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 48.
b7
b0
CPU mode register
(CPUM: address 003B16, initial value: 8016)
Processor mode bits (Note 1)
b1 b0
0 0 Single-chip mode
0 1
Not available
1 0
1 1
Stack page selection bit
0 : 0 page
1 : 1 page
On-chip oscillator oscillation control bit
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
XIN oscillation control bit
0 : Ceramic/quartz-crystal or RC oscillation enabled
1 : Ceramic/quartz-crystal or RC oscillation stop
Oscillation mode selection bit (Note 1)
0 : Ceramic/quartz-crystal oscillation
1 : RC oscillation
Clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(XIN)/2 (High-speed mode)
0 1 : f(φ) = f(XIN)/8 (Middle-speed mode)
1 0 : applied from on-chip oscillator
1 1 : f(φ) = f(XIN) (Double-speed mode)(Note 2)
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37544RSS”.)
2: These bits are used only when a ceramic/quartz-crystal oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 44 Structure of CPU mode register
7544 Group
● Oscillation stop detection circuit
The oscillation stop detection circuit is used for reset occurrence
when a ceramic resonator or an oscillation circuit stops by disconnection. When internal reset occurs, reset because of oscillation
stop can be detected by setting “1” to the oscillation stop detection
status bit.
Also, when using the oscillation stop detection circuit, an on-chip
oscillator is required.
Figure 48 shows the state transition.
The oscillation stop detection status bit retains “1”, not initialized,
when the oscillation stop reset occurs. The oscillation stop detection status bit is initialized to “0” when the external reset occurs.
Accordingly, reset by oscillation stop can be confirmed by using
this bit.
■ Notes on Oscillation Stop Detection Circuit
• Oscillation stop detection status bit is initialized by the following
operation.
(1) External reset
(2) Write “0” data to the ceramic or RC oscillation stop detection
function active bit.
• The oscillation stop detection circuit is not included in the emulator MCU “M37544RSS”.
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 37 of 66
b7
b0
MISRG(address 003816, initial value: 0016)
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “0116” in timer1, and “FF16”
in prescaler 1 automatically
1: Not set automatically
Ceramic/quartz-crystal or RC oscillation
stop detection function active bit
0: Detection function inactive
1: Detection function active
Reserved bits (return “0” when read)
(Do not write “1” to these bits)
Disable (return “0” when read)
Oscillation stop detection status bit
0: Oscillation stop not detected
1: Oscillation stop detected
Fig. 45 Structure of MISRG
7544 Group
XIN
XOUT
Rf
Clock division ratio selection bit
Middle-, high-, low-speed mode
1/2
1/4
1/2
On-chip oscillator mode
Timer 1
Prescaler 1
Clock division
ratio selection bit
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
Double-speed mode
RING
On-chip oscillator
1/8
On-chip oscillator mode
Q
S
Q S
R
WIT
instruction
STP instruction
S
Q
R
RESET
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Fig. 46 Block diagram of internal clock generating circuit (for ceramic/quartz-crystal resonator)
XOUT
XIN
Clock division ratio selection bit
Middle-, high-, low-speed mode
1/2
1/4
1/2
On-chip
oscillator
mode
Delay
Prescaler 1
Timer 1
Clock division
ratio selection bit
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
Double-speed mode
RING
On-chip oscillator
1/8
On-chip oscillator mode
S
Q S
R
STP instruction
WIT
instruction
Q
R
Reset
Interrupt disable flag l
Interrupt request
Fig. 47 Block diagram of internal clock generating circuit (for RC oscillation)
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Q
S
RESET
R
STP instruction
7544 Group
Stop mode
Wait mode
Interrupt
WIT
instruction
Interrupt
STP
instruction
State 1
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator stop
Interrupt
WIT
instruction
f(XIN) (Note 1)
f(XIN) oscillation enabled
State 3
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enabled
On-chip oscillator enabled
State 2
CPUM3←02 Operation clock source:
CPUM3¨12
MISRG1¨12
CPUM76¨102
CPUM76¨002
012
112
(Note 2)
MISRG1←02
MISRG1¨12
State 2’
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator enabled
CPUM76¨102
MISRG1¨02
State 3’
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
CPUM76←002
012 On-chip oscillator enabled
112
(Note 2)
Oscillation stop detection circuit valid
Reset released
Reset state
State 4
CPUM4←12 Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation stop
CPUM4¨02
On-chip oscillator enabled
Notes on switch of clock
(1) In operation clock source = f(XIN), the following can be
selected for the CPU clock division ratio.
● f(XIN)/2 (high-speed mode)
● f(XIN)/8 (middle-speed mode)
● f(XIN) (double-speed mode, only at a ceramic/quartz-crystal
oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing XIN oscillation.
(3) In operation clock source = on-chip oscillator, the middlespeed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2 → state 3 → state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
• CPUM76 → 102 (State 2 → state 3)
• NOP instruction
• CPUM4 → 12 (State 3 → state 4)
Double-speed mode at on-chip oscillator: NOP ✕ 3
High-speed mode at on-chip oscillator: NOP ✕ 1
Middle-speed mode at on-chip oscillator: NOP 0
Fig. 48 State transition
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7544 Group
NOTES ON PROGRAMMING
State transition
Processor Status Register
Do not stop the clock selected as the operation clock because of
setting of CM3, 4.
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular,
it is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed
contents, execute one instruction before executing the BBC or
BBS instruction.
Decimal Calculations
• For calculations in decimal notation, set the decimal mode flag
D to “1”, then execute the ADC instruction or SBC instruction. In
this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction
or SBC instruction.
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
Ports
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using
direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA instruction, etc.
A/D Conversion
Do not execute the STP instruction during A/D conversion.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles mentioned in the machine-language instruction table.
The frequency of the internal clock φ is the same as that of the XIN
in double-speed mode, twice the X IN cycle in high-speed mode
and 8 times the XIN cycle in middle-speed mode.
CPU Mode Register
The oscillation mode selection bit and processor mode bits can be
rewritten only once after releasing reset. However, after rewriting it
is disable to write any value to the bit. (Emulator MCU is excluded.)
When a ceramic / quartz-crystal oscillation is selected, a doublespeed mode of the clock division ratio selection bits can be used.
Do not use it when an RC oscillation is selected.
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NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF to 0.1 µF is recommended.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1.Mask ROM Order Confirmation Form *
2.Mark Specification Form *
For the mask ROM confirmation and the mark specifications,
refer to the "Renesas Technology Corp." Homepage
(http://www.renesas.com/en/rom).
7544 Group
NOTES ON USE
Countermeasures against noise
1. Shortest wiring length
(1) Package
Select the smallest possible package to make the total wiring
length short.
<Reason>
The wiring length depends on a microcomputer package. Use of a
small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise.
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as
short as possible.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
<Reason>
If noise enters clock I/O pins, clock waveforms may be deformed.
This may cause a program failure or program runaway. Also, if a
potential difference is caused by the noise between the VSS level
of a microcomputer and the VSS level of an oscillator, the correct
clock will not be input in the microcomputer.
Noise
DIP
SDIP
SOP
XIN
XOUT
VSS
QFP
Fig. 49 Selection of packages
Fig. 51 Wiring for clock I/O pins
(4) Wiring to CNVss pin
Connect the CNVss pin to the Vss pin with the shortest possible
wiring.
<Reason>
The processor mode of a microcomputer is influenced by a potential at the CNVss pin. If a potential difference is caused by the
noise between pins CNVss and Vss, the processor mode may become unstable. This may cause a microcomputer malfunction or a
program runaway.
Noise
Noise
Reset
circuit
RESET
VSS
VSS
O.K.
N.G.
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as
short as possible. Especially, connect a capacitor across the
RESET pin and the V SS pin with the shortest possible wiring
(within 20mm).
<Reason>
The width of a pulse input into the RESET pin is determined by the
timing necessary conditions. If noise having a shorter pulse width
than the standard is input to the RESET pin, the reset is released
before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
XIN
XOUT
VSS
CNVSS
CNVSS
VSS
VSS
N.G.
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Fig. 50 Wiring for the RESET pin
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Fig. 52 Wiring for CNVss pin
O.K.
7544 Group
(5) Wiring to VPP pin of One Time PROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest
possible in series and also to the Vss pin. When not connecting
the resistor, make the length of wiring between the VPP pin and
the Vss pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ
resistor is used in the Mask ROM version, the microcomputer operates correctly.
<Reason>
The VPP pin of the One Time PROM is the power source input pin
for the built-in PROM. When programming in the built-in PROM,
the impedance of the VPP pin is low to allow the electric current for
writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data
are read from the built-in PROM, which may cause a program runaway.
3. Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog
signal line which is connected to an analog input pin in series.
Besides, connect the resistor to the microcomputer as close as
possible.
• Connect an approximately 1000 pF capacitor across the Vss pin
and the analog input pin. Besides, connect the capacitor to the
Vss pin as close as possible. Also, connect the capacitor across
the analog input pin and the Vss pin at equal length.
<Reason>
Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are usually output signals from
sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to
an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
Noise
About 5kΩ
CNVSS/VPP
(Note)
Microcomputer
VSS
shortest
distance
Analog
input pin
Thermistor
Fig. 53 Wiring for the VPP pin of the One Time PROM
2. Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 0.1 µF bypass capacitor across the VSS
line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
VCC
VCC
VSS
VSS
N.G.
O.K.
Fig. 54 Bypass capacitor across the VSS line and the VCC line
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REJ03B0012-0104Z
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N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 55 Analog signal line and a resistor and a capacitor
• The analog input pin is connected to the capacitor of a voltage
comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D
conversion when the analog signal source of high-impedance is
connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an
analog signal source, or add the smoothing capacitor to an analog input pin.
7544 Group
4. Oscillator concerns
So that the product obtains the stabilized operation clock on the
user system and its condition, contact the resonator manufacturer
and select the resonator and oscillation circuit constants.
Be careful especially when range of voltage and temperature is
wide.
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the tolerance of current value flows.
<Reason>
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise occurs
because of mutual inductance.
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away
from signal lines where potential levels change frequently. Also, do
not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
<Reason>
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge
or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or
a program runaway.
➀ Keeping oscillator away from large current signal lines
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
➁ Installing oscillator away from signal lines where potential levels change frequently
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig. 56 Wiring for a large current signal line/Writing of signal
lines where potential levels change frequently
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(3) Oscillator protection using Vss pattern
As for a two-sided printed circuit board, print a Vss pattern on the
underside (soldering side) of the position (on the component side)
where an oscillator is mounted.
Connect the Vss pattern to the microcomputer Vss pin with the
shortest possible wiring. Besides, separate this Vss pattern from
other Vss patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 57 Vss pattern on the underside of an oscillator
7544 Group
5. Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for
checking whether input levels are equal or not.
• As for an output port, since the output data may reverse because
of noise, rewrite data to its port latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at
fixed periods.
Note: When a direction register is set for input port again at fixed
periods, a several-nanosecond short pulse may be output
from this port. If this is undesirable, connect a capacitor to
this port to remove the noise pulse.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer
(SWDT) and writes the initial value N in the SWDT once at each
execution of the main routine. The initial value N should satisfy
the following condition:
N+1 ≥ (Counts of interrupt processing executed in each main
routine)
As the main routine execution cycle may change because of an
interrupt processing or others, the initial value N should have a
margin.
• Watches the operation of the interrupt processing routine by
comparing the SWDT contents with counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for
recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the
SWDT contents are reset to the initial value N at almost fixed
cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to
branch to the program initialization routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but
continued to decrement and if they reach 0 or less.
Fig. 58 Setup for I/O ports
6. Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can
be detected by a software watchdog timer and the microcomputer
can be reset to normal operation. This is equal to or more effective
than program runaway detection by a hardware watchdog timer.
The following shows an example of a watchdog timer provided by
software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing
routine and the interrupt processing routine detects errors of the
main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
≤0
(SWDT)
=N?
N
Interrupt processing
routine errors
>0
RTI
Return
Main routine
errors
Fig. 59 Watchdog timer by software
7. Electric Characteristic Differences Between Mask ROM and
One Time PROM Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between the mask ROM and
One Time PROM version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with the One Time
PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
Rev.1.04 2004.06.08
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7544 Group
PROM Mode
There are three operation modes in PROM Mode : Read, Program
and Program-Verify. Three commands are defined to enable each
mode respectively.
M37544G2SP/GP (referred to as “the MCU”) has a PROM Mode
as well as the normal operation mode. PROM Mode enables an
external device (referred to as “Programmer”) to read and program the built-in EPROM via a minimum number of serial I/O pins
by sending commands to control the MCU.
The format of the serial I/O is : clock synchronous and LSB-datafirst.
To enable PROM Mode, use the pin connection shown in Figure
60 to 61 and apply power (VCC). Then execute the new OTP entry operation, called “Mad Dog Entry”.
ESCLK
Fig. 60 “Mad Dog Entry” Pin Diagram (32P4B)
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1
32
2
31
3
30
4
29
5
28
6
7
8
9
10
11
12
M37544G2SP
RESETB
VPP
VCC
XIN
XOUT
VSS
P12/SCLK
P13/SRDY
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
XIN
XOUT
VSS
27
26
25
24
23
22
21
13
20
14
19
15
18
16
17
P11/TXD
P10/RXD
P07(LED7)
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
P37(LED13)/INT0
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
ESDA
ESPGMB
18
17
20
19
22
25
16
26
15
27
14
28
29
13
M37544G2GP
12
8
7
RESETB
VPP
VCC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
6
9
5
10
32
3
11
31
4
30
1
P07(LED7)
P10/RXD
P11/TXD
P12/SCLK
P13/SRDY
P14/CNTR0
P20/AN0
P21/AN1
2
ESPGMB
ESDA
ESCLK
21
24
23
P06(LED6)
P05(LED5)
P04(LED4)
P03(LED3)/TXOUT
P02(LED2)
P01(LED1)
P00(LED0)/CNTR1
P37(LED13)/INT0
7544 Group
Fig. 61 “Mad Dog Entry” Pin Diagram (32P6U-A)
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 46 of 66
P34(LED12)/INT1
P33(LED11)
P32(LED10)
P31(LED9)
P30(LED8)
VSS
VSS
XOUT
XOUT
XIN
XIN
7544 Group
Precaution for Handling One-Time-Programmable
Devices
Our company ships one-time-programmable version MCUs (OneTime PROM MCU) without being screened by the PROM writing
test.
To ensure the reliability of the MCU, We recommend that the user
performs the program and test procedure shown in Figure 62
before using the MCU.
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
programmer
Functional check in
target device
Caution: The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 62 Programming and testing of One Time PROM
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 47 of 66
7544 Group
ROM Code Access Protection
We would like to support a simple ROM code protection function
that prevents a party other than the ROM-code owner to read and
reprogram the builit-in PROM code of the MCU.
The MCU has 7 bytes of dedicated ROM spaces in address
0xFFD4 to 0xFFDA, as an ID-code (referred to as “the ID-code”)
enabling a Programmer to verify with the input ID-code and
validate further operations.
Expected Programmer ID-Code Verification
Function
First, Programmer must check the ID-code of the MCU.
If the ID-code is still in blank, Programmer enables all operations,
Read, Program, and Program-Verify.
When Programmer programs the MCU, Programmer also
programs the given ID-code as well as the actual firmware.
If the ID-code is not blank, Programmer verifies it with the input
ID-code.
When the ID-codes don't match, Programmer will reject all further
operations.
If they match, Programmer perform operations according to the
given command.
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 48 of 66
Address
FFD416
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
ID1
ID2
ID3
ID4
ID5
ID6
ID7
Fig. 63 ROM-Code Protection ID Location
7544 Group
ELECTRICAL CHARACTERISTICS
1.7544Group
Applied to: M37544M2-XXXSP/GP/HP, M37544G2SP/GP/HP(Note)
Note: M37544G2HP: Only ES version (MP: no plan)
Absolute Maximum Ratings
Table 9 Absolute maximum ratings
Symbol
VCC
VI
Power source voltage
Parameter
VI
VI
P00–P07, P10–P14, P20–P25, P30–P34,P37, VREF
______
Input voltage RESET, XIN
Input voltage CNVSS (Note)
VO
Output voltage
Conditions
Input voltage
All voltages are
based on VSS.
Output transistors
are cut off.
–0.3 to 6.5
–0.3 to VCC + 0.3
Ratings
Unit
V
V
–0.3 to VCC + 0.3
V
–0.3 to 7.0
V
–0.3 to VCC + 0.3
V
P00–P07, P10–P14, P20–P25, P30–P34,P37, XOUT
Ta = 25°C
Pd
Power dissipation
200
mW
Topr
Operating temperature
–20 to 85
°C
Tstg
Storage temperature
–40 to 125
°C
Notes : It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version.
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 49 of 66
7544 Group
Recommended Operating Conditions
Table 10 Recommended operating conditions (1) (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
Parameter
Power source voltage (ceramic)
Power source voltage (RC)
Limits
Unit
Min.
Typ.
Max.
f(XIN) = 8 MHz (Double-speed mode)
4.0
4.5
5.0
5.0
5.5
5.5
V
V
f(XIN) = 4 MHz (High-, Middle-speed mode)
4.0
5.0
5.5
V
f(XIN) = 8 MHz (High-, Middle-speed mode)
VSS
Power source voltage
VREF
Analog reference voltage
VIH
“H” input voltage
VIH
P00–P07, P10–P14, P20–P25, P30–P34, P37
“H” input voltage (TTL input level selected)
V
0
2.0
VCC
V
0.8VCC
VCC
V
2.0
VCC
V
P10, P12, P34, P37
VIH
“H” input voltage
______
RESET, XIN
0.8VCC
VCC
V
VIL
“L” input voltage
0
0.3VCC
V
VIL
P00–P07, P10–P14, P20–P25, P30–P34, P37
“L” input voltage (TTL input level selected)
0
0.8
V
P10, P12, P34, P37
VIL
“L” input voltage
______
RESET, CNVSS
0
0.2VCC
V
VIL
“L” input voltage
0
0.16VCC
V
∑IOH(peak)
XIN
“H” total peak output current (Note)
–80
mA
80
mA
P00–P07, P10–P14, P20–P25, P30–P34, P37
∑IOL(peak)
“L” total peak output current (Note)
P10–P14, P20–P25
∑IOL(peak)
“L” total peak output current (Note)
P00–P07, P30–P34, P37
60
mA
∑IOH(avg)
“H” total average output current (Note)
–40
mA
40
mA
30
mA
P00–P07, P10–P14, P20–P25, P30–P34, P37
∑IOL(avg)
“L” total average output current (Note)
P10–P14, P20–P25
∑IOL(avg)
“L” total average output current (Note)
P00–P07, P30–P34, P37
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an
average value measured over 100 ms. The total peak current is the peak value of all the currents.
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 50 of 66
7544 Group
Recommended Operating Conditions (continued)
Table 11 Recommended operating conditions (2) (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
IOH(peak)
“H” peak output current (Note 1)
P00–P07, P10–P14, P20–P25, P30–P34, P37
IOL(peak)
“L” peak output current (Note 1)
Min.
Typ.
Max.
–10
Unit
mA
10
mA
30
mA
P10–P14, P20–P25
IOL(peak)
“L” peak output current (Note 1)
P00–P07, P30–P34, P37
IOH(avg)
“H” average output current (Note 2)
P00–P07, P10–P14, P20–P25, P30–P34, P37
–5
mA
IOL(avg)
“L” average output current (Note 2)
5
mA
15
mA
8
MHz
8
MHz
4
MHz
P10–P14, P20–P25
IOL(avg)
“L” average output current (Note 2)
P00–P07, P30–P34, P37
f(XIN)
Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50 %.
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 51 of 66
7544 Group
Electrical Characteristics
Table 12 Electrical characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VOL
Parameter
Test conditions
Min.
Typ.
Max.
Unit
“H” output voltage
IOH = –5 mA
P00–P07, P10–P14, P20–P25, P30–P34, P37 (Note 1) VCC = 4.0 to 5.5 V
VCC–1.5
V
IOH = –1.0 mA
VCC = 4.0 to 5.5 V
VCC–1.0
V
“L” output voltage
P10–P14, P20–P25
“L” output voltage
P00–P07, P30–P34, P37
IOL = 5 mA
VCC = 4.0 to 5.5 V
1.5
V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
0.3
V
IOL = 1.0 mA
VCC = 4.0 to 5.5 V
1.0
V
IOL = 15 mA
VCC = 4.0 to 5.5 V
2.0
V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
0.3
V
IOL = 10 mA
VCC = 4.0 to 5.5 V
1.0
V
VT+–VT–
Hysteresis
CNTR0, CNTR1, INT0, INT1 (Note 2)
P00–P07 (Note 3)
0.4
V
VT+–VT–
Hysteresis
RXD, SCLK (Note 2)
0.5
V
VT+–VT–
Hysteresis
______
RESET
0.9
V
IIH
“H” input current
P00–P07, P10–P14, P20–P25, P30–P34, P37
VI = VCC
(Pin floating. Pull up
transistors “off”)
5.0
µA
IIH
“H”
input current
______
RESET
VI = VCC
5.0
µA
IIH
“H” input current
XIN
VI = VCC
IIL
“L” input current
P00–P07, P10–P14, P20–P25, P30–P34, P37
VI = VSS
(Pin floating. Pull up
transistors “off”)
–5.0
µA
IIL
“L” input current
______
RESET, CNVSS
VI = VSS
–5.0
µA
IIL
“L” input current
XIN
VI = VSS
–4.0
IIL
“L” input current
P00–P07, P30–P34, P37
VI = VSS
(Pull up transistors “on”)
–0.2
–0.5
VRAM
RAM hold voltage
When clock stopped
5.5
V
ROSC
On-chip oscillator oscillation frequency
VCC = 5.0 V, Ta = 25 °C
1000
2000
3000
kHz
DOSC
Oscillation stop detection circuit detection frequency
VCC = 5.0 V, Ta = 25 °C
62.5
125
187.5
kHz
2.0
Notes 1: P11 is measured when the P11/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: RXD, SCLK, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).
3: It is available only when operating key-on wake up.
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 52 of 66
µA
4.0
µA
mA
7544 Group
Electrical Characteristics (continued)
Table 13 Electrical characteristics (2) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ICC
Parameter
Power source
current
Rev.1.04 2004.06.08
REJ03B0012-0104Z
Test conditions
Min.
Unit
Typ.
Max.
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
3.3
8.0
mA
Double-speed mode, f(XIN) = 8 MHz
Output transistors “off”
4.8
10.0
mA
Middle-speed mode, f(XIN) = 8 MHz
Output transistors “off”
1.8
5.0
mA
On-chip oscillator operation mode, VCC = 5 V
Output transistors “off”
250
900
µA
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
1.3
3.2
mA
On-chip oscillator operation mode(in WIT state), VCC = 5V
functions except timer 1 disabled,
Output transistors “off”
140
450
µA
Increment when A/D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
0.45
All oscillation stopped
(in STP state)
Output transistors “off”
0.1
page 53 of 66
Ta = 25 °C
Ta = 85 °C
mA
1.0
µA
10.0
µA
7544 Group
A/D Converter Characteristics
Table 14 A/D Converter characteristics (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
—
Resolution
ABS
Absolute accuracy
(quantification error excluded)
tCONV
Conversion time
RLADDER
Ladder resistor
IVREF
Reference power source
VREF = 5.0 V
50
135
200
input current
VREF = 3.0 V
30
80
120
II(AD)
Ta = –20 to 85 °C, Vcc = VREF
8
Bits
±3
LSB
109
tc(XIN)
37
A/D port input current
Unit
kΩ
5.0
µA
µA
Note: As for AD translation accuracy, on the following operating conditions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage,
accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value..
(2) When VREF voltage is less than [ 3.0V ], the accuracy at the time of low temperature may become extremely low compared with
the time of room temperature. The use beyond VREF=3.0V is recommended in the system the use by the side of low temperature
is assumed to be.
Timing Requirements
Table 15 Timing requirements (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
Limits
Symbol
______
tW(RESET)
Reset input “L” pulse width
Min.
2
tC(XIN)
External clock input cycle time
125
ns
tWH(XIN)
External clock input “H” pulse width
50
ns
tWL(XIN)
External clock input “L” pulse width
50
ns
tC(CNTR0)
CNTR0 input cycle time
200
ns
tWH(CNTR0)
CNTR0, INT0, INT1, input “H” pulse width
80
ns
tWL(CNTR0)
CNTR0, INT0, INT1, input “L” pulse width
80
ns
Typ.
Max.
Unit
µs
tC(CNTR1)
CNTR1 input cycle time
2000
ns
tWH(CNTR1)
CNTR1 input “H” pulse width
800
ns
tWL(CNTR1)
CNTR1 input “L” pulse width
800
ns
tC(SCLK)
Serial I/O clock input cycle time (Note)
800
ns
tWH(SCLK)
Serial I/O clock input “H” pulse width (Note)
370
ns
tWL(SCLK)
Serial I/O clock input “L” pulse width (Note)
370
ns
tsu(RxD–SCLK)
Serial I/O input set up time
220
ns
th(SCLK–RxD)
Serial I/O input hold time
100
ns
Note: In this time, bit 6 of the serial I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 54 of 66
7544 Group
Switching Characteristics
Table 16 Switching characteristics (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
tWH(SCLK)
Serial I/O clock output “H” pulse width
tC(SCLK)/2–30
ns
tWL(SCLK)
Serial I/O clock output “L” pulse width
tC(SCLK)/2–30
ns
td(SCLK–TxD)
Serial I/O output delay time
tv(SCLK–TxD)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
30
ns
tf(SCLK)
Serial I/O clock output falling time
30
ns
tr(CMOS)
CMOS output rising time (Note)
10
30
ns
tf(CMOS)
CMOS output falling time (Note)
10
30
ns
Note : Pin XOUT is excluded.
Measured
output pin
100 pF
///
CMOS output
Fig. 64 Switching characteristics measurement circuit diagram
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 55 of 66
140
–30
ns
ns
7544 Group
tC(CNTR0)
tWL(CNTR0)
tWH(CNTR0)
CNTR0
0.8VCC
0.2VCC
tC(CNTR1)
tWL(CNTR1)
tWH(CNTR1)
0.8VCC
CNTR1
0.2VCC
tWL(CNTR0)
tWH(CNTR0)
INT0, INT1
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(SCLK)
tf
SCLK
tWL(SCLK)
tsu(RxD-SCLK)
td(SCLK-TxD)
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 56 of 66
th(SCLK-RxD)
0.8VCC
0.2VCC
RXD (at receive)
Fig. 65 Timing chart
tWH(SCLK)
0.8VCC
0.2VCC
TXD (at transmit)
tr
tv(SCLK-TxD)
7544 Group
PACKAGE OUTLINE
Recommended
32P4B
EIAJ Package Code
SDIP32-P-400-1.78
Plastic 32pin 400mil SDIP
Weight(g)
2.2
Lead Material
Alloy 42/Cu Alloy
17
1
16
E
32
e1
c
JEDEC Code
–
D
Dimension in Millimeters
Min
Nom
Max
–
–
5.08
0.51
–
–
–
3.8
–
0.35
0.45
0.55
0.9
1.0
1.3
0.63
0.73
1.03
0.22
0.27
0.34
27.8
28.0
28.2
8.75
8.9
9.05
–
1.778
–
–
10.16
–
3.0
–
–
0°
–
15°
L
A1
A
A2
Symbol
e
b1
b
b2
SEATING PLANE
32P6U-A
Recommended
Plastic 32pin 7✕7mm body LQFP
Weight(g)
JEDEC Code
–
Lead Material
Cu Alloy
MD
b2
HD
D
32
ME
e
EIAJ Package Code
LQFP32-P-0707-0.80
A
A1
A2
b
b1
b2
c
D
E
e
e1
L
25
I2
24
Recommended Mount Pad
Symbol
E
HE
1
8
17
9
16
A
b
y
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 57 of 66
x
M
L
Lp
Detail F
c
A2
A1
F
A3
L1
e
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.32
0.37
0.45
0.105
0.125
0.175
6.9
7.0
7.1
6.9
7.0
7.1
–
0.8
–
8.8
9.0
9.2
8.8
9.0
9.2
0.3
0.5
0.7
1.0
–
–
0.6
0.45
0.75
–
0.25
–
–
–
0.2
–
–
0.1
–
0°
10°
0.5
–
–
1.0
–
–
7.4
–
–
–
–
7.4
7544 Group
36PJW-A
Plastic 36pin 6X6mm body WQFN
Weight(g)
0.83
JEDEC Code
–
Lead Material
Cu Alloy
MD
ME
b2
e
EIAJ Package Code
WQFN36-P-0606-0.50
I2
4.26 (Typ.)
D
27
c
19
18
Recommended Mount Pad
27
18
28
4.26 (Typ.)
y
E
e
28
19
Symbol
36
10
1
10
9
9
A
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 58 of 66
36
Lp
1
b
x
M
A
b
c
D
E
e
Lp
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
0.8
0.2
0.15
0.25
–
–
0.2
5.9
6.1
6.0
5.9
6.1
6.0
–
–
0.5
0.5
0.6
0.7
–
–
0.05
–
–
0.05
0.3
–
–
0.7
–
–
4.8
–
–
–
4.8
–
7544 Group
APPENDIX
NOTES ON PROGRAMMING
1. Processor Status Register
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because
they have an important effect on calculations.
<Reason>
After a reset, the contents of the processor status register (PS) are
undefined except for the I flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 1 Initialization of processor status register
(2) How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If
necessary, execute the PLP instruction to return the PS to its original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
↓
NOP
Fig. 2 Sequence of PLP instruction execution
(S)
(S)+1
Stored PS
Fig. 3 Stack memory contents after PHP instruction execution
Rev.1.04 2004.06.08
REJ03B0012-0104Z
page 59 of 66
2. Decimal calculations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper
decimal notation, set the decimal mode flag (D) to “1” with the
SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD
instruction.
(2) Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC or
SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of
the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag
must be initialized to “0” before each calculation. To check for a
borrow, the C flag must be initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 4 Status flag at decimal calculations
3. JMP instruction
When using the JMP instruction in indirect addressing mode, do
not specify the last address on a page as an indirect address.
4. BRK instruction
(1) Interrupt priority level
When the BRK instruction is executed with the following conditions satisfied, the interrupt execution is started from the address
of interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
5. Multiplication and Division Instructions
(1) The index X mode (T) and the decimal mode (D) flags do not
affect the MUL and DIV instruction.
(2) The execution of these instructions does not change the contents of the processor status register.
7544 Group
6. Read-modify-write instruction
Do not execute a read-modify-write instruction to the read invalid
address (SFR).
The read-modify-write instruction operates in the following sequence: read one-byte of data from memory, modify the data,
write the data back to original memory. The following instructions
are classified as the read-modify-write instructions in the 740
Family.
(1) Bit management instructions: CLB, SEB
(2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF
(3) Add and subtract instructions: DEC, INC
(4) Logical operation instructions (1’s complement): COM
Add and subtract/logical operation instructions (ADC, SBC, AND,
EOR, and ORA) when T flag = “1” operate in the way as the readmodify-write instruction. Do not execute the read invalid SFR.
<Reason>
When the read-modify-write instruction is executed to read invalid
SFR, the instruction may cause the following consequence: the instruction reads unspecified data from the area due to the read
invalid condition. Then the instruction modifies this unspecified
data and writes the data to the area. The result will be random
data written to the area or some unexpected event.
3. Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed.
<Reason>
The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when
these instructions are executed on a bit of the port latch of an I/O
port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit
managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to
this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for
an input port, its port latch holds the output data.
• As for a bit of the port latch which is set for an input port, its
value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port
latch contents.
*2 bit managing instructions : SEB, and CLB instructions
NOTES ON PERIPHERAL FUNCTIONS
Notes on I/O Ports
1. Pull-up control register
When using each port which built in pull-up resistor as an output
port, the pull-up control bit of corresponding port becomes invalid,
and pull-up resistor is not connected.
<Reason>
Pull-up control is effective only when each direction register is set
to the input mode.
2. Notes in stand-by state
In stand-by state*1 for low-power dissipation, do not make input
levels of an input port and an I/O port “undefined”.
Pull-up (connect the port to Vcc) or pull-down (connect the port to
Vss) these ports through a resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using a built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
•When setting as an output port : Prevent current from flowing out
to external.
<Reason>
The output transistor becomes the OFF state, which causes the
ports to be the high-impedance state. Note that the level becomes
“undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input
port and an I/O port are “undefined”. This may cause power
source current.
*1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
Rev.1.04 2004.06.08
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4. Direction register
The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using
direction register values as qualifiers, and bit test instructions
such as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read-modify-write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA instruction, etc.
7544 Group
Termination of Unused Pins
Notes on Interrupts
1. Terminate unused pins
Perform the following wiring at the shortest possible distance (20
mm or less) from microcomputer pins.
(1) I/O ports
Set the I/O ports for the input mode and connect each pin to VCC
or VSS through each resistor of 1 kΩ to 10 kΩ. The port which can
select a built-in pull-up resistor can also use the built-in pull-up resistor.
When using the I/O ports as the output mode, open them at “L” or
“H”.
• When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched over
to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may
increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program
periodically to increase the reliability of program.
1. Change of relevant register settings
When not requiring for the interrupt occurrence synchronous with
the following case, take the sequence shown in Figure 5.
• When switching external interrupt active edge
• When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
2. Termination remarks
(1) I/O ports setting as input mode
[1] Do not open in the input mode.
<Reason>
• The power source current may increase depending on the firststage circuit.
• An effect due to noise may be easily produced as compared with
proper termination (1) shown on the above “1. Terminate unused
pins”.
[2] Do not connect to VCC or VSS directly.
<Reason>
If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur.
[3] Do not connect multiple ports in a lump to VCC or VSS through
a resistor.
<Reason>
If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur
between ports.
Set the corresponding interrupt enable bit to “0” (disabled) .
↓
Set the interrupt edge selection bit, active edge switch bit, or
the interrupt source selection bit.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1” (enabled).
Fig. 5 Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit of the corresponding interrupt may be set to “1”.
• When switching external interrupt active edge
INT0 interrupt edge selection bit
(bit 0 of Interrupt edge selection register (address 3A16))
INT1 interrupt edge selection bit
(bit 1 of Interrupt edge selection register)
CNTR0 active edge switch bit
(bit 2 of timer X mode register (address 2B16))
CNTR1 active edge switch bit
(bit 6 of timer A mode register (address 1D16))
2. Check of interrupt request bit
When executing the BBC or BBS instruction to determine an interrupt request bit immediately after this bit is set to “0”, take the
following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after an interrupt request bit is cleared to “0”, the value of the interrupt
request bit before being cleared to “0” is read.
Set the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Fig. 6 Sequence of check of interrupt request bit
Rev.1.04 2004.06.08
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7544 Group
Notes on Timers
Notes on Timer X
1. When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
1. CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit (bit 2 of timer X mode register (address 2B16)).
When this bit is “0”, the CNTR0 interrupt request bit goes to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR 0 interrupt request bit goes to “1” at the rising edge of
CNTR0 pin input signal.
2. When a count source of timer X is switched, stop a count of the
timer.
Notes on Timer 1
1. Timer 1 count source
The “on-chip oscillator output” of timer 1 count source selection
bits (bits 1 and 0 of timer count source set register 2 (address
2F16)) can be selected while the on-chip oscillator oscillation control bit (bit 3 of CPU mode register (address 3B16)) is “0” (on-chip
oscillator oscillation enabled).
2. Timer X count source selection
The f(XIN) (frequency not divided) can be selected by the timer X
count source selection bits (bits 1 and 0 of timer count source set
register 1 (address 2E16)) only when the ceramic oscillation or the
on-chip oscillator is selected.
Do not select it for the timer X count source at the RC oscillation.
Notes on Timer A
1. CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit (bit 6 of timer A mode register (address 1D16)).
When this bit is “0”, the CNTR1 interrupt request bit goes to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit goes to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR 1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
2. Period measurement mode, event counter mode and pulse
width HL continuously measurement mode
Set the direction register of port P00, which is also used as CNTR1
pin, to input.
Set the key-on wakeup function of P0 0, which is also used as
CNTR1 pin, to be disabled by setting the P00 key-on wakeup selection bit (bit 7 of interrupt edge selection register (address 3A16))
to “1”.
3. Timer A count source
The “on-chip oscillator output” of timer A count source selection
bits (bits 3 and 2 of timer count source set register 2 (address
2F16)) can be selected while the on-chip oscillator oscillation control bit (bit 3 of CPU mode register (address 3B16)) is “0” (on-chip
oscillator oscillation enabled).
Rev.1.04 2004.06.08
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3. Pulse output mode
Set the direction register of port P14, which is also used as CNTR0
pin, to output.
When the TXOUT pin is used, set the direction register of port P03,
which is also used as TXOUT pin, to output.
4. Pulse width measurement mode
Set the direction register of port P14, which is also used as CNTR0
pin, to input.
7544 Group
Notes on Serial I/O
1. Clock synchronous serial I/O
(1) When the transmit operation is stopped, clear the serial I/O enable bit (bit 7) and the transmit enable bit (bit 4 of serial I/O
control register (address 1A16)) to “0” (serial I/O and transmit
disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports,
the transmission data is not output). When data is written to the
transmit buffer register in this state, data starts to be shifted to the
transmit shift register. When the serial I/O enable bit is set to “1” at
this time, the data during internally shifting is output to the TxD pin
and an operation failure occurs.
(2) When the receive operation is stopped, clear the receive enable bit (bit 5) to “0” (receive disabled), or clear the serial I/O
enable bit (bit 7 of serial I/O control register (address 1A16)) to
“0” (serial I/O disabled).
(3) When the transmit/receive operation is stopped, clear both the
transmit enable bit and receive enable bit to “0” (transmit and
receive disabled) simultaneously. (any one of data transmission and reception cannot be stopped.)
<Reason>
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit cannot be initialized even
if the serial I/O enable bit is cleared to “0” (serial I/O disabled)
(same as (1)).
(4) When signals are output from the SRDY pin on the reception
side by using an external clock, set all of the receive enable bit
(bit 5), the SRDY output enable bit (bit 2 of serial I/O control
register (address 1A16)), and the transmit enable bit to “1”.
(5) When the SRDY signal input is used, set the using pin to the input mode before data is written to the transmit/receive buffer
register.
2. UART
When the transmit operation is stopped, clear the transmit enable
bit to “0” (transmit disabled).
<Reason>
Same as (1) shown on the above “1. Clock synchronous serial I/
O“.
When the receive operation is stopped, clear the receive enable
bit to “0” (receive disabled).
When the transmit/receive operation is stopped, clear the transmit
enable bit to “0” (transmit disabled) and receive enable bit to “0”
(receive disabled).
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3. Notes common to clock synchronous serial I/O and UART
(1) Set the serial I/O control register again after the transmission
and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
Set both the transmit enable bit (TE)
and the receive enable bit (RE), or
one of them to “1”
Can be set
with the LDM
instruction at
the same time
Fig. 7 Sequence of setting serial I/O control register again
(2) The transmit shift completion flag (bit 2 of serial I/O status register (address 19 16)) changes from “1” to “0” with a delay of
0.5 to 1.5 shift clocks. When data transmission is controlled
with referring to the flag after writing the data to the transmit
buffer register, note the delay.
(3) When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set “1” to
the transmit enable bit while the SCLK is “H” state. Also, write
to the transmit buffer register while the SCLK is “H” state.
(4) When the transmit interrupt is used, set as the following sequence.
➀ Serial I/O transmit interrupt enable bit is set to “0” (disabled).
➁ Serial I/O transmit enable bit is set to “1”.
➂ Serial I/O transmit interrupt request bit (bit 1 of interrupt request
register 1 (address 3C16)) is set to “0” after 1 or more instructions have been executed.
➃ Serial I/O transmit interrupt enable bit (bit 1 of interrupt control
register 1 (address 3E16)) is set to “1” (enabled).
<Reason>
When the transmit enable bit is set to “1”, the transmit buffer
empty flag (bit 0) and transmit shift completion flag (bit 2 of serial
I/O status register (address 1916)) are set to “1”.
Accordingly, even if the timing when any of the above flags is set
to “1” is selected for the transmit interrupt source, interrupt request
occurs and the transmit interrupt request bit is set.
(5) Write to the baud rate generator (BRG) while the transmit/receive operation is stopped.
7544 Group
4. I/O pin function when serial I/O is enabled.
The pin functions of P12/S CLK and P13 /SRDY are switched to as
follows according to the setting values of a serial I/O mode selection bit (bit 6 of serial I/O control register (address 1A 16)) and a
serial I/O synchronous clock selection bit (bit 1 of serial I/O control
register).
(1) Serial I/O mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
• Setup of a serial I/O synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
• Setup of a SRDY output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY output pin.
(2) Serial I/O mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
• Setup of a serial I/O synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
• When clock asynchronous (UART) type serial I/O is selected, it
functions P13 pin. It can be used as a normal I/O pin.
Notes on A/D conversion
1. Analog input pin
In order to execute the A/D conversion correctly, to complete the
charge to an internal capacitor within the specified time is required. The maximum output impedance of the analog input
source required to complete the charge to a capacitor within the
specified time is as follows;
3. A/D conversion accuracy
As for AD translation accuracy, on the following operating conditions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc
voltage, accuracy may become low rather than the case
where VREF voltage and Vcc voltage are set up to the same
value.
(2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the
low temperature may become extremely low compared with
that at room temperature. When the system would be used at
low temperature, the use at VREF =3.0 V or more is recommended.
Notes on Watchdog Timer
1. The watchdog timer is operating during the wait mode. Write
data to the watchdog timer control register to prevent timer underflow.
2. The watchdog timer stops during the stop mode. However, the
watchdog timer is running during the oscillation stabilizing time
after the STP instruction is released. In order to avoid the underflow of the watchdog timer, the watchdog timer control
register must be written just before executing the STP instruction.
3. The STP instruction disable bit (bit 6 of watchdog timer control
register (address 3916)) can be set to “1” but cannot be set to
“0” by program.
Notes on RESET pin
About 35 kΩ (at f(XIN) = 8 MHz)
When the maximum output impedance exceeds the above value,
equip an analog input pin with an external capacitor of 0.01µF to
1µF between an analog input pin and VSS.
Further, be sure to verify the operation of application products on
the user side.
<Reason>
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high
impedance are input to an analog input pin, charge and discharge
noise generates. This may cause the A/D conversion/comparison
precision to be worse.
2. Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of
the capacity will be lost if the clock frequency is too low. This may
cause the A/D conversion precision to be worse. Accordingly, set
f(X IN) in order that the A/D conversion clock is 500 kHz or over
during A/D conversion.
Rev.1.04 2004.06.08
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1. Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the Vss pin.
And use a 1000 pF or more capacitor for high frequency use.
When connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor
as short as possible.
• Be sure to verify the operation of application products on the
user side.
<Reason>
If the several nanosecond or several ten nanosecond impulse
noise enters the RESET pin, it may cause a microcomputer failure.
7544 Group
Notes on Clock Generating Circuit
Notes on Oscillation Control
1. Switch of ceramic/quartz-crystal oscillation and RC oscillation
After releasing reset, the oscillation mode selection bit (bit 5 of
CPU mode register (address 3B16)) is “0” (ceramic/quartz-crystal
oscillation selected). When the RC oscillation is used, after releasing reset, set this bit to “1”.
1. Oscillation stop detection circuit
(1) When the stop mode is used, set the oscillation stop detection
function to “invalid”.
2. Double-speed mode
The double-speed mode can be used only when a ceramic oscillation is selected. Do not use it when an RC oscillation is selected.
3. CPU mode register
Oscillation mode selection bit (bit 5), processor mode bits (bits 1
and 0) of CPU mode register (address 3B16) are used to select oscillation mode and to control operation modes of the
microcomputer. In order to prevent the dead-lock by erroneously
writing (ex. program run-away), these bits can be rewritten only
once after releasing reset. After rewriting, it is disabled to write any
data to the bit. (The emulator MCU “M37542RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB, etc.) are
executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
4. Clock division ratio, XIN oscillation control, on-chip oscillator
control
The state transition shown in Fig. 81 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 81.
5. On-chip oscillator operation
When the MCU operates by the on-chip oscillator for the main
clock, connect XIN pin to VCC through a 1 kΩ to 10 kΩ resistor and
leave XOUT pin open.
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range.
Be careful that this margin of frequencies when designing application products.
6. Ceramic resonator
When the ceramic resonator/quartz-crystal oscillation is used for
the main clock, connect the ceramic resonator and the external
circuit to pins XIN and XOUT at the shortest distance. A feedback
resistor is built-in.
7. RC oscillation
When the RC oscillation is used for the main clock, connect the
XIN pin and XOUT pin to the external circuit of resistor R and the
capacitor C at the shortest distance.
The frequency is affected by a capacitor, a resistor and a microcomputer.
So, set the constants within the range of the frequency limits.
8. External clock
When the external signal clock is used for the main clock, connect
the XIN pin to the clock source and leave XOUT pin open.
Select “0” (ceramic oscillation) to oscillation mode selection bit.
Rev.1.04 2004.06.08
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(2) When the ceramic or RC oscillation is stopped (bit 4 of CPU
mode register (address 3B 16)), set the oscillation stop detection function to “invalid”.
(3) The oscillation stop detection circuit is not included in the emulator MCU “M37542RSS”.
2. Stop mode
(1) When the stop mode is used, set the oscillation stop detection
function to “invalid”.
(2) When the stop mode is used, set “0” (STP instruction enabled)
to the STP instruction disable bit of the watchdog timer control
register (bit 6 of watchdog timer control register (address
3916)).
(3) The oscillation stabilizing time after release of STP instruction
can be selected from “set automatically”/“not set automatically” by the oscillation stabilizing time set bit after release of
the STP instruction (bit 0 of MISRG (address 3816)). When “0”
is set to this bit, “01 16” is set to timer 1 and “FF 16 ” is set to
prescaler 1 automatically at the execution of the STP instruction. When “1” is set to this bit, set the wait time to timer 1 and
prescaler 1 according to the oscillation stabilizing time of the
oscillation. Also, when timer 1 is used, set values again to
timer 1 and prescaler 1 after system is returned from the stop
mode.
(4) The STP instruction cannot be used when the on-chip oscillator is selected by the clock division ratio selection bits (bits 7
and 6 of CPU mode register (address 3B16)).
(5) When the stop mode is used, set the on-chip oscillator oscillation control bit (bit 3 of CPU mode register (address 3B16)) to
“1” (on-chip oscillator oscillation stop).
(6) Do not execute the STP instruction during the A/D conversion.
7544 Group
Electric Characteristic Differences Among
Mask ROM and One Time PROM Version
MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation among mask ROM and One
Time PROM version MCUs due to the differences in the manufacturing processes.
When manufacturing an application system with One Time PROM
version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the
mask ROM version.
Note on Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF to 0.1 µF is recommended.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.
Rev.1.04 2004.06.08
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7544 Group Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
–
1.00 Nov. 8, 2002
1.01 May. 6, 2003 44 to 48
48
1.02 Jun. 25, 2003
First edition issued
Added to Electrical Characteristics
Entered to Limits
Icc Power source current On-chip oscillator operation mode,
On-chip oscillator operation mode(in WIT state)
49
Entered to Limits
A/D Converter characteristics
6
1.03 Feb. 12, 2004
Table 2 and Fig.6: Under development eliminated.
17
[Interrupt edge selection register] added.
23
Fig.23: “1” is added to Fig. title and register name.
Timer count source set register 1, TCSS1
29
■ Notes on A/D converter added.
33
Fig.38: Processing of XIN pin revised.
38
DATA REQUIRED FOR MASK ORDERS added.
39
■ Notes on A/D converter added.
47
Table 12: VOH/VOL Test conditions revised.
Hysteresis RESET revised.
49
Table 14: ABS Test conditions revised.
Note added.
3
Fig.4 Pin configuration : 36PJW-A added.
1.04 Jun. 08, 2004
6
Fig.7 Functional block diagram: 36PJW-A added.
8
Package: 36PJW-A added.
Table 2: M37544M2-XXXHP, M37544G2HP added.
“Under development” eliminated.
14
Fig.14: SIO1STS → SIOSTS, SIO1CON → SIOCON
23
Fig.23: Address revised.
25
Fig.25: Bit 6 revised.
31
Comparator and control circuit revised.
37
Oscillation stop detection circuit revised.
38
Fig. 46, Fig. 47 a bit name revised.
41
Countermeasure against noise added.
(NOTES ON PERIPHERAL FUNCTIONS described previously here are included
in APPENDIX at the end of this data sheet.)
49
Part number: M37544M2-XXXHP, M37544G2HP added.
58
PACKAGE OUTLINE: 36PJW-A added.
59 to 66 APPENDIX added.
All pages Words standardized: On-chip oscillator, A/D converter
(1/1)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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