[ /Title (CD74 HC406 7, CD74 HCT40 67) /Subject (HighSpeed CMOS CD74HC4067, CD74HCT4067 Data sheet acquired from Harris Semiconductor SCHS209C February 1998 - Revised July 2003 High-Speed CMOS Logic 16-Channel Analog Multiplexer/Demultiplexer Features Description • Wide Analog Input Voltage Range The CD74HC4067 and CD74HCT4067 devices are digitally controlled analog switches that utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits. • Low “ON” Resistance - VCC = 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . 70Ω (Typ) - VCC = 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Ω (Typ) • Fast Switching and Propagation Speeds These analog multiplexers/demultiplexers control analog voltages that may vary across the voltage supply range. They are bidirectional switches thus allowing any analog input to be used as an output and vice-versa. The switches have low “on” resistance and low “off” leakages. In addition, these devices have an enable control which when high will disable all switches to their “off” state. • “Break-Before-Make” Switching. . . . . 6ns (Typ) at 4.5V • Available in Both Narrow and Wide-Body Plastic Packages • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information • Wide Operating Temperature Range . . . -55oC to 125oC PART NUMBER • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V TEMP. RANGE (oC) CD74HC4067E -55 to 125 24 Ld PDIP CD74HC4067M -55 to 125 24 Ld SOIC CD74HC4067M96 -55 to 125 24 Ld SOIC CD74HC4067SM96 -55 to 125 24 Ld SSOP CD74HCT4067M -55 to 125 24 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD74HC4067 (PDIP, SOIC, SSOP) CD74HCT4067 (SOIC) TOP VIEW COMMON INPUT/OUTPUT 1 I7 2 24 VCC 23 I8 I6 3 22 I9 I5 4 21 I10 I4 5 20 I11 I3 6 19 I12 I2 7 18 I13 I1 8 17 I14 I0 9 16 I15 S0 10 15 E S1 11 14 S2 GND 12 13 S3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated PACKAGE 1 CD74HC4067, CD74HCT4067 Functional Diagram I0 9 10 S0 S1 S2 S3 11 P 14 N 13 BINARY 1 OF 16 DECODER SN = 5 STAGES E = 4 STAGES 14 - OUTPUT CIRCUITS SAME AS ABOVE (WITH ANALOG INPUTS) I1 TO I14 1 P N 16 15 I15 E TRUTH TABLE S0 S1 S2 S3 E SELECTED CHANNEL X X X X 1 None 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 2 1 1 0 0 0 3 0 0 1 0 0 4 1 0 1 0 0 5 0 1 1 0 0 6 1 1 1 0 0 7 0 0 0 1 0 8 1 0 0 1 0 9 0 1 0 1 0 10 1 1 0 1 0 11 0 0 1 1 0 12 1 0 1 1 0 13 0 1 1 1 0 14 1 1 1 1 0 15 H= High Level L= Low Level X= Don’t Care 2 COMMON INPUT/ OUTPUT CD74HC4067, CD74HCT4067 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC (Voltages Referenced to Ground) . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical) θJA (oC/W) E (PDIP) Package, Note 1 . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package, Note 2 . . . . . . . . . . . . . . . . . . . 46 SM (SSOP) Package, Note 2. . . . . . . . . . . . . . . . . . 63 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3. 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) VIS (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS VIH - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V HC TYPES High Level Input Voltage Low Level Input Voltage Maximum “ON” Resistance IO = 1mA VIL RON - - VCC or GND VCC or GND 4.5 - 70 160 - 200 - 240 Ω 6 - 60 140 - 175 - 210 Ω VCC to GND VCC to GND 4.5 - 90 180 - 225 - 270 Ω 6 - 80 160 - 200 - 240 Ω - - 4.5 - 10 - - - - - Ω 6 - 8.5 - - - - - Ω Maximum “ON” Resistance Between Any Two Switches ∆RON Switch “Off” Leakage Current 16 Channels IIZ E = VCC VCC or GND 6 - - ±0.8 - ±8 - ±8 µA Logic Input Leakage Current II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA 3 CD74HC4067, CD74HCT4067 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) VIS (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS ICC VCC or GND - 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 - - 0.8 - 0.8 - 0.8 V Maximum “ON” Resistance IO = 1mA RON VCC or GND VCC or GND 4.5 - 70 160 - 200 - 240 Ω VCC to GND VCC to GND 4.5 - 90 180 - 225 - 270 Ω PARAMETER Quiescent Device Current IO = 0mA HCT TYPES Maximum “ON” Resistance Between Any Two Switches ∆RON - - 4.5 - 10 - - - - - Ω Switch “Off” Leakage Current 16 Channels IIZ E = VCC VCC or GND 6 - - ±0.8 - ±8 - ±8 µA Logic Input Leakage Current II VCC or GND (Note 3) - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND - 6 - - 8 - 80 - 160 µA ∆ICC (Note 4) VCC -2.1 - - - 100 360 - 450 - 490 µA Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTES: 3. Any voltage between VCC and GND. 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOAD S0 - S3 0.5 E 0.3 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns 5 - 6 - - - - - ns HC TYPES Propagation Delay Time Switch In to Out CL = 15pF 4 CD74HC4067, CD74HCT4067 Switching Specifications Input tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPZH, tPZL CL = 50pF 2 - - 275 - 345 - 415 ns 4.5 - - 55 - 69 - 83 ns 6 - - 47 - 59 - 71 ns CL = 15pF 5 - 23 - - - - - ns CL = 50pF 2 - - 300 - 375 - 450 ns 4.5 - - 60 - 75 - 90 ns 6 - - 51 - 64 - 76 ns CL = 15pF 5 - 25 - - - - - ns CL = 50pF 2 - - 275 - 345 - 415 ns 4.5 - - 55 - 69 - 83 ns 6 - - 47 - 59 - 71 ns CL = 15pF 5 - 23 - - - - - ns CL = 50pF 2 - - 290 - 365 - 435 ns 4.5 - - 58 - 73 - 87 ns 6 - - 49 - 62 - 74 ns CL = 50pF 5 - 21 - - - - - ns CI - - - - 10 - 10 - 10 pF CPD - 5 - 93 - - - - - pF Propagation Delay Time Switch In to Out tPLH, tPHL CL = 50pF 4.5 - - 15 - 19 - 22 ns CL = 15pF 5 - 6 - - - - - ns Switch Turn On E to Out tPZH, tPZL CL = 50pF 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns Switch Turn On Sn to Out tPZH, tPZL CL = 50pF 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns Switch Turn Off E to Out tPHZ, tPLZ CL = 50pF 4.5 - - 55 - 69 - 83 ns CL = 15pF 5 - 23 - - - - - ns Switch Turn Off Sn to Out tPHZ, tPLZ CL = 50pF 4.5 - - 58 - 73 - 87 ns CL = 15pF 5 - 21 - - - - - ns CI - - - - 10 - 10 - 10 pF CPD - 5 - 96 - - - - - pF PARAMETER Switch Turn On E to Out Switch Turn On Sn to Out Switch Turn Off E to Out Switch Turn Off Sn to Out Input (Control) Capacitance Power Dissipation Capacitance (Notes 5, 6) tPZH, tPZL tPHZ, tPLZ tPHZ, tPLZ HCT TYPES Input (Control) Capacitance Power Dissipation Capacitance (Notes 5, 6) NOTES: 5. CPD is used to determine the dynamic power consumption, per package. 6. PD = CPD VCC2 fi + Σ (CL + CS) VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, CS = switch capacitance, VCC = supply voltage. 5 CD74HC4067, CD74HCT4067 Analog Channel Specifications TA = 25oC PARAMETER TEST CONDITIONS VCC (V) HC/HCT UNITS Switch Frequency Response Bandwidth at -3dB (Figure 2) Figure 4, Notes 7, 8 4.5 89 MHz Sine Wave Distortion Figure 5 4.5 0.051 % Feedthrough Noise E to Switch Figure 6, Notes 8, 9 4.5 TBE mV TBE mV 4.5 -75 dB Switch Input Capacitance, CS - 5 pF Common Capacitance, CCOM - 50 pF Feedthrough Noise S to Switch Switch “OFF” Signal Feedthrough (Figure 3) Figure 7 NOTES: 7. Adjust input level for 0dBm at output, f = 1MHz. 8. VIS is centered at VCC/2. 9. Adjust input for 0dBm at VIS. Typical Performance Curves 0 140 TA = 25oC, GND = 0V -1 -2 100 -3 UNITS (dB) “ON” RESISTANCE, RON (Ω) 120 80 60 VCC = 4.5V 40 -4 -5 -6 -7 -8 20 -9 0 0 1 2 3 4 5 6 7 8 9 VCC = 4.5V RL = 50Ω TA = 25oC -10 104 10 105 106 INPUT SIGNAL VOLTAGE, VIS (V) SWITCH-OFF SIGNAL FEEDTHROUGH (dB) FIGURE 2. TYPICAL SWITCH FREQUENCY RESPONSE 0 -20 VCC = 4.5V RL = 50Ω TA = 25oC -30 -40 -50 -60 -70 -80 -90 -100 104 108 FREQUENCY, f (Hz) FIGURE 1. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL VOLTAGE -10 107 105 106 107 FREQUENCY, f (Hz) 108 FIGURE 3. TYPICAL SWITCH-OFF SIGNAL FEEDTHROUGH vs FREQUENCY 6 CD74HC4067, CD74HCT4067 Analog Test Circuits VCC VCC 0.1µF VIS SINE WAVE 10µF VIS VOS SWITCH ON 50Ω VOS SWITCH ON 10kΩ 10pF dB METER VCC/2 50pF DISTORTION METER VCC/2 fIS = 1kHz TO 10kHz FIGURE 4. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 5. SINE WAVE DISTORTION TEST CIRCUIT VCC 600Ω VCC SWITCH ALTERNATING ON AND OFF tr, tf ≤ 6ns fCONT = 1MHz 50% DUTY CYCLE 0.1µF 600Ω 10pF SCOPE VCC/2 FIGURE 6. CONTROL-TO-SWITCH FEEDTHROUGH NOISE TEST CIRCUIT VOS SWITCH OFF VIS VOS VC = VIL fIS ≥ 1MHz SINEWAVE R = 50Ω C = 10pF R R VCC/2 VCC/2 C dB METER FIGURE 7. SWITCH OFF SIGNAL FEEDTHROUGH TEST CIRCUIT Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 8. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 9. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 7 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) CD74HC4067DB PREVIEW SSOP DB 24 60 TBD Call TI Call TI -55 to 125 CD74HC4067E ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4067E CD74HC4067EE4 ACTIVE PDIP N 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4067E CD74HC4067M ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4067M CD74HC4067M96 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4067M CD74HC4067M96E4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4067M CD74HC4067M96G4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4067M CD74HC4067ME4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4067M CD74HC4067MG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4067M CD74HC4067SM96 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4067 CD74HC4067SM96E4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4067 CD74HC4067SM96G4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HP4067 CD74HCT4067M ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4067M CD74HCT4067ME4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4067M CD74HCT4067MG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4067M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD74HCT4067 : • Automotive: CD74HCT4067-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4067M96 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CD74HC4067M96 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CD74HC4067M96G4 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CD74HC4067SM96 SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4067M96 SOIC DW 24 2000 366.0 364.0 50.0 CD74HC4067M96 SOIC DW 24 2000 367.0 367.0 45.0 CD74HC4067M96G4 SOIC DW 24 2000 367.0 367.0 45.0 CD74HC4067SM96 SSOP DB 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002 N (R–PDIP–T24) PLASTIC DUAL–IN–LINE 1.222 (31,04) MAX 24 13 0.360 (9,14) MAX 1 12 0.070 (1,78) MAX 0.200 (5,08) MAX 0.425 (10,80) MAX 0.020 (0,51) MIN Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0’–15’ 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25) NOM 4040051–3/D 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS–010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI008 – OCTOBER 1994 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PIN SHOWN A 24 13 0.560 (14,22) 0.520 (13,21) 1 12 0.060 (1,52) TYP 0.200 (5,08) MAX 0.610 (15,49) 0.590 (14,99) 0.020 (0,51) MIN Seating Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0.010 (0,25) M PINS ** 0°– 15° 0.010 (0,25) NOM 24 28 32 40 48 52 A MAX 1.270 (32,26) 1.450 (36,83) 1.650 (41,91) 2.090 (53,09) 2.450 (62,23) 2.650 (67,31) A MIN 1.230 (31,24) 1.410 (35,81) 1.610 (40,89) 2.040 (51,82) 2.390 (60,71) 2.590 (65,79) DIM 4040053 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MS-011 Falls within JEDEC MS-015 (32 pin only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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