Cypress CY62256VN 256k (32k ã 8) static ram Datasheet

CY62256VN
256K (32K × 8) Static RAM
256K (32K × 8) Static RAM
Features
Functional Description
■
Temperature ranges
❐ Commercial: 0 °C to +70 °C
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
The CY62256VN[1] family is composed of two high performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and tristate drivers.
These devices have an automatic power down feature, reducing
the power consumption by over 99% when deselected.
■
Speed: 70 ns
■
Low voltage range: 2.7 V to 3.6 V
■
Low active power and standby power
■
Easy memory expansion with CE and OE features
■
TTL compatible inputs and outputs
■
Automatic power down when deselected
■
CMOS for optimum speed and power
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
■
Available in standard Pb-free and non Pb-free 28-pin (300-mil)
narrow SOIC, 28-pin TSOP-I, and 28-pin reverse TSOP-I
packages
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
Logic Block Diagram
I/O0
INPUTBUFFER
I/O1
32K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
I/O3
I/O4
I/O5
CE
WE
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A12
A11
A1
A0
A14
A13
OE
.
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 001-06512 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 4, 2011
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CY62256VN
Contents
Product Portfolio .............................................................. 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
Data Retention Characteristics ....................................... 5
Switching Characteristics ................................................ 6
Document Number: 001-06512 Rev. *D
Typical DC and AC Characteristics ................................ 9
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
Page 2 of 14
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CY62256VN
Product Portfolio
Product
Power Dissipation
VCC Range (V)
Range
Min
Typ[2]
Max
Operating, ICC (mA)
Standby, ISB2 (A)
Typ[2]
Typ[2]
Max
Max
CY62256VNLL
Commercial
2.7
3.0
3.6
11
30
0.1
5
CY62256VNLL
Industrial
2.7
3.0
3.6
11
30
0.1
10
CY62256VNLL
Automotive-A
2.7
3.0
3.6
11
30
0.1
10
CY62256VNLL
Automotive-E
2.7
3.0
3.6
11
30
0.1
130
Pin Configurations
Narrow SOIC
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
20
19
18
17
16
15
14
13
12
11
10
9
8
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
VCC
WE
A4
A3
A2
A1
OE
7
6
8
9
5
4
3
2
10
11
12
13
14
15
16
17
18
1
28
27
26
25
24
23
22
TSOP I
Reverse Pinout
Top View
(not to scale)
19
20
21
A12
A13
A14
I/O0
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A0
Pin Definitions
Pin Number
Type
Description
1–10, 21, 23–26 Input
A0–A14. Address inputs
11–13, 15–19
Input/Output
I/O0–I/O7. Data lines. Used as input or output lines depending on operation.
27
Input/Control
WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted.
20
Input/Control
CE. When LOW, selects the chip. When HIGH, deselects the chip
22
Input/Control
OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins
14
Ground
GND. Ground for the device
28
Power Supply
VCC. Power supply for the device
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25 °C, and tAA = 70 ns.
Document Number: 001-06512 Rev. *D
Page 3 of 14
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CY62256VN
Maximum Ratings
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch-up current .................................................... > 200 mA
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage to ground potential
(pin 28 to pin 14)...........................................–0.5 V to +4.6 V
Operating Range
Device
Range
CY62256VN Commercial
Ambient
Temperature
(TA)[4]
VCC
0 °C to +70 °C
2.7 V to 3.6 V
DC voltage applied to outputs
in high Z State[3] .................................. –0.5 V to VCC + 0.5 V
Industrial
–40 °C to +85 °C
Automotive-A
–40 °C to +85 °C
DC input voltage[3] ............................... –0.5 V to VCC + 0.5 V
Automotive-E –40 °C to +125 °C
Output current into outputs (LOW) .............................. 20 mA
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
–70
Min
Typ[5]
Max
2.4
–
–
Unit
VOH
Output HIGH voltage
IOH = 1.0 mA
VCC = 2.7 V
VOL
Output LOW voltage
IOL = 2.1 mA
VCC = 2.7 V
–
–
0.4
V
VIH
Input HIGH voltage
2.2
–
VCC + 0.3V
V
VIL
Input LOW voltage
–0.5
–
0.8
V
IIX
Input leakage current
GND < VIN < VCC
Commercial/
Indusrial/
Automotive-A
–1
–
+1
A
Automotive-E
–10
–
+10
A
IOZ
Output leakage current
GND < VIN < VCC, Output
Disabled
Commercial/
Indusrial/
Automotive-A
–1
–
+1
A
Automotive-E
–10
–
+10
A
V
ICC
VCC operating supply
current
All ranges
–
11
30
mA
ISB1
Automatic CE power
VCC = 3.6 V, CE > VIH,
All ranges
down current - TTL inputs VIN > VIH or VIN < VIL, f = fMAX
–
100
300
A
ISB2
Automatic CE power
down current - CMOS
inputs
VCC = 3.6 V, CE > VCC – 0.3 V, Commercial
VIN > VCC – 0.3 V or VIN < 0.3 V,
Indusrial/
f=0
Automotive-A
–
0.1
5
A
–
10
Automotive-E
–
130
VCC = 3.6 V, IOUT = 0 mA,
f = fMAX = 1/tRC
Notes
3. VIL (min) = –2.0 V for pulse durations of less than 20 ns.
4. TA is the “Instant-On” case temperature.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25 °C, and tAA = 70 ns.
Document Number: 001-06512 Rev. *D
Page 4 of 14
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CY62256VN
Capacitance
Parameter[6]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
6
pF
8
pF
TA = 25 °C, f = 1 MHz, VCC = 3.0 V
Thermal Resistance
Parameter[6]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
SOIC
TSOPI
RTSOPI
Unit
68.45
87.62
87.62
C/W
26.94
23.73
23.73
C/W
Figure 1. AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
OUTPUT
VCC
50 pF
INCLUDING
JIG AND
SCOPE
10%
R2
90%
10%
90%
GND
< 5 ns
< 5 ns
Equivalent to:
THÉVENIN EQUIVALENT
Rth
OUTPUT
Parameter
R1
R2
RTH
VTH
Vth
Value
1100
1500
645
1.750
Units
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
VDR
VCC for data retention
ICCDR
Data retention current
tCDR[6]
Chip deselect to data
retention time
tR[6]
Operation recovery time
Conditions[7]
VCC = 1.4 V,
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V
or VIN < 0.3 V
Min
Typ[8]
Max
Unit
1.4
–
–
V
Commercial
–
0.1
3
A
Indusrial/
Automotive-A
–
Automotive-E
6
–
50
0
–
–
ns
tRC
–
–
ns
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. No input may exceed VCC + 0.3 V.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25 °C, and tAA = 70 ns.
Document Number: 001-06512 Rev. *D
Page 5 of 14
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CY62256VN
Figure 2. Data Retention Waveform
DATA RETENTION MODE
1.8 V
VCC
VDR > 1.4 V
tCDR
1.8 V
tR
CE
Switching Characteristics
Over the Operating Range[9]
Parameter
Description
CY62256VN-70
Min
Max
Unit
Read Cycle
tRC
Read cycle time
70
–
ns
tAA
Address to data valid
–
70
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
70
ns
tDOE
OE LOW to data valid
–
35
ns
5
–
ns
–
25
ns
OE LOW to low
tLZOE
Z[10]
OE HIGH to high
tHZOE
Z[10, 11]
Z[10]
tLZCE
CE LOW to low
10
–
ns
tHZCE
CE HIGH to high Z[10, 11]
–
25
ns
tPU
CE LOW to power up
0
–
ns
CE HIGH to power down
–
70
ns
tWC
Write cycle time
70
–
ns
tSCE
CE LOW to write end
60
–
ns
tAW
Address setup to write end
60
–
ns
tPD
Write Cycle
[12, 13]
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
50
–
ns
tSD
Data setup to write end
30
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to high Z[10, 11]
–
25
ns
tLZWE
WE HIGH to low Z[10]
10
–
ns
Notes
9. Test conditions assume signal transition time of 5 ns or less timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOL/IOH
and 100-pF load capacitance.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-06512 Rev. *D
Page 6 of 14
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CY62256VN
Switching Waveforms
Figure 3. Read Cycle No. 1[14, 15]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2[15, 16]
t RC
CE
tACE
OE
t HZOE
tHZCE
tDOE
DATA OUT
t LZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
t PD
t PU
ICC
50%
50%
ISB
Figure 5. Write Cycle No. 1 (WE Controlled)[17, 18, 19]
tWC
ADDRESS
CE
tAW
tSA
WE
tHA
t PWE
OE
tSD
DATA I/O
NOTE 20
tHD
DATAINVALID
t HZOE
Notes
14. Device is continuously selected. OE, CE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
17. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
18. Data I/O is high impedance if OE = VIH.
19. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
20. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 001-06512 Rev. *D
Page 7 of 14
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CY62256VN
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (CE Controlled)[21, 22, 23]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
t HD
DATAINVALID
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)[23, 24]
tWC
ADDRESS
CE
tAW
t HA
tSA
WE
tSD
DATA I/O
NOTE 25
t HZWE
t HD
DATA INVALID
tLZWE
Notes
21. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
22. Data I/O is high impedance if OE = VIH.
23. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
24. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
25. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 001-06512 Rev. *D
Page 8 of 14
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CY62256VN
Typical DC and AC Characteristics
1.4
1.6
1.4
1.2
2.5
1.0
2.0
TA= 25C
0.4
0.2
0.0
0.0
55
3.6
3.2
2.8
2.4
2.0
1.8
1.6
0.5
25
125
2.5
1.6
2.0
1.4
NORMALIZED tAA
VCC = 3.0V
TA = 25C
1.0
0.0
1.65
1.2
1.0
0.8
0.5
2.1
2.6
3.1
3.6
0.6
55
25
125
OUTPUT SOURCE CURRENT (mA)
3.
3V
105
OUTPUT SINK CURRENT
14 vs. OUTPUT VOLTAGE
12
10
8
6
4
TA = 25°C
2
0
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
25
AMBIENT TEMPERATURE (C)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
ISB
–0.5
55
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
1.5
1.0
0.4
OUTPUT SINK CURRENT (mA)
0.6
0.6
1.5
=
0.8
0.8
cc
1.0
V
1.2
3.0
VCC = 3.0V
ISB2 A
NORMALIZED ICC
NORMALIZED ICC
1.8
0.2
NORMALIZED tAA
STANDBY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
–14
–12
–10
–8
–6
TA = 25°C
–4
0
0.0
0.5
1.0
1.5
2
2.5
OUTPUT VOLTAGE (V)
Document Number: 001-06512 Rev. *D
Page 9 of 14
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CY62256VN
Typical DC and AC Characteristics
(continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED ICC vs. CYCLE TIME
1.25
NORMALIZED ICC
DELTA tAA (ns)
30.0
25.0 T = 25C
A
VCC = 3V
20.0
15.0
10.0
VCC = 3.0V
1.00
TA = 25C
VIN = 0.5V
0.75
5.0
0.0
0
200
400
600
0.50
1
800 1000
10
20
30
CYCLE FREQUENCY (MHz)
CAPACITANCE (pF)
Truth Table
CE
WE
OE
H
X
X
High Z
Inputs/Outputs
Deselect/power down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Deselect, output disabled
Active (ICC)
Document Number: 001-06512 Rev. *D
Mode
Power
Page 10 of 14
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CY62256VN
Ordering Information
Speed
(ns)
70
Ordering Code
Package
Diagram
CY62256VNLL-70ZXC
51-85071
28-pin TSOP I (Pb-free)
CY62256VNLL-70SNXI
51-85092
28-pin (300-mil) Narrow SOIC (Pb-free)
Package Type
CY62256VNLL-70ZXI
51-85071
28-pin TSOP I (Pb-free)
CY62256VNLL-70ZRXI
51-85074
28-pin Reverse TSOP I (Pb-free)
CY62256VNLL-70SNXE
51-85092
28-pin (300-mil) Narrow SOIC (Pb-free)
CY62256VNLL-70ZXE
51-85071
28-pin TSOP I (Pb-free)
Operating
Range
Commercial
Industrial
Automotive-E
Contact your local Cypress sales representative for availability of other parts
Ordering Code Definitions
CY 62 256 V
N LL - 70 XXX
X
Temperature Grade: X = C or I or E
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C;
E = Automotive-E = –40 °C to +125 °C
Package Type: XXX = ZX or SNX or ZRX
ZX = 28-pin TSOP I (Pb-free)
SNX = 28-pin Narrow SOIC (Pb-free)
ZRX = 28-pin Reverse TSOP I (Pb-free)
Speed Grade
Low Power
Nitride Seal Mask fix
Voltage Range (3 V Typical)
Density: 256 Kbit
MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-06512 Rev. *D
Page 11 of 14
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CY62256VN
Package Diagrams
Figure 8. 28-pin (300-mil) SNC (Narrow Body), 51-85092
51-85092 *C
Figure 9. 28-pin TSOP 1 (8 × 13.4 mm), 51-85071
51-85071 *H
Document Number: 001-06512 Rev. *D
Page 12 of 14
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CY62256VN
Figure 10. 28-pin Reverse TSOP 1 (8 × 13.4 mm), 51-85074
51-85074-*F
Document Number: 001-06512 Rev. *D
Page 13 of 14
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CY62256VN
Document History Page
Document Title: CY62256VN 256K (32K × 8) Static RAM
Document Number: 001-06512
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
426504
See ECN
NXR
New Data Sheet
*A
488954
See ECN
NXR
Added Automotive product
Updated ordering Information table
Description of Change
VKN/AESA Corrected VIL description in the Electrical Characteristics table
*B
2769239
09/25/09
*C
2901521
03/30/2010
AJU
Removed inactive parts from Ordering Information.
Updated Package Diagram
*D
3119519
01/04/2011
AJU
Updated Ordering Information.
Added Ordering Code Definitions.
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© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06512 Rev. *D
Revised January 4, 2011
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All products and company names mentioned in this document may be the trademarks of their respective holders.
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