Eorex EM488M1644VTC-75F 128mb (2mx4bankx16) synchronous dram Datasheet

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EM488M1644VTC
128Mb (2Mx4Bankx16) Synchronous DRAM
Feature
Description
• Fully synchronous to positive clock edge
The EM488M1644VTC is Synchronous
• Single 3.3V +/- 0.3V power supply
Dynamic Random Access Memory (SDRAM)
• LVTTL compatible with multiplexed address
organized as 2Meg words x 4 banks x 16
• Programmable Burst Length (B/ L) - 1,2,4, 8
bits.All inputs and outputs are synchronized
or full page
with the positive edge of the clock.
• Programmable CAS Latency (C/ L) - 2 or 3
The 128Mb SDRAM uses synchronized
• Data Mask (DQM) for Read / Write masking
pipelined architecture to achieve high
• Programmable wrap sequence
speed data transfer rates and is designed to
– Sequential (B/ L = 1/2/4/8/full page )
operate at 3.3V low power memory system.
– Interleave (B/ L = 1/2/4/8 )
• Burst read with single-bit write operation
It also provides auto refresh with power
• All inputs are sampled at the rising edge of
voltage levels are compatible with LVTTL.
saving / down mode. All inputs and outputs
the system clock.
Packages: TSOPII 54P 400mil
• Auto refresh and self refresh
• 4,096 refresh cycles / 64ms (15.625us)
Ordering Information
Part No
EM488M1644VTC –75F
EM488M1644VTC –7F
Organization
Max. Freq
8M X16
133MHz @CL3
8M X16
143MHz @CL3
Package
54pin TSOP (II)
54pin TSOP (II)
Power
Commercial
Commercial
* EOREX reserves the right to change products or specification without notice.
1
Pb
Free
Free
____________________________________________
EM488M1644VTC
Absolute Maximum Ratings
Symbol
VIN, VOUT
VDD, VDDQ
TOP
TSTG
PD
IOS
Item
Input, Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Power Dissipation
Short Circuit Current
Rating
-0.3 ~ 4.6
-0.3 ~ 4.6
0 ~ 70
-55 ~ 150
1
50
Units
V
V
°C
°C
W
mA
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operation Conditions ( Ta = 0 ~ 70 °C )
Symbol
VDD
VDDQ
VIH
VIL
Parameter
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Input logic high voltage
Input logic low voltage
Min.
3.0
3.0
2.0
-0.3
Typical
3.3
3.3
Typical
3.6
3.6
VDD+0.3
0.8
Units
V
V
V
V
Note : 1. All voltage referred to VSS.
2. VIH (max) = 5.6V for pulse width ≤3ns
3. VIL (min) = -2.0V for pulse width ≤ 3ns
Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25°C )
Symbol
CCLK
CI
Parameter
Clock capacitance
Input capacitance for CLK, CKE, Address, /CS,
Min.
2.5
2.5
Max.
3.5
3.8
Units
pF
pF
CO
/RAS, /CAS, /WE, DQML, DQMU
Input/Output capacitance
4.0
6.5
pF
2
EM488M1644VTC
____________________________________________
Recommended DC Operating Conditions
( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C )
Parameter
Operating current
Symbol
ICC1
Test condition
MAX
Units Notes
mA
mA
Burst length = 1,
1
85
tRC ≥ tRC (min), IOL = 0 mA,
One bank active
Precharge standby
current in power down
ICC2P
CKE ≤ VIL (max.), tCK= 15 ns
2.5
mA
ICC2PS
CKE ≤ VIL (max.), tCK= ∞
2.5
mA
ICC2N
CKE ≥ VIL (min.), tCK=15ns,
35
mA
10
mA
mode
Precharge standby
current in non-power
/CS ≥ VIH (min.) Input signals are
down mode
changed one time during 30ns
ICC2NS
CKE ≥ VIL (min.), tCK = ∞
Input signals are stable
Active standby current
in power down mode
Active standby current
ICC3P
CKE ≤ VIL (max), tCK = 15ns
10
mA
ICC3PS
CKE ≤ VIL (max), tCK = ∞
10
mA
ICC3N
CKE ≥ VIL (min), tCK = 15ns,
45
mA
35
mA
/CS ≥ VIH (min) Input signals are
in non-power down
mode
changed one time during 30ns
ICC3NS
CKE ≥ VIL (min), tCK = ∞
Input signals are stable
operating current
tCCD ≥ 2CLKs , IOL = 0 mA
ICC4
(Burst mode)
2
170
mA
3
3
mA
4
110
Refresh current
ICC5
tRC ≥ tRC(min.)
Self Refresh current
ICC6
CKE ≤ 0.2V
*
mA
All voltages referenced to Vss.
Note : 1. ICC1 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min)
2. ICC4 depends on output loading and cycle rates.
Specified values are obtained with the output open.
Input signals are changed only one time during tCK (min)
3. Input signals are changed only one time during tCK (min)
4. Standard power version.
3
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EM488M1644VTC
Recommended DC Operating Conditions (Continued)
Parameter
Input leakage current
Symbol
Test condition
IIL
0 ≤ VI ≤ VDDQ, VDDQ=VDD
Output leakage current
High level output voltage
Low level output voltage
IOL
VOH
VOL
All other pins not under test=0 V
0 ≤ VO ≤ VDDQ, DOUT is disabled
Io = -4mA
Io = +4mA
Min.
-0.5
Max.
+0.5
Unit
uA
-0.5
2.4
+0.5
uA
V
V
0.4
AC Operating Test Conditions
( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70°C )
Output Reference Level
Output Load
Input Signal Level
Transition Time of Input Signals
Input Reference Level
1.4V / 1.4V
See diagram as below
2.4V / 0.4V
2ns
1.4V
4
EM488M1644VTC
____________________________________________
Operating AC Characteristics
( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C)
Parameter
Symbol
-7
-7.5
Units
Notes
Min. Max. Min. Max.
Clock cycle time
CL = 3
tCK
Access time from CLK
CL = 2
CL = 3
tAC
7
7.5
7.5
10
5.4
CL = 2
ns
5.4
5.4
6
ns
ns
CLK high level width
tCH
2.5
2.5
ns
ns
CLK low level width
tCL
2.5
2.5
ns
3
ns
Data-out hold time
CL = 3
tOH
3
Data-out high impedance time
CL = 2
CL = 3
tHZ
3
Data-out low impedance time
tLZ
0
0
ns
ns
Input hold time
tIH
1
1
ns
Input setup time
tIS
1.5
1.5
ns
ACTIVE to ACTIVE command period
tRC
62
67
ns
2
ACTIVE to PRECHARGE command period
tRAS
42
ns
2
PRECHARGE to ACTIVE command period
tRP
3
3
CLK
2
ACTIVE to READ/WRITE delay time
tRCD
3
3
CLK
2
ACTIVE(one) to ACTIVE(another) command
tRRD
2
2
CLK
2
READ/WRITE command to READ/WRITE
tCCD
1
1
CLK
command
Data-in to PRECHARGE command
tDPL
2
2
CLK
Data-in to BURST stop command
tBDL
1
1
CLK
tROH
3
3
CLK
7
3
7
CL = 2
Data-out to high impedance
from PRECHARGE command
CL = 3
CL = 2
Refresh time(4,096 cycle)
100k
2
tEF
45
2
64
* All voltages referenced to Vss.
Note : 1. tHZ defines the time at which the output achieve the open circuit
condition and is not referenced to output voltage levels.
2. These parameters account for the number of clock cycles and
depend on the operating frequency of the clock, as follows :
The number of clock cycles = Specified value of timing/clock period
(Count fractions as a whole number)
5
100k
64
ns
ns
CLK
ms
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EM488M1644VTC
DOi
Block Diagram
6
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EM488M1644VTC
Pin Assignment : TSOP 54P
x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
54pin TSOP-II
(400mil x 875mil)
7
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
____________________________________________
EM488M1644VTC
Pin Descriptions (Simplified)
Name
Pin Function
CLK
Pin
System Clock
Master Clock Input(Active on the Positive rising edge)
/CS
Chip select
Selects chip when active
CKE
Clock Enable
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
A0 ~ A11
Address
Row address (A0 to A11) is determined by A0 to A11 level at the
bank active command cycle CLK rising edge.
CA (CA0 to CA8) is determined by A0 to A8 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the precharge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
BA0, BA1
Bank Address
Selects which bank is to be active.
/RAS
Row address strobe
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
/CAS
Column address strobe Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
/WE
Write Enable
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
UDQM / LDQM Data input/output Mask DQM controls I/O buffers.
DQ0 ~ 15
Data input/output
DQ pins have the same function as I/O pins on a conventional
DRAM.
VDD / VSS
Power supply / Ground VDD and VSS are power supply pins for internal circuits.
VDDQ / VSSQ
Power supply / Ground VDDQ and VSSQ are power supply pins for the output buffers.
NC
No connection
This pin is recommended to be left No Connection on the device.
8
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Simplified State Diagram
9
EM488M1644VTC
EM488M1644VTC
____________________________________________
Address Input for Mode Register Set
BA1
BA0
A11
A10
A9
A8
A7
A6
Operation Mode
A5
A4
Cas Latency
BT
Sequential
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Burst Type
Interleave
Sequential
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
BA1
0
0
BA0
0
0
A11
0
0
A10
0
0
A9
0
1
A6
0
0
0
0
1
1
1
1
A8
0
0
10
A2
A1
A0
Burst Length
Burst Length
Interleave
A2
1
0
2
0
4
0
8
0
Reserved
1
Reserved
1
Reserved
1
Reserved
1
A1
0
0
1
1
0
0
1
1
A3
1
0
A5
0
0
1
1
0
0
1
1
A7
0
0
A3
A4
0
1
0
1
0
1
0
1
Operation Mode
Normal
Burst read with Single-bit Write
A0
0
1
0
1
0
1
0
1
____________________________________________
EM488M1644VTC
Burst Type ( A3 )
Burst Length
2
4
8
Full Page *
A2
X
X
X
X
X
X
0
0
0
0
1
1
1
1
n
A1 A0
X
0
X
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
n
n
Sequential Addressing
01
10
0123
1230
2301
3012
01234567
12345670
23456701
34567012
45670123
56701234
67012345
70123456
Cn Cn+1 Cn+2 …...
* Page length is a function of I/O organization and column addressing
X16 (CA0 ~ CA8) : Full page = 512bits
11
Interleave Addressing
01
10
0123
1032
2301
3210
01234567
10325476
23016745
32107654
45670123
54761032
67452301
76543210
-
EM488M1644VTC
____________________________________________
Truth Table
1.Command Truth Table
Command
Symbol
CKE
/CS
n-1
n
/RAS /CAS
/WE
BA0,
A10
BA1
A11,
A9~A0
Ignore Command
DESL
H
X
H
X
X
X
X
X
X
No operation
NOP
H
X
L
H
H
H
X
X
X
Burst stop
BSTH
H
X
L
H
H
L
X
X
X
Read
READ
H
X
L
H
L
H
V
L
V
Read with auto pre-charge READA
H
X
L
H
L
H
V
H
V
Write
WRIT
H
X
L
H
L
L
V
L
V
Write with auto pre-charge
WRITA
H
X
L
L
H
H
V
H
V
ACT
H
X
L
L
H
H
V
V
V
Pre-charge select bank
PRE
H
X
L
L
H
L
V
L
X
Pre-charge all banks
PALL
H
X
L
L
H
L
X
H
X
Mode register set
MRS
H
X
L
L
L
L
L
L
V
Bank activate
2. DQM Truth Table
Command
Symbol
CKE
/CS
n-1
n
Data write / output enable
ENB
H
x
H
Data mask / output disable
MASK
H
x
L
Upper byte write enable / output enable
BSTH
H
H
x
L
Read
READ
H
x
L
Read with auto pre-charge
READA
H
x
L
Write
WRIT
H
x
L
Write with auto pre-charge
WRITA
H
x
L
Bank activate
ACT
H
x
L
Pre-charge select bank
PRE
H
x
L
Pre-charge all banks
PALL
H
x
L
Mode register set
MRS
H
x
L
3. CKE Truth Table
Command
Command
Symbol
CKE
/CS
/RAS /CAS
/WE
Addr.
n-1
n
Activating
Clock suspend mode entry
H
L
X
X
X
X
X
Any
Clock suspend mode
L
L
X
X
X
X
X
L
H
X
X
X
X
X
Clock suspend Clock suspend mode exit
Idle
CBR refresh command
REF
H
H
L
L
L
H
X
Idle
Self refresh entry
SELF
H
L
L
L
L
H
X
Self refresh
Self refresh exit
L
H
L
H
H
H
X
L
H
H
X
X
X
X
Idle
Power down entry
H
L
X
X
X
X
X
Power down
Power down exit
L
H
X
X
X
X
X
Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
12
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EM488M1644VTC
4. Operative Command Table
Current /CS /R
state
Idle
/C
/W
Addr.
Command
DESL
H
X
X
X
X
L
H
H
X
X
L
H
L
L
H
L
L
L
L
L
L
L
Action
Notes
Nop or power down
2
NOP or BST Nop or power down
READ/READA
H BA/CA/A10
ILLEGAL
2
3
H
L BA/CA/A10 WRIT/WRITA ILLEGAL
ACT
H
BA/RA
Row activating
H
L
L
L
L
L
BA, A10
PRE/PALL
Nop
H
X
REF/SELF
Refresh or self refresh
L
Op-Code
MRS
Mode register accessing
DESL
Nop
3
4
Row
H
X
X
X
X
active
L
H
H
X
X
L
H
L
H BA/CA/A10 READ/READA Begin read : Determine AP
5
L
H
L
L BA/CA/A10 WRIT/WRITA Begin write : Determine AP
5
L
L
H
H
BA/RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Pre-charge
6
L
L
L
H
X
REF/SELF
ILLEGAL
4
L
L
L
L
Op-Code
MRS
ILLEGAL
Read
Write
NOP or BST Nop
H
X
X
X
X
DESL
Continue burst to end→ Row active
L
H
H
H
X
NOP
Continue burst to end→ Row active
L
H
H
L
X
BST
Burst stop→ Row active
L
H
L
H BA/CA/A10 READ/READA Terminate burst, new read : Determine AP
7
L
L
L
L BA/CA/A10 WRIT/WRITA Terminate burst, start write : Determine AP
7.8
L
L
H
H
BA/RA
L
L
H
L
BA/A10
L
L
L
H
X
ACT
ILLEGAL
3
PRE/PALL
Terminate burst, pre-charging
4
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end→ Write recovering
L
H
H
H
X
NOP
Continue burst to end→ Write recovering
L
H
H
L
X
BST
Burst stop→ Row active
L
H
L
L
L
L
L
L
H
H BA/CA/A10 READ/READA Terminate burst, start read: Determine AP 7, 8
L BA/CA/A10 WRIT/WRITA Terminate burst, new write: Determine AP 7
ILLEGAL
H
BA/RA
ACT
L
L
H
L
L
L
L
L
L
L
BA/A10
PRE/PALL
Terminate burst, pre-charging
H
X
REF/SELF
ILLEGAL
L
Op-Code
MRS
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care)
13
7.8
7
3
9
____________________________________________
Current
state
/CS /R
/C
EM488M1644VTC
/W
Addr.
Command
Action
Notes
Read with AP H
X
X
X
X
DESL
Continue burst to end→ Pre-charging
L
H
H
H
X
NOP
Continue burst to end→ Pre-charging
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA/CA/A10 READ/READA ILLEGAL
3
L
H
L
L
BA/CA/A10 WRIT/WRITA ILLEGAL
3
L
L
H
H
BA/RA
L
L
H
L
L
L
L
H
Write with
AP
Pre-charging
Row
activating
ACT
ILLEGAL
3
BA, A10
PRE/PALL
ILLEGAL
3
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
burst to end→ Write
recovering with auto pre-charge
L
H
H
H
X
NOP
Continue burst to end→ Write
recovering with auto pre-charge
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA/CA/A10 READ/READA ILLEGAL
3
L
H
L
L
BA/CA/A10 WRIT/WRITA ILLEGAL
3
L
L
H
H
BA/RA
L
L
H
L
L
L
L
H
ACT
ILLEGAL
3
BA, A10
PRE/PALL
ILLEGAL
3
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop→ Enter idle after tRP
L
H
H
H
X
NOP
Nop→ Enter idle after tRP
L
H
H
L
X
L
H
L
H
L
H
L
L
L
L
H
H
BA/RA
L
L
H
L
BA, A10
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
BST
ILLEGAL
READ/READA
BA/CA/A10
ILLEGAL
BA/CA/A10 WRIT/WRITA ILLEGAL
ACT
PRE/PALL
ILLEGAL
3
3
3
Nop→ Enter idle after tRP
H
X
X
X
X
DESL
Nop→ Enter idle after tRCD
L
H
H
H
X
NOP
L
H
H
L
Nop→ Enter idle after tRCD
ILLEGAL
L
H
L
H
L
H
L
L
L
L
H
H
BA/RA
L
L
H
L
L
L
L
L
L
L
X
BST
BA/CA/A10 READ/READA ILLEGAL
BA/CA/A10 WRIT/WRITA ILLEGAL
3
3
ILLEGAL
3.1
BA, A10
ACT
PRE/PALL
ILLEGAL
3
H
X
REF/SELF
ILLEGAL
L
Op-Code
MRS
ILLEGAL
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
14
____________________________________________
Current
/CS /R
/C /W
Addr.
Command
EM488M1644VTC
Action
Notes
state
Write
H
recovering L
X
X
X
X
DESL
Nop→ Enter row active after tDPL
H
H
H
X
NOP
Nop→ Enter row active after tDPL
L
H
H
L
X
BST
Nop→ Enter row active after tDPL
L
H
L
H
BA/CA/A10 READ/READA
L
H
L
L
BA/CA/A10
L
L
H
H
BA/RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
Write
H
recovering L
X
X
X
X
DESL
ILLEGAL
Nop→ Enter pre-charge after tDPL
H
H
H
X
NOP
Nop→ Enter pre-charge after tDPL
L
H
H
L
X
BST
Nop→ Enter pre-charge after tDPL
L
H
L
H
BA/CA/A10 READ/READA ILLEGAL
L
H
L
L
BA/CA/A10
L
L
H
H
BA/RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
X
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
with AP
Refreshing H
Mode
Register
WRIT/WRITA ILLEGAL
X X
X
X
DESL
Nop→ Enter idle after tRC
L
H
H
X
X
NOP/ BST
Nop→ Enter idle after tRC
L
H
L
X
X
L
L
H
X
X
ACT/PRE/PALL ILLEGAL
REF/SELF/MRS ILLEGAL
READ/WRIT
8
3.8
3
3
ILLEGAL
L
L
L
X
X
H
X
X
X
X
DESL
Nop
L
Accessing
Start read, Determine AP
WRIT/WRITA New write, Determine AP
H
H
H
X
NOP
Nop
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRIT
ILLEGAL
L
L
X
X
X
ACT/PRE/PALL/ ILLEGAL
REF/SELF/MRS
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge
Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states;Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don't satisfy tDPL.
10. Illegal if tRRD is not satisfied.
15
____________________________________________
EM488M1644VTC
5. Command Truth Table for CKE
Current
CKE
/CS /R
/C
/W
Addr.
Action
Notes
state
n-1 n
Self refresh H X
Self refresh
recovery
X
X
X
X
X
INVALID, CLK (n – 1) would exit self refresh
L
H
H
X
X
X
X
Self refresh recovery
L
H
L
H
H
X
X
Self refresh recovery
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
Maintain self refresh
H
H
H
X
X
X
X
Idle after tRC
H
H
L
H
H
X
X
Idle after tRC
H
H
L
H
L
X
X
ILLEGAL
H
H
L
L
X
X
X
ILLEGAL
H
L
H
X
X
X
X
ILLEGAL
H
L
L
H
H
X
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
Power
down
H
X
X
X
X
X
X
INVALID, CLK(n-1) would exit power down
L
H
X
X
X
X
X
Exit power down→ Idle
L
L
X
X
X
X
X
Maintain power down mode
Both banks
H
H
H
X
X
X
Refer to operations in Operative Command Table
H
H
L
H
X
X
Refer to operations in Operative Command Table
H
H
L
L
H
X
Refer to operations in Operative Command Table
H
H
L
L
L
H
H
H
L
L
L
L Op-Code Refer to operations in Operative Command Table
H
L
H
X
X
X
Refer to operations in Operative Command Table
H
L
L
H
X
X
Refer to operations in Operative Command Table
H
L
L
L
H
X
H
L
L
L
L
H
idle
X
Refresh
Refer to operations in Operative Command Table
X
Self refresh
H
L
L
L
L
L Op-Code Refer to operations in Operative Command Table
L
X
X
X
X
X
X
Power down
H
X
X
X
X
X
X
Refer to operations in Operative Command Table
L
X
X
X
X
X
X
Power down
H
H
X
X
X
X
H
L
X
X
X
X
X
Begin clock suspend next cycle
L
H
X
X
X
X
X
Exit clock suspend next cycle
listed above L
L
X
X
X
X
X
Maintain clock suspend
Row active
Any state
other than
1
1
1
Refer to operations in Operative Command Table
Remark : H = High level, L = Low level, X = High or Low level (Don't care)
Notes: 1. Self refresh can be entered only from the both banks idle state.
Power down can be entered only from both banks idle or row active state.
2. Must be legal command as defined in Operative Command Tabl
16
2
____________________________________________
EM488M1644VTC
Recommended Power On and Initialization :
The following power on and initialization sequence guarantees the device is preconditioned to
each users specific needs.(Like a conventional DRAM)
During power on, all VDD and VDDQ pins must be built up simultaneously to the specified
voltage when the input signals are held in the “NOP” state.
The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies.
(CLK signal started at same time)
After power on, an initial pause of 200 µs is required followed by a precharge of all banks
using the precharge command.
To prevent data contention on the DQ bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause period.
Once all banks have been precharged, the Mode Register Set Command must be issued to
initialize the Mode Register.
A minimum of eight Auto Refresh cycles (CBR) are also required, and these may be done
before or after programming the Mode Register.
17
____________________________________________
Package Drawing :
TSOPII 54P
18
EM488M1644VTC
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