FUJITSU SEMICONDUCTOR DATA SHEET DS05-50202-2E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 16M ( × 8/ × 16) FLASH MEMORY & 4M ( × 8/ × 16) STATIC RAM MB84VD2118XA-85/MB84VD2119XA-85 ■ FEATURES • Power supply voltage of 2.7 to 3.6 V • High performance 85 ns maximum access time • Operating Temperature −25 to +85 °C • Package 69-ball FBGA, 56-pin TSOP(I) (Continued) ■ PRODUCT LINE UP Flash Memory Ordering Part No. VCCf, VCCs = 3.0 V +0.6 V −0.3 V SRAM MB84VD2118XA-85/MB84VD2119XA-85 Max. Address Access Time (ns) 85 85 Max. CE Access Time (ns) 85 85 Max. OE Access Time (ns) 35 45 ■ PACKAGES 69-ball plastic FBGA 56-pin plastic TSOP(I) (BGA-69P-M02) (FPT-56P-M04) MB84VD2118XA-85/MB84VD2119XA-85 (Continued) 1. FLASH MEMORY • Simultaneous Read/Write operations (dual bank) Miltiple devices available with different bank sizes (Refer to “PIN DESCRIPTION”) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program • Minimum 100,000 write/erase cycles • Sector erase architecture Eight 4 K words and thirty one 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture MB84VD2118XA : Top sector MB84VD2119XA : Bottom sector • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. • Low VCCf write inhibit ≤ 2.5 V • Hidden ROM (Hi-ROM) region 64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status (MB84VD2118XA : SA37, SA38 MB84VD2119XA : SA0, SA1) At VIH, allows removal of boot sector protection At VACC, program time will reduse by 40%. • Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device • Please refer to “MBM29DL16XTD/BD” data sheet in detailed function 2. SRAM • Power dissipation Operating : 40 mA max. Standby : 7 µA max. • Power down features using CE1s and CE2s • Data retention supply voltage : 1.5 V to 3.6 V • CE1s and CE2s Chip Select • Byte data control : LBs (DQ0 to DQ7) , UBs (DQ8 to DQ15) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MB84VD2118XA-85/MB84VD2119XA-85 ■ PIN ASSIGNMENTS (Top View) A N.C. B N.C. N.C. N.C. N.C. A7 LBS WP/ ACC WE A8 A11 C A3 A6 UBS RESET CE2S A19 A12 A15 D A2 A5 A18 RY/BY N.C. A9 A13 N.C. E N.C. A1 A4 A17 A10 A14 N.C. N.C. F N.C. A0 VSS DQ1 DQ6 SA A16 N.C. G CEf OE DQ9 DQ3 DQ4 DQ13 DQ15/ A−1 CIOf H CE1S DQ0 DQ10 VCCf VCCs DQ12 DQ7 VSS DQ8 DQ2 DQ11 CIOS DQ5 DQ14 N.C. N.C. 5 6 J K N.C. 1 2 3 4 N.C. 7 8 9 10 69-ball FBGA 3 MB84VD2118XA-85/MB84VD2119XA-85 (Top View) N.C. 1 56 A16 A15 2 55 CIOf A14 3 54 VSS A13 4 53 SA A12 5 52 DQ15/A-1 A11 6 51 DQ7 A10 7 50 DQ14 A9 8 49 DQ6 A8 9 48 DQ13 A19 10 47 DQ5 N.C. 11 46 DQ12 WE 12 45 DQ4 CE2s 13 44 CIOs RESET 14 43 VCCs WP/ACC 15 42 VCCf RY/BY 16 41 DQ11 UBs 17 40 DQ3 LBs 18 39 DQ10 A18 19 38 DQ2 A17 20 37 DQ9 A7 21 36 DQ1 A6 22 35 DQ8 A5 23 34 DQ0 A4 24 33 OE A3 25 32 VSS A2 26 31 CE1s A1 27 30 CEf N.C. 28 29 A0 56-pin TSOP(I) 4 MB84VD2118XA-85/MB84VD2119XA-85 ■ PIN DESCRIPTION Pin A0 to A17 Function Input/Output Address Inputs (Common) I A-1, A18, A19 Address Input (Flash) I SA Address Input (SRAM) I DQ0 to DQ15 Data Inputs/Outputs (Common) I/O CEf Chip Enable (Flash) I CE1s Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I WE Write Enable (Common) I Ready/Busy Outputs (Flash) Open Drain Output O UBs Upper Byte Control (SRAM) I LBs Lower Byte Control (SRAM) I CIOf I/O Configuration (Flash) CIOf = VIH is Word mode ( × 16), CIOf = VIL is Byte mode ( × 8) I CIOs I/O Configuration (SRAM) CIOs = VIH is Word mode ( × 16), CIOs = VIL is Byte mode ( × 8) I Hardware Reset Pin/Sector Protection Unlock (Flash) I Write Protect / Acceleration (Flash) I RY/BY RESET WP/ACC N.C. No Internal Connection VSS Device Ground (Common) Power VCCf Device Power Supply (Flash) Power VCCs Device Power Supply (SRAM) Power 5 MB84VD2118XA-85/MB84VD2119XA-85 ■ BLOCK DIAGRAM VCCf VSS A0 to A19 RY/BY A0 to A19 A-1 WP/ACC RESET CEf CIOf 16 M bit Flash Memory DQ0 to DQ15/A-1 DQ0 to DQ15/A-1 VCCs VSS A0 to A17 DQ0 to DQ15/A-1 SA LBs UBs WE OE CE1s CE2s CIOs 6 4 M bit Static RAM MB84VD2118XA-85/MB84VD2119XA-85 ■ DEVICE BUS OPERATIONS Table 2.1 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Word mode; CIOs = VCCs) Operation (Note 1, 3) Full Standby CEf CE1s CE2s OE H H Output Disable L Read from Flash (Note 2) L Write to Flash L Read from SRAM Write to SRAM H H Temporary Sector Group Unprotection (Note 4) X Flash Hardware Reset X Boot Block Sector Write Protection X H X X L L H H X X L H X X L H X X L L L H H X X H X X L X X WE SA LBs UBs (Note 6) DQ0 to DQ7 DQ8 to DQ15 RESET WP/ ACC (Note 5) H X H X X X X X X HIGH-Z HIGH-Z H H X X X HIGH-Z HIGH-Z X X X H H HIGH-Z HIGH-Z H H X X X HIGH-Z HIGH-Z L H X X X DOUT DOUT H X H L X X X DIN DIN H X L L DOUT DOUT H L HIGH-Z DOUT H X L H DOUT HIGH-Z L L DIN DIN H L HIGH-Z DIN H X L H DIN HIGH-Z L X H L X X X X X X X X X VID X X X X X X HIGH-Z HIGH-Z L X X X X X X X X X L Legend: L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for voltage levels. Notes : 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4. It is also used for the extended sector group protections. 5. WP/ACC = VIL ; protection of boot sectors. WP/ACC = VIH ; removal of boot sectors protection. WP/ACC = VACC (9V) ; Program time will reduce by 40%. 6. SA ; Don’t care or Open. 7 MB84VD2118XA-85/MB84VD2119XA-85 Table 2.2 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Byte mode; CIOs = VSS) Operation (Note 1, 3) Full Standby CEf CE1s CE2s OE H H Output Disable L H X X L L H H X X L H X X L H X X L WE SA LBs UBs (Note 6) (Note 6) DQ0 to DQ7 DQ8 to RESET DQ15 X X X X X HIGH-Z HIGH-Z H H X X X HIGH-Z HIGH-Z X X X X X HIGH-Z HIGH-Z H H X X X HIGH-Z HIGH-Z L H X X X DOUT H L X X X WP/ ACC (Note 5) H X H X DOUT H X DIN DIN H X Read from Flash (Note 2) L Write to Flash L Read from SRAM H L H L H SA X X DOUT HIGH-Z H X Write to SRAM H L H X L SA X X DIN HIGH-Z H X Temporary Sector Group Unprotection (Note 4) X X X X X X X X X X VID X Flash Hardware Reset X H X X L X X X X X L X Boot Block Sector Write Protection X X X X X X X X X L HIGH-Z HIGH-Z X X Legend: L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for voltage levels. Notes : 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4. It is also used for the extended sector group protections. 5. WP/ACC = VIL ; protection of boot sectors. WP/ACC = VIH ; removal of boot sectors protection. WP/ACC = VACC (9V) ; Program time will reduce by 40%. 6. LBS , UBS ; Don’t care or Open. 8 MB84VD2118XA-85/MB84VD2119XA-85 Table 2.3 User Bus Operations (Flash = Byte mode; CIOf = VSS, SRAM = Byte mode; CIOs = VSS) Operation (Note 1, 3) Full Standby CEf CE1s CE2s H H Output Disable L H X X L L H H X X L H X X L H X X L DQ1/ LBs UBs DQ0 to OE WE SA A-1 (Note 6) (Note 6) DQ7 DQ8 to RESET DQ14 X X X X X X HIGH-Z HIGH-Z X H H X X X HIGH-Z HIGH-Z X X X X X X HIGH-Z HIGH-Z A-1 H H X X X HIGH-Z HIGH-Z A-1 L H X X X DOUT A-1 H L X X X WP/ ACC (Note 5) H X H X X H X DIN X H X Read from Flash (Note 2) L Write to Flash L Read from SRAM H L H X L H SA X X DOUT HIGH-Z H X Write to SRAM H L H X X L SA X X DIN HIGH-Z H X Temporary Sector Group Unprotection (Note 4) X X X X X X X X X X X VID X Flash Hardware Reset H X X X L X X X X X X L X Boot Block Sector Write Protection X X X X X X X X X X L HIGH-Z HIGH-Z X X Legend: L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for voltage levels. Notes : 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4. It is also used for the extended sector group protections. 5. WP/ACC = VIL ; protection of boot sectors. WP/ACC = VIH ; removal of boot sectors protection. WP/ACC = VACC (9V) ; Program time will reduce by 40%. 6. LBS, UBS ; Don’t care or Open. 9 MB84VD2118XA-85/MB84VD2119XA-85 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY • Eight 4 K words, and thirty one 32 K words. • Individual-sector, multiple-sector, or bulk-erase capability. Word mode Byte mode SA38 : SA37 : SA36 : Bank 1 SA35 : MB84VD21181A SA34 : SA33 : Bank 1 SA32 : MB84VD21182A SA31 : SA30 : Bank 1 SA29 : MB84VD21183A SA28 : SA27 : Bank 1 SA26 : MB84VD21184A SA25 : SA24 : SA23 : SA22 : SA21 : SA20 : SA19 : SA18 : SA17 : SA16 : SA15 : Bank 2 SA14 : MB84VD21181A SA13 : SA12 : Bank 2 SA11 : MB84VD21182A SA10 : SA9 : Bank 2 SA8 : MB84VD21183A SA7 : Bank 2 SA6 : MB84VD21184A SA5 : SA4 : SA3 : SA2 : SA1 : SA0 : 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) MB84VD2118XA Sector Architecture (Top Boot Block) 10 0FFFFFH 0FF000H 0FE000H 0FD000H 0FC000H 0FB000H 0FA000H 0F9000H 0F8000H 0F0000H 0E8000H 0E0000H 0D8000H 0D0000H 0C8000H 0C0000H 0B8000H 0B0000H 0A8000H 0A0000H 098000H 090000H 088000H 080000H 078000H 070000H 068000H 060000H 058000H 050000H 048000H 040000H 038000H 030000H 028000H 020000H 018000H 010000H 008000H 000000H 1FFFFFH 1FE000H 1FC000H 1FA000H 1F8000H 1F6000H 1F4000H 1F2000H 1F0000H 1E0000H 1D0000H 1C0000H 1B0000H 1A0000H 190000H 180000H 170000H 160000H 150000H 140000H 130000H 120000H 110000H 100000H 0F0000H 0E0000H 0D0000H 0C0000H 0B0000H 0A0000H 090000H 080000H 070000H 060000H 050000H 040000H 030000H 020000H 010000H 000000H MB84VD2118XA-85/MB84VD2119XA-85 • Eight 4 K words, and thirty one 32 K words. • Individual-sector, multiple-sector, or bulk-erase capability. Word mode Byte mode SA38 : SA37 : SA36 : Bank 2 SA35 : MB84VD21194A SA34 : SA33 : Bank 2 SA32 : MB84VD21193A SA31 : SA30 : Bank 2 SA29 : MB84VD21192A SA28 : SA27 : Bank 2 SA26 : MB84VD21191A SA25 : SA24 : SA23 : SA22 : SA21 : SA20 : SA19 : SA18 : SA17 : SA16 : SA15 : SA14 : SA13 : SA12 : Bank 1 SA11 : MB84VD21194A SA10 : SA9 : Bank 1 SA8 : MB84VD21193A SA7 : SA6 : Bank 1 SA5 : MB84VD21192A SA4 : Bank 1 SA3 : MB84VD21191A SA2 : SA1 : SA0 : 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB 8KB (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (32KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) (4KW) 0FFFFFH 0F8000H 0F0000H 0E8000H 0E0000H 0D8000H 0D0000H 0C8000H 0C0000H 0B8000H 0B0000H 0A8000H 0A0000H 098000H 090000H 088000H 080000H 078000H 070000H 068000H 060000H 058000H 050000H 048000H 040000H 038000H 030000H 028000H 020000H 018000H 010000H 008000H 007000H 006000H 005000H 004000H 003000H 002000H 001000H 000000H 1FFFFFH 1F0000H 1E0000H 1D0000H 1C0000H 1B0000H 1A0000H 190000H 180000H 170000H 160000H 150000H 140000H 130000H 120000H 110000H 100000H 0F0000H 0E0000H 0D0000H 0C0000H 0B0000H 0A0000H 090000H 080000H 070000H 060000H 050000H 040000H 030000H 020000H 010000H 00E000H 00C000H 00A000H 008000H 006000H 004000H 002000H 000000H MB84VD2119XA Sector Architecture (Bottom Boot Block) 11 MB84VD2118XA-85/MB84VD2119XA-85 Table 3.1 Sector Address Tables (MB84VD21181) Sector Address Bank Bank 2 Bank 1 12 Sector Bank Address Address Range (Byte mode) Address Range (Word mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 X X X 000000H to 00FFFFH 000000H to 007FFFH SA1 0 0 0 0 1 X X X 010000H to 01FFFFH 008000H to 00FFFFH SA2 0 0 0 1 0 X X X 020000H to 02FFFFH 010000H to 017FFFH SA3 0 0 0 1 1 X X X 030000H to 03FFFFH 018000H to 01FFFFH SA4 0 0 1 0 0 X X X 040000H to 04FFFFH 020000H to 027FFFH SA5 0 0 1 0 1 X X X 050000H to 05FFFFH 028000H to 02FFFFH SA6 0 0 1 1 0 X X X 060000H to 06FFFFH 030000H to 037FFFH SA7 0 0 1 1 1 X X X 070000H to 07FFFFH 038000H to 03FFFFH SA8 0 1 0 0 0 X X X 080000H to 08FFFFH 040000H to 047FFFH SA9 0 1 0 0 1 X X X 090000H to 09FFFFH 048000H to 04FFFFH SA10 0 1 0 1 0 X X X 0A0000H to 0AFFFFH 050000H to 057FFFH SA11 0 1 0 1 1 X X X 0B0000H to 0BFFFFH 058000H to 05FFFFH SA12 0 1 1 0 0 X X X 0C0000H to 0CFFFFH 060000H to 067FFFH SA13 0 1 1 0 1 X X X 0D0000H to 0DFFFFH 068000H to 06FFFFH SA14 0 1 1 1 0 X X X 0E0000H to 0EFFFFH 070000H to 077FFFH SA15 0 1 1 1 1 X X X 0F0000H to 0FFFFFH 078000H to 07FFFFH SA16 1 0 0 0 0 X X X 100000H to 10FFFFH 080000H to 087FFFH SA17 1 0 0 0 1 X X X 110000H to 11FFFFH 088000H to 08FFFFH SA18 1 0 0 1 0 X X X 120000H to 12FFFFH 090000H to 097FFFH SA19 1 0 0 1 1 X X X 130000H to 13FFFFH 098000H to 09FFFFH SA20 1 0 1 0 0 X X X 140000H to 14FFFFH 0A0000H to 0A7FFFH SA21 1 0 1 0 1 X X X 150000H to 15FFFFH 0A8000H to 0AFFFFH SA22 1 0 1 1 0 X X X 160000H to 16FFFFH 0B0000H to 0B7FFFH SA23 1 0 1 1 1 X X X 170000H to 17FFFFH 0B8000H to 0BFFFFH SA24 1 1 0 0 0 X X X 180000H to 18FFFFH 0C0000H to 0C7FFFH SA25 1 1 0 0 1 X X X 190000H to 19FFFFH 0C8000H to 0CFFFFH SA26 1 1 0 1 0 X X X 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH SA27 1 1 0 1 1 X X X 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH SA28 1 1 1 0 0 X X X 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH SA29 1 1 1 0 1 X X X 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH SA30 1 1 1 1 0 X X X 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH SA31 1 1 1 1 1 0 0 0 1F0000H to 1F1FFFH 0F8000H to 0F8FFFH SA32 1 1 1 1 1 0 0 1 1F2000H to 1F3FFFH 0F9000H to 0F9FFFH SA33 1 1 1 1 1 0 1 0 1F4000H to 1F5FFFH 0FA000H to 0FAFFFH SA34 1 1 1 1 1 0 1 1 1F6000H to 1F7FFFH 0FB000H to 0FBFFFH SA35 1 1 1 1 1 1 0 0 1F8000H to 1F9FFFH 0FC000H to 0FCFFFH SA36 1 1 1 1 1 1 0 1 1FA000H to 1FBFFFH 0FD000H to 0FDFFFH SA37 1 1 1 1 1 1 1 0 1FC000H to 1FDFFFH 0FE000H to 0FEFFFH SA38 1 1 1 1 1 1 1 1 1FE000H to 1FFFFFH 0FF000H to 0FFFFFH MB84VD2118XA-85/MB84VD2119XA-85 Table 3.2 Sector Address Tables (MB84VD21191) Sector Address Bank Bank 1 Bank 2 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 0 0 0 000000H to 001FFFH 000000H to 000FFFH SA1 0 0 0 0 0 0 0 1 002000H to 003FFFH 001000H to 001FFFH SA2 0 0 0 0 0 0 1 0 004000H to 005FFFH 002000H to 002FFFH SA3 0 0 0 0 0 0 1 1 006000H to 007FFFH 003000H to 003FFFH SA4 0 0 0 0 0 1 0 0 008000H to 009FFFH 004000H to 004FFFH SA5 0 0 0 0 0 1 0 1 00A000H to 00BFFFH 005000H to 005FFFH SA6 0 0 0 0 0 1 1 0 00C000H to 00DFFFH 006000H to 006FFFH SA7 0 0 0 0 0 1 1 1 00E000H to 00FFFFH 007000H to 007FFFH SA8 0 0 0 0 1 X X X 010000H to 01FFFFH 008000H to 00FFFFH SA9 0 0 0 1 0 X X X 020000H to 02FFFFH 010000H to 017FFFH SA10 0 0 0 1 1 X X X 030000H to 03FFFFH 018000H to 01FFFFH SA11 0 0 1 0 0 X X X 040000H to 04FFFFH 020000H to 027FFFH SA12 0 0 1 0 1 X X X 050000H to 05FFFFH 028000H to 02FFFFH SA13 0 0 1 1 0 X X X 060000H to 06FFFFH 030000H to 037FFFH SA14 0 0 1 1 1 X X X 070000H to 07FFFFH 038000H to 03FFFFH SA15 0 1 0 0 0 X X X 080000H to 08FFFFH 040000H to 047FFFH SA16 0 1 0 0 1 X X X 090000H to 09FFFFH 048000H to 04FFFFH SA17 0 1 0 1 0 X X X 0A0000H to 0AFFFFH 050000H to 057FFFH SA18 0 1 0 1 1 X X X 0B0000H to 0BFFFFH 058000H to 05FFFFH SA19 0 1 1 0 0 X X X 0C0000H to 0CFFFFH 060000H to 067FFFH SA20 0 1 1 0 1 X X X 0D0000H to 0DFFFFH 068000H to 06FFFFH SA21 0 1 1 1 0 X X X 0E0000H to 0EFFFFH 070000H to 077FFFH SA22 0 1 1 1 1 X X X 0F0000H to 0FFFFFH 078000H to 07FFFFH SA23 1 0 0 0 0 X X X 100000H to 10FFFFH 080000H to 087FFFH SA24 1 0 0 0 1 X X X 110000H to 11FFFFH 088000H to 08FFFFH SA25 1 0 0 1 0 X X X 120000H to 12FFFFH 090000H to 097FFFH SA26 1 0 0 1 1 X X X 130000H to 13FFFFH 098000H to 09FFFFH SA27 1 0 1 0 0 X X X 140000H to 14FFFFH 0A0000H to 0A7FFFH SA28 1 0 1 0 1 X X X 150000H to 15FFFFH 0A8000H to 0AFFFFH SA29 1 0 1 1 0 X X X 160000H to 16FFFFH 0B0000H to 0B7FFFH SA30 1 0 1 1 1 X X X 170000H to 17FFFFH 0B8000H to 0BFFFFH SA31 1 1 0 0 0 X X X 180000H to 18FFFFH 0C0000H to 0C7FFFH SA32 1 1 0 0 1 X X X 190000H to 19FFFFH 0C8000H to 0CFFFFH SA33 1 1 0 1 0 X X X 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH SA34 1 1 0 1 1 X X X 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH SA35 1 1 1 0 0 X X X 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH SA36 1 1 1 0 1 X X X 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH SA37 1 1 1 1 0 X X X 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH SA38 1 1 1 1 1 X X X 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH 13 MB84VD2118XA-85/MB84VD2119XA-85 Table 3.3 Sector Address Tables (MB84VD21182) Sector Address Bank Bank 2 Bank 1 14 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 X X X 000000H to 00FFFFH 000000H to 007FFFH SA1 0 0 0 0 1 X X X 010000H to 01FFFFH 008000H to 00FFFFH SA2 0 0 0 1 0 X X X 020000H to 02FFFFH 010000H to 017FFFH SA3 0 0 0 1 1 X X X 030000H to 03FFFFH 018000H to 01FFFFH SA4 0 0 1 0 0 X X X 040000H to 04FFFFH 020000H to 027FFFH SA5 0 0 1 0 1 X X X 050000H to 05FFFFH 028000H to 02FFFFH SA6 0 0 1 1 0 X X X 060000H to 06FFFFH 030000H to 037FFFH SA7 0 0 1 1 1 X X X 070000H to 07FFFFH 038000H to 03FFFFH SA8 0 1 0 0 0 X X X 080000H to 08FFFFH 040000H to 047FFFH SA9 0 1 0 0 1 X X X 090000H to 09FFFFH 048000H to 04FFFFH SA10 0 1 0 1 0 X X X 0A0000H to 0AFFFFH 050000H to 057FFFH SA11 0 1 0 1 1 X X X 0B0000H to 0BFFFFH 058000H to 05FFFFH SA12 0 1 1 0 0 X X X 0C0000H to 0CFFFFH 060000H to 067FFFH SA13 0 1 1 0 1 X X X 0D0000H to 0DFFFFH 068000H to 06FFFFH SA14 0 1 1 1 0 X X X 0E0000H to 0EFFFFH 070000H to 077FFFH SA15 0 1 1 1 1 X X X 0F0000H to 0FFFFFH 078000H to 07FFFFH SA16 1 0 0 0 0 X X X 100000H to 10FFFFH 080000H to 087FFFH SA17 1 0 0 0 1 X X X 110000H to 11FFFFH 088000H to 08FFFFH SA18 1 0 0 1 0 X X X 120000H to 12FFFFH 090000H to 097FFFH SA19 1 0 0 1 1 X X X 130000H to 13FFFFH 098000H to 09FFFFH SA20 1 0 1 0 0 X X X 140000H to 14FFFFH 0A0000H to 0A7FFFH SA21 1 0 1 0 1 X X X 150000H to 15FFFFH 0A8000H to 0AFFFFH SA22 1 0 1 1 0 X X X 160000H to 16FFFFH 0B0000H to 0B7FFFH SA23 1 0 1 1 1 X X X 170000H to 17FFFFH 0B8000H to 0BFFFFH SA24 1 1 0 0 0 X X X 180000H to 18FFFFH 0C0000H to 0C7FFFH SA25 1 1 0 0 1 X X X 190000H to 19FFFFH 0C8000H to 0CFFFFH SA26 1 1 0 1 0 X X X 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH SA27 1 1 0 1 1 X X X 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH SA28 1 1 1 0 0 X X X 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH SA29 1 1 1 0 1 X X X 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH SA30 1 1 1 1 0 X X X 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH SA31 1 1 1 1 1 0 0 0 1F0000H to 1F1FFFH 0F8000H to 0F8FFFH SA32 1 1 1 1 1 0 0 1 1F2000H to 1F3FFFH 0F9000H to 0F9FFFH SA33 1 1 1 1 1 0 1 0 1F4000H to 1F5FFFH 0FA000H to 0FAFFFH SA34 1 1 1 1 1 0 1 1 1F6000H to 1F7FFFH 0FB000H to 0FBFFFH SA35 1 1 1 1 1 1 0 0 1F8000H to 1F9FFFH 0FC000H to 0FCFFFH SA36 1 1 1 1 1 1 0 1 1FA000H to 1FBFFFH 0FD000H to 0FDFFFH SA37 1 1 1 1 1 1 1 0 1FC000H to 1FDFFFH 0FE000H to 0FEFFFH SA38 1 1 1 1 1 1 1 1 1FE000H to 1FFFFFH 0FF000H to 0FFFFFH MB84VD2118XA-85/MB84VD2119XA-85 Table 3.4 Sector Address Tables (MB84VD21192) Sector Address Bank Bank 1 Bank 2 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 0 0 0 000000H to 001FFFH 000000H to 000FFFH SA1 0 0 0 0 0 0 0 1 002000H to 003FFFH 001000H to 001FFFH SA2 0 0 0 0 0 0 1 0 004000H to 005FFFH 002000H to 002FFFH SA3 0 0 0 0 0 0 1 1 006000H to 007FFFH 003000H to 003FFFH SA4 0 0 0 0 0 1 0 0 008000H to 009FFFH 004000H to 004FFFH SA5 0 0 0 0 0 1 0 1 00A000H to 00BFFFH 005000H to 005FFFH SA6 0 0 0 0 0 1 1 0 00C000H to 00DFFFH 006000H to 006FFFH SA7 0 0 0 0 0 1 1 1 00E000H to 00FFFFH 007000H to 007FFFH SA8 0 0 0 0 1 X X X 010000H to 01FFFFH 008000H to 00FFFFH SA9 0 0 0 1 0 X X X 020000H to 02FFFFH 010000H to 017FFFH SA10 0 0 0 1 1 X X X 030000H to 03FFFFH 018000H to 01FFFFH SA11 0 0 1 0 0 X X X 040000H to 04FFFFH 020000H to 027FFFH SA12 0 0 1 0 1 X X X 050000H to 05FFFFH 028000H to 02FFFFH SA13 0 0 1 1 0 X X X 060000H to 06FFFFH 030000H to 037FFFH SA14 0 0 1 1 1 X X X 070000H to 07FFFFH 038000H to 03FFFFH SA15 0 1 0 0 0 X X X 080000H to 08FFFFH 040000H to 047FFFH SA16 0 1 0 0 1 X X X 090000H to 09FFFFH 048000H to 04FFFFH SA17 0 1 0 1 0 X X X 0A0000H to 0AFFFFH 050000H to 057FFFH SA18 0 1 0 1 1 X X X 0B0000H to 0BFFFFH 058000H to 05FFFFH SA19 0 1 1 0 0 X X X 0C0000H to 0CFFFFH 060000H to 067FFFH SA20 0 1 1 0 1 X X X 0D0000H to 0DFFFFH 068000H to 06FFFFH SA21 0 1 1 1 0 X X X 0E0000H to 0EFFFFH 070000H to 077FFFH SA22 0 1 1 1 1 X X X 0F0000H to 0FFFFFH 078000H to 07FFFFH SA23 1 0 0 0 0 X X X 100000H to 10FFFFH 080000H to 087FFFH SA24 1 0 0 0 1 X X X 110000H to 11FFFFH 088000H to 08FFFFH SA25 1 0 0 1 0 X X X 120000H to 12FFFFH 090000H to 097FFFH SA26 1 0 0 1 1 X X X 130000H to 13FFFFH 098000H to 09FFFFH SA27 1 0 1 0 0 X X X 140000H to 14FFFFH 0A0000H to 0A7FFFH SA28 1 0 1 0 1 X X X 150000H to 15FFFFH 0A8000H to 0AFFFFH SA29 1 0 1 1 0 X X X 160000H to 16FFFFH 0B0000H to 0B7FFFH SA30 1 0 1 1 1 X X X 170000H to 17FFFFH 0B8000H to 0BFFFFH SA31 1 1 0 0 0 X X X 180000H to 18FFFFH 0C0000H to 0C7FFFH SA32 1 1 0 0 1 X X X 190000H to 19FFFFH 0C8000H to 0CFFFFH SA33 1 1 0 1 0 X X X 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH SA34 1 1 0 1 1 X X X 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH SA35 1 1 1 0 0 X X X 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH SA36 1 1 1 0 1 X X X 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH SA37 1 1 1 1 0 X X X 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH SA38 1 1 1 1 1 X X X 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH 15 MB84VD2118XA-85/MB84VD2119XA-85 Table 3.5 Sector Address Tables (MB84VD21183) Sector Address Bank Bank 2 Bank 1 16 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 X X X 000000H to 00FFFFH 000000H to 007FFFH SA1 0 0 0 0 1 X X X 010000H to 01FFFFH 008000H to 00FFFFH SA2 0 0 0 1 0 X X X 020000H to 02FFFFH 010000H to 017FFFH SA3 0 0 0 1 1 X X X 030000H to 03FFFFH 018000H to 01FFFFH SA4 0 0 1 0 0 X X X 040000H to 04FFFFH 020000H to 027FFFH SA5 0 0 1 0 1 X X X 050000H to 05FFFFH 028000H to 02FFFFH SA6 0 0 1 1 0 X X X 060000H to 06FFFFH 030000H to 037FFFH SA7 0 0 1 1 1 X X X 070000H to 07FFFFH 038000H to 03FFFFH SA8 0 1 0 0 0 X X X 080000H to 08FFFFH 040000H to 047FFFH SA9 0 1 0 0 1 X X X 090000H to 09FFFFH 048000H to 04FFFFH SA10 0 1 0 1 0 X X X 0A0000H to 0AFFFFH 050000H to 057FFFH SA11 0 1 0 1 1 X X X 0B0000H to 0BFFFFH 058000H to 05FFFFH SA12 0 1 1 0 0 X X X 0C0000H to 0CFFFFH 060000H to 067FFFH SA13 0 1 1 0 1 X X X 0D0000H to 0DFFFFH 068000H to 06FFFFH SA14 0 1 1 1 0 X X X 0E0000H to 0EFFFFH 070000H to 077FFFH SA15 0 1 1 1 1 X X X 0F0000H to 0FFFFFH 078000H to 07FFFFH SA16 1 0 0 0 0 X X X 100000H to 10FFFFH 080000H to 087FFFH SA17 1 0 0 0 1 X X X 110000H to 11FFFFH 088000H to 08FFFFH SA18 1 0 0 1 0 X X X 120000H to 12FFFFH 090000H to 097FFFH SA19 1 0 0 1 1 X X X 130000H to 13FFFFH 098000H to 09FFFFH SA20 1 0 1 0 0 X X X 140000H to 14FFFFH 0A0000H to 0A7FFFH SA21 1 0 1 0 1 X X X 150000H to 15FFFFH 0A8000H to 0AFFFFH SA22 1 0 1 1 0 X X X 160000H to 16FFFFH 0B0000H to 0B7FFFH SA23 1 0 1 1 1 X X X 170000H to 17FFFFH 0B8000H to 0BFFFFH SA24 1 1 0 0 0 X X X 180000H to 18FFFFH 0C0000H to 0C7FFFH SA25 1 1 0 0 1 X X X 190000H to 19FFFFH 0C8000H to 0CFFFFH SA26 1 1 0 1 0 X X X 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH SA27 1 1 0 1 1 X X X 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH SA28 1 1 1 0 0 X X X 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH SA29 1 1 1 0 1 X X X 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH SA30 1 1 1 1 0 X X X 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH SA31 1 1 1 1 1 0 0 0 1F0000H to 1F1FFFH 0F8000H to 0F8FFFH SA32 1 1 1 1 1 0 0 1 1F2000H to 1F3FFFH 0F9000H to 0F9FFFH SA33 1 1 1 1 1 0 1 0 1F4000H to 1F5FFFH 0FA000H to 0FAFFFH SA34 1 1 1 1 1 0 1 1 1F6000H to 1F7FFFH 0FB000H to 0FBFFFH SA35 1 1 1 1 1 1 0 0 1F8000H to 1F9FFFH 0FC000H to 0FCFFFH SA36 1 1 1 1 1 1 0 1 1FA000H to 1FBFFFH 0FD000H to 0FDFFFH SA37 1 1 1 1 1 1 1 0 1FC000H to 1FDFFFH 0FE000H to 0FEFFFH SA38 1 1 1 1 1 1 1 1 1FE000H to 1FFFFFH 0FF000H to 0FFFFFH MB84VD2118XA-85/MB84VD2119XA-85 Table 3.6 Sector Address Tables (MB84VD21193) Sector Address Bank Bank 1 Bank 2 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 0 0 0 000000H to 001FFFH 000000H to 000FFFH SA1 0 0 0 0 0 0 0 1 002000H to 003FFFH 001000H to 001FFFH SA2 0 0 0 0 0 0 1 0 004000H to 005FFFH 002000H to 002FFFH SA3 0 0 0 0 0 0 1 1 006000H to 007FFFH 003000H to 003FFFH SA4 0 0 0 0 0 1 0 0 008000H to 009FFFH 004000H to 004FFFH SA5 0 0 0 0 0 1 0 1 00A000H to 00BFFFH 005000H to 005FFFH SA6 0 0 0 0 0 1 1 0 00C000H to 00DFFFH 006000H to 006FFFH SA7 0 0 0 0 0 1 1 1 00E000H to 00FFFFH 007000H to 007FFFH SA8 0 0 0 0 1 X X X 010000H to 01FFFFH 008000H to 00FFFFH SA9 0 0 0 1 0 X X X 020000H to 02FFFFH 010000H to 017FFFH SA10 0 0 0 1 1 X X X 030000H to 03FFFFH 018000H to 01FFFFH SA11 0 0 1 0 0 X X X 040000H to 04FFFFH 020000H to 027FFFH SA12 0 0 1 0 1 X X X 050000H to 05FFFFH 028000H to 02FFFFH SA13 0 0 1 1 0 X X X 060000H to 06FFFFH 030000H to 037FFFH SA14 0 0 1 1 1 X X X 070000H to 07FFFFH 038000H to 03FFFFH SA15 0 1 0 0 0 X X X 080000H to 08FFFFH 040000H to 047FFFH SA16 0 1 0 0 1 X X X 090000H to 09FFFFH 048000H to 04FFFFH SA17 0 1 0 1 0 X X X 0A0000H to 0AFFFFH 050000H to 057FFFH SA18 0 1 0 1 1 X X X 0B0000H to 0BFFFFH 058000H to 05FFFFH SA19 0 1 1 0 0 X X X 0C0000H to 0CFFFFH 060000H to 067FFFH SA20 0 1 1 0 1 X X X 0D0000H to 0DFFFFH 068000H to 06FFFFH SA21 0 1 1 1 0 X X X 0E0000H to 0EFFFFH 070000H to 077FFFH SA22 0 1 1 1 1 X X X 0F0000H to 0FFFFFH 078000H to 07FFFFH SA23 1 0 0 0 0 X X X 100000H to 10FFFFH 080000H to 087FFFH SA24 1 0 0 0 1 X X X 110000H to 11FFFFH 088000H to 08FFFFH SA25 1 0 0 1 0 X X X 120000H to 12FFFFH 090000H to 097FFFH SA26 1 0 0 1 1 X X X 130000H to 13FFFFH 098000H to 09FFFFH SA27 1 0 1 0 0 X X X 140000H to 14FFFFH 0A0000H to 0A7FFFH SA28 1 0 1 0 1 X X X 150000H to 15FFFFH 0A8000H to 0AFFFFH SA29 1 0 1 1 0 X X X 160000H to 16FFFFH 0B0000H to 0B7FFFH SA30 1 0 1 1 1 X X X 170000H to 17FFFFH 0B8000H to 0BFFFFH SA31 1 1 0 0 0 X X X 180000H to 18FFFFH 0C0000H to 0C7FFFH SA32 1 1 0 0 1 X X X 190000H to 19FFFFH 0C8000H to 0CFFFFH SA33 1 1 0 1 0 X X X 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH SA34 1 1 0 1 1 X X X 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH SA35 1 1 1 0 0 X X X 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH SA36 1 1 1 0 1 X X X 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH SA37 1 1 1 1 0 X X X 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH SA38 1 1 1 1 1 X X X 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH 17 MB84VD2118XA-85/MB84VD2119XA-85 Table 3.7 Sector Address Tables (MB84VD21184) Sector Address Bank Bank 2 Bank 1 18 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 X X X 000000H to 00FFFFH 000000H to 007FFFH SA1 0 0 0 0 1 X X X 010000H to 01FFFFH 008000H to 00FFFFH SA2 0 0 0 1 0 X X X 020000H to 02FFFFH 010000H to 017FFFH SA3 0 0 0 1 1 X X X 030000H to 03FFFFH 018000H to 01FFFFH SA4 0 0 1 0 0 X X X 040000H to 04FFFFH 020000H to 027FFFH SA5 0 0 1 0 1 X X X 050000H to 05FFFFH 028000H to 02FFFFH SA6 0 0 1 1 0 X X X 060000H to 06FFFFH 030000H to 037FFFH SA7 0 0 1 1 1 X X X 070000H to 07FFFFH 038000H to 03FFFFH SA8 0 1 0 0 0 X X X 080000H to 08FFFFH 040000H to 047FFFH SA9 0 1 0 0 1 X X X 090000H to 09FFFFH 048000H to 04FFFFH SA10 0 1 0 1 0 X X X 0A0000H to 0AFFFFH 050000H to 057FFFH SA11 0 1 0 1 1 X X X 0B0000H to 0BFFFFH 058000H to 05FFFFH SA12 0 1 1 0 0 X X X 0C0000H to 0CFFFFH 060000H to 067FFFH SA13 0 1 1 0 1 X X X 0D0000H to 0DFFFFH 068000H to 06FFFFH SA14 0 1 1 1 0 X X X 0E0000H to 0EFFFFH 070000H to 077FFFH SA15 0 1 1 1 1 X X X 0F0000H to 0FFFFFH 078000H to 07FFFFH SA16 1 0 0 0 0 X X X 100000H to 10FFFFH 080000H to 087FFFH SA17 1 0 0 0 1 X X X 110000H to 11FFFFH 088000H to 08FFFFH SA18 1 0 0 1 0 X X X 120000H to 12FFFFH 090000H to 097FFFH SA19 1 0 0 1 1 X X X 130000H to 13FFFFH 098000H to 09FFFFH SA20 1 0 1 0 0 X X X 140000H to 14FFFFH 0A0000H to 0A7FFFH SA21 1 0 1 0 1 X X X 150000H to 15FFFFH 0A8000H to 0AFFFFH SA22 1 0 1 1 0 X X X 160000H to 16FFFFH 0B0000H to 0B7FFFH SA23 1 0 1 1 1 X X X 170000H to 17FFFFH 0B8000H to 0BFFFFH SA24 1 1 0 0 0 X X X 180000H to 18FFFFH 0C0000H to 0C7FFFH SA25 1 1 0 0 1 X X X 190000H to 19FFFFH 0C8000H to 0CFFFFH SA26 1 1 0 1 0 X X X 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH SA27 1 1 0 1 1 X X X 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH SA28 1 1 1 0 0 X X X 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH SA29 1 1 1 0 1 X X X 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH SA30 1 1 1 1 0 X X X 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH SA31 1 1 1 1 1 0 0 0 1F0000H to 1F1FFFH 0F8000H to 0F8FFFH SA32 1 1 1 1 1 0 0 1 1F2000H to 1F3FFFH 0F9000H to 0F9FFFH SA33 1 1 1 1 1 0 1 0 1F4000H to 1F5FFFH 0FA000H to 0FAFFFH SA34 1 1 1 1 1 0 1 1 1F6000H to 1F7FFFH 0FB000H to 0FBFFFH SA35 1 1 1 1 1 1 0 0 1F8000H to 1F9FFFH 0FC000H to 0FCFFFH SA36 1 1 1 1 1 1 0 1 1FA000H to 1FBFFFH 0FD000H to 0FDFFFH SA37 1 1 1 1 1 1 1 0 1FC000H to 1FDFFFH 0FE000H to 0FEFFFH SA38 1 1 1 1 1 1 1 1 1FE000H to 1FFFFFH 0FF000H to 0FFFFFH MB84VD2118XA-85/MB84VD2119XA-85 Table 3.8 Sector Address Tables (MB84VD21194) Sector Address Bank Bank 1 Bank 2 Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A19 A18 A17 A16 A15 A14 A13 A12 SA0 0 0 0 0 0 0 0 0 000000H to 001FFFH 000000H to 000FFFH SA1 0 0 0 0 0 0 0 1 002000H to 003FFFH 001000H to 001FFFH SA2 0 0 0 0 0 0 1 0 004000H to 005FFFH 002000H to 002FFFH SA3 0 0 0 0 0 0 1 1 006000H to 007FFFH 003000H to 003FFFH SA4 0 0 0 0 0 1 0 0 008000H to 009FFFH 004000H to 004FFFH SA5 0 0 0 0 0 1 0 1 00A000H to 00BFFFH 005000H to 005FFFH SA6 0 0 0 0 0 1 1 0 00C000H to 00DFFFH 006000H to 006FFFH SA7 0 0 0 0 0 1 1 1 00E000H to 00FFFFH 007000H to 007FFFH SA8 0 0 0 0 1 X X X 010000H to 01FFFFH 008000H to 00FFFFH SA9 0 0 0 1 0 X X X 020000H to 02FFFFH 010000H to 017FFFH SA10 0 0 0 1 1 X X X 030000H to 03FFFFH 018000H to 01FFFFH SA11 0 0 1 0 0 X X X 040000H to 04FFFFH 020000H to 027FFFH SA12 0 0 1 0 1 X X X 050000H to 05FFFFH 028000H to 02FFFFH SA13 0 0 1 1 0 X X X 060000H to 06FFFFH 030000H to 037FFFH SA14 0 0 1 1 1 X X X 070000H to 07FFFFH 038000H to 03FFFFH SA15 0 1 0 0 0 X X X 080000H to 08FFFFH 040000H to 047FFFH SA16 0 1 0 0 1 X X X 090000H to 09FFFFH 048000H to 04FFFFH SA17 0 1 0 1 0 X X X 0A0000H to 0AFFFFH 050000H to 057FFFH SA18 0 1 0 1 1 X X X 0B0000H to 0BFFFFH 058000H to 05FFFFH SA19 0 1 1 0 0 X X X 0C0000H to 0CFFFFH 060000H to 067FFFH SA20 0 1 1 0 1 X X X 0D0000H to 0DFFFFH 068000H to 06FFFFH SA21 0 1 1 1 0 X X X 0E0000H to 0EFFFFH 070000H to 077FFFH SA22 0 1 1 1 1 X X X 0F0000H to 0FFFFFH 078000H to 07FFFFH SA23 1 0 0 0 0 X X X 100000H to 10FFFFH 080000H to 087FFFH SA24 1 0 0 0 1 X X X 110000H to 11FFFFH 088000H to 08FFFFH SA25 1 0 0 1 0 X X X 120000H to 12FFFFH 090000H to 097FFFH SA26 1 0 0 1 1 X X X 130000H to 13FFFFH 098000H to 09FFFFH SA27 1 0 1 0 0 X X X 140000H to 14FFFFH 0A0000H to 0A7FFFH SA28 1 0 1 0 1 X X X 150000H to 15FFFFH 0A8000H to 0AFFFFH SA29 1 0 1 1 0 X X X 160000H to 16FFFFH 0B0000H to 0B7FFFH SA30 1 0 1 1 1 X X X 170000H to 17FFFFH 0B8000H to 0BFFFFH SA31 1 1 0 0 0 X X X 180000H to 18FFFFH 0C0000H to 0C7FFFH SA32 1 1 0 0 1 X X X 190000H to 19FFFFH 0C8000H to 0CFFFFH SA33 1 1 0 1 0 X X X 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH SA34 1 1 0 1 1 X X X 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH SA35 1 1 1 0 0 X X X 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH SA36 1 1 1 0 1 X X X 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH SA37 1 1 1 1 0 X X X 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH SA38 1 1 1 1 1 X X X 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH 19 MB84VD2118XA-85/MB84VD2119XA-85 Table 4.1 Sector Group Addresses (MB84VD2118XA) (Top Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 X X X SA0 0 0 0 0 1 X X X 0 0 0 1 0 X X X 0 0 0 1 1 X X X SGA2 0 0 1 X X X X X SA4 to SA7 SGA3 0 1 0 X X X X X SA8 to SA11 SGA4 0 1 1 X X X X X SA12 to SA15 SGA5 1 0 0 X X X X X SA16 to SA19 SGA6 1 0 1 X X X X X SA20 to SA23 SGA7 1 1 0 X X X X X SA24 to SA27 1 1 1 0 0 X X X 1 1 1 0 1 X X X 1 1 1 1 0 X X X SGA9 1 1 1 1 1 0 0 0 SA31 SGA10 1 1 1 1 1 0 0 1 SA32 SGA11 1 1 1 1 1 0 1 0 SA33 SGA12 1 1 1 1 1 0 1 1 SA34 SGA13 1 1 1 1 1 1 0 0 SA35 SGA14 1 1 1 1 1 1 0 1 SA36 SGA15 1 1 1 1 1 1 1 0 SA37 SGA16 1 1 1 1 1 1 1 1 SA38 SGA1 SGA8 20 SA1 to SA3 SA28 to SA30 MB84VD2118XA-85/MB84VD2119XA-85 Table 4.2 Sector Group Addresses (MB84VD2119XA) (Bottom Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 1 1 1 SA7 0 0 0 0 1 X X X 0 0 0 1 0 X X X 0 0 0 1 1 X X X SGA9 0 0 1 X X X X X SA11 to SA14 SGA10 0 1 0 X X X X X SA15 to SA18 SGA11 0 1 1 X X X X X SA19 to SA22 SGA12 1 0 0 X X X X X SA23 to SA26 SGA13 1 0 1 X X X X X SA27 to SA30 SGA14 1 1 0 X X X X X SA31 to SA34 1 1 1 0 0 X X X 1 1 1 0 1 X X X 1 1 1 1 0 X X X 1 1 1 1 1 X X X SGA8 SGA15 SGA16 SA8 to SA10 SA35 to SA37 SA38 21 MB84VD2118XA-85/MB84VD2119XA-85 Table 5 Flash Memory Autoselect Codes Type Manufacturer’s Code MB84VD21181A MB84VD21191A MB84VD21182A MB84VD21192A Device Code MB84VD21183A MB84VD21193A MB84VD21184A MB84VD21194A Sector Group protect Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word A12 to A19 A6 A1 A0 A-1*1 Code (HEX) X VIL VIL VIL VIL 04H X VIL VIL VIH VIL 36H X 2236H X VIL VIL VIH VIL 39 X 2239H X VIL VIL VIH VIL 2D X 222DH X VIL VIL VIH VIL 2E X 222EH X VIL VIL VIH VIL 28H X 2228H X VIL VIL VIH VIL 2BH X 222BH X VIL VIL VIH VIL 33H X 2233H X VIL VIL VIH VIL 35 X 2235H Sector Group Address VIL VIH VIL VIL 01H*2 *1 : A-1 is for Byte mode. *2 : Output 01H at protected sector address and output 00H at unprotected sector address. 22 MB84VD2118XA-85/MB84VD2119XA-85 Table 6 Flash Memory Command Definitions Bus Write Command Sequence First Bus Write Cycle Second Bus Write Cycle Cycles Req’d Addr. Data Addr. Read/Reset (Note 1) Read/Reset (Note 1) Word Byte 1 3 Word Autoselect Chip Erase Sector Erase XXXH F0H 555H AAAH 3 Word Byte Word Byte Word Byte AAH 555H Byte Program Third Bus Write Cycle 6 6 2AAH 555H AAH 555H AAAH 555H AAAH 555H AAAH Addr. 55H 2AAH AAAH 4 Data 55H 555H AAH AAH AAH 2AAH 555H 2AAH 555H 2AAH 555H 55H 55H 55H 555H AAAH (BA) 555H (BA) AAAH 555H AAAH 555H AAAH 555H AAAH Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Data Addr. Data Addr. Data Addr. Data F0H RA RD 90H A0H PA PD 80H 80H 555H AAAH 555H AAAH AAH AAH 2AAH 555H 2AAH 555H 55H 555H AAAH 10H 55H SA 30H Sector Erase Suspend 1 BA B0H Sector Erase Resume 1 BA 30H 20H Set to Fast Mode Word Fast Program (Note 2) Word Reset from Fast Mode (Note 2) Word Extended Sector Group Protection (Note 3) Word Query (Note 4) Word Hi-ROM Entry Byte Byte Byte Byte Byte Word Byte Hi-ROM Program (Note 5) Word Hi-ROM Erase (Note 5) Word Hi-ROM Exit (Note 5) Byte Byte 3 2 2 4 1 3 555H AAAH XXXH A0H BA 90H XXXH 60H 55H AAH 555H AAAH 98H AAH 555H 4 6 Word AAAH 555H AAAH 2AAH 555H AAH 555H AAAH PA PD XXXH F0H (Note6) SPA 60H SPA 40H SPA SD 88H A0H PA PD 55H HRA 30H 2AAH 555H 555H 2AAH 555H 55H 55H 55H 555H 555H AAAH 555H 55H 2AAH AAH AAAH 55H 2AAH AAH 555H 4 Byte AAH AAAH 555H AAAH (HRBA) 555H (HRBA) AAAH 80H 555H AAAH AAH 90H XXXH 00H 2AAH 555H 23 MB84VD2118XA-85/MB84VD2119XA-85 Notes : 1 : Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 2 : This command is valid while Fast Mode. 3 : This command is valid while RESET = VID. 4 : The valid Address is A0 to A6. 5 : This command is valid while Hi-ROM mode. 6 : The data “00H” is also acceptable. Address bits A12 to A19 = X = “H” or “L” for all address commands except for Program Address (PA) , Sector Address (SA) , and Bank Address (BA) . Bus operations are defined in Table 2 “User Bus Operations”. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A15 to A19) SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). HRA = Address of the Hidden-ROM area. SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). HRA = Address of the Hidden-ROM area. MB84VD2118XA (Top Boot Type) Word mode: 0F8000H to 0FFFFFH Byte mode: 1F0000H to 1FFFFFH MB84VD2119XA (Bottom Boot Type) Word mode: 000000H to 007FFFH Byte mode: 000000H to 00FFFFH HRBA = Bank addrss of the Hidden-ROM area. MB84VD2118XA (Top Boot Type) : A15 = A16 = A17 = A18 = A19 = A20 = 1 MB84VD2119XA (Bottom Boot Type) : A15 = A16 = A17 = A18 = A19 = A20 = 0 RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotectedsector addresses. The system should generate the following address patterns; Word mode : 555H or 2AAH to addresses A0 to A10 Byte mode : AAAH or 555H to addresses A -1 and A0 to A10 24 MB84VD2118XA-85/MB84VD2119XA-85 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min. Max. Tstg −55 +125 °C TA −25 +85 °C VIN, VOUT −0.3 VCCf, VCCs −0.3 +4.0 V A9 and OE (Note 2) VIN −0.3 +13.0 V RESET (Note 2) VIN −0.5 +13.0 V WP/ACC (Note 3) VIN −0.5 +10.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET, WP/ACC (Note 1) VCCf/VCCs Supply (Note 1) VCCf + 0.4 VCCs + 0.4 V WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Notes 1. Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf +0.4 V or VCCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on A9 and OE pin is –0.3 V. Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, A9, OE, and RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input voltage on A9, OE, and RESET pins is +13.0 V which may overshoot to 14.0 V for periods of up to 20 ns. 3. Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to 12.0 V for periods of up to 20 ns, when VCCf is applied. ■ RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature VCCf/VCCs Supply Voltages Symbol Value Unit Min. Max. TA −25 +85 °C VCCf, VCCs +2.7 +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 25 MB84VD2118XA-85/MB84VD2119XA-85 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol 26 Parameter Description Test Conditions Min. Typ. Max. Unit ILI Input Leakage Current VIN = VSS to VCCf, VCCs −1.0 +1.0 µA ILO Output Leakage Current VOUT = VSS to VCCf, VCCs −1.0 +1.0 µA ILIT RESET Inputs Leakage Current VCCf = VCCf Max, VCCs = VCCs Max, RESET = 12.5V 35 µA ILIA ACC Input Leakage Current VCCf = VCCf Max, VCCs = VCCs Max, WP/ACC = VACC Max 20 mA tCYCLE = 5 MHz Byte 13 ICC1f Flash VCC Active Current (Read) (Note 1) tCYCLE = 5 MHz Word 15 tCYCLE = 1 MHz Byte 7 tCYCLE = 1 MHz Word 7 35 Byte 48 Word 50 Byte 48 Word 50 35 mA 40 mA tCYCLE = 10 MHz 40 mA tCYCLE = 1 MHz 8 mA CEf = VIL, OE = VIH mA mA ICC2f Flash VCC Active Current (Program/Erase) (Note 2) CEf = VIL, OE = VIH ICC3f Flash VCC Active Current (Read-While-Program) (Note 5) CEf = VIL, OE = VIH ICC4f Flash VCC Active Current (Read-While-Erase) (Note 5) CEf = VIL, OE = VIH ICC5f Flash VCC Active Current (Erase-Suspend-Program) CEf = VIL, OE = VIH ICC1s VCCs = VCC Max., SRAM VCC Active Current CE1s = VIL, tCYCLE = 10 MHz CE2s = VIH ICC2s CE1s = 0.2 V, SRAM VCC Active Current CE2s = VCCs − 0.2 V, ISB1f Flash VCC Standby Current VCCf = VCC Max., CEf = VCCf ± 0.3 V RESET = VCCf ± 0.3 V, WP/ACC = VCCf ± 0.3 V 1 5 µA ISB2f Flash VCC Standby Current (RESET) VCCf = VCC Max., RESET = VSS ± 0.3 V WP/ACC = VCCf ± 0.3 V 1 5 µA ISB3f Flash VCC Current (Automatic Sleep Mode) (Note 3) VCCf = VCC Max., CEf = VSS ± 0.3 V RESET = VCCf ± 0.3 V, WP/ACC = VCCf ± 0.3 V VIN = VCCf ± 0.3 V or VSS ± 0.3 V 1 5 µA ISB1s SRAM VCC Standby Current CE1s ≥ VCCs − 0.2V, CE2s ≥ VCCs − 0.2V 0.2 7 µA ISB2s SRAM VCC Standby Current CE2s ≤ 0.2V 0.2 7 µA mA mA mA MB84VD2118XA-85/MB84VD2119XA-85 (Continued) (Continued) Parameter Symbol Parameter Description Test Conditions Min. Typ. Max. Unit VIL Input Low Level −0.3 0.5 V VIH Input High Level 2.4 VCC + 0.3* V VID Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) (Note 4) 11.5 12.5 V VACC Voltage for Program Acceleration (WP/ACC) (Note4) 8.5 9.0 9.5 V VOL Output Low Voltage Level VCCf = VCCf Min., VCCs = VCCs Min., IOL = 1.0 mA 0.4 V VOH Output High Voltage Level VCCf = VCCf Min., VCCs = VCCs Min., IOH = −0.5 mA 2.4 V VLKO Flash Low VCCf Lock-Out Voltage 2.3 2.5 V *: VCC indicates lower of VCCf or VCCs. Notes : 1. The ICC current listed includes both the DC operating current and the frequency dependent component. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remain stable for 150ns. 4. Applicable for only VCCf applying. 5. Embedded Alogorithm (program or erase) is in progress. (@5MHz) 27 MB84VD2118XA-85/MB84VD2119XA-85 2. AC Characteristics • CE Timing Parameter Symbols JEDEC Standard tCCR Description Test Setup CE Recover Time Min. • Timing Diagram for alternating SRAM to Flash CEf tCCR tCCR tCCR tCCR CE1s CE2s 28 -85 Unit 0 ns MB84VD2118XA-85/MB84VD2119XA-85 • Read Only Operations Characteristics (Flash) Parameter Symbols Description JEDEC Standard Test Setup -85 (Note) Unit Min. Max. 85 ns tAVAV tRC Read Cycle Time tAVQV tACC Address to Output Delay CEf = VIL OE = VIL 85 ns tELQV tCEf Chip Enable to Output Delay OE = VIL 85 ns tGLQV tOE Output Enable to Output Delay 35 ns tEHQZ tDF Chip Enable to Output High-Z 30 ns tGHQZ tDF Output Enable to Output High-Z 30 ns tAXQX tOH Output Hold Time From Addresses, CEf or OE, Whichever Occurs First 0 ns tREADY RESET Pin Low to Read Mode 20 µs Note : Test Conditions − Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V to 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V 29 MB84VD2118XA-85/MB84VD2119XA-85 • Read Cycle (Flash) tRC Addresses Stable Addresses tACC CEf tDF tOE OE tOEH WE tCEf HIGH-Z DQ HIGH-Z Output Valid tRC Addresses Addresses Stable tRH tACC CEf tRP tRH tCEf RESET tOH HIGH-Z DQ 30 Output Valid MB84VD2118XA-85/MB84VD2119XA-85 • Erase/Program Operations (Flash) Parameter Symbols JEDEC Standard tAVAV tWC tAVWL Description -85 Unit Min. Typ. Max. Write Cycle Time 85 ns tAS Address Setup Time (WE to Addr.) 0 ns tASO Address Setup Time to CEf Low During Toggle Bit Polling 15 ns tWLAX tAH Address Hold Time (WE to Addr.) 45 ns tAHT Address Hold Time from CEf or OE High During Toggle Bit Polling 0 ns tDVWH tDS Data Setup Time 35 ns tWHDX tDH Data Hold Time 0 ns tOES Output Enable Setup Time 0 ns tOEH Output Enable Hold Time Read 0 ns Toggle and Data Polling 10 ns tCEPH CEf High During Toggle Bit Polling 20 ns tOEPH OE High During Toggle Bit Polling 20 ns tGHEL tGHEL Read Recover Time Before Write (OE to CEf) 0 ns tGHWL tGHWL Read Recover Time Before Write (OE to WE) 0 ns tWLEL tWS WE Setup Time (CEf to WE) 0 ns tELWL tCS CEf Setup Time (WE to CEf) 0 ns tEHWH tWH WE Hold Time (CEf to WE) 0 ns tWHEH tCH CEf Hold Time (WE to CEf) 0 ns tWLWH tWP Write Pulse Width 35 ns tELEH tCP CEf Pulse Width 35 ns tWHWL tWPH Write Pulse Width High 30 ns tEHEL tCPH CEf Pulse Width High 30 ns tWHWH1 tWHWH1 Byte Programming Operation 8 µs Word Programming Operation 16 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 1) 1 s (Continued) 31 MB84VD2118XA-85/MB84VD2119XA-85 (Continued) Parameter Symbols JEDEC Standard tVCS Description -85 Unit Min. Typ. Max. VCCf Setup Time 50 µs tVLHT Voltage Transition Time (Note 2) 4 µs tVIDR Rise Time to VID (Note 2) 500 ns tVACCR Rise Time to VACC 500 ns tRB Recover Time from RY/BY 0 ns tRP RESET Pulse Width 500 ns tEOE Delay Time from Embedded Output Enable 85 ns tRH RESET Hold Time Before Read 200 ns tBUSY Program/Erase Valid to RY/BY Delay 90 ns tTOW Erase Time-out Time (Note 3) 50 µs tSPD Erase Suspend Transition Time (Note 4) 20 µs Notes : 1. This does not include the preprogramming time. 2. This timing is for Sector Protection Operation. 3. The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command (s) . 4. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “tSPD” to suspend the erase operation. 32 MB84VD2118XA-85/MB84VD2119XA-85 • Write Cycle (WE control) (Flash) 3rd Bus Cycle Addresses Data Polling 555H tWC PA tAS PA tRC tAH CEf tCS tCH tCEf OE tGHWL tWP tOE tWHWH1 tWPH WE tOH tDS tDH DQ A0H PD DQ7 DOUT DOUT Notes : 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.) 33 MB84VD2118XA-85/MB84VD2119XA-85 • Write Cycle (CEf control) (Flash) 3rd Bus Cycle Addresses Data Polling 555H tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tWHWH1 tCPH CEf tDS tDH DQ A0H PD DQ7 DOUT Notes : 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.) 34 MB84VD2118XA-85/MB84VD2119XA-85 • AC Waveforms Chip/Sector Erase Operations (Flash) 555H Addresses tWC 2AAH tAS 555H 555H 2AAH SA* tAH CEf tCS tCH OE tGHWL tWP tWPH WE tDS tDH AAH 30H for Sector Erase 55H 80H AAH 55H DQ 10H/ 30H tVCS VCCf * : SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase. Note : These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.) 35 MB84VD2118XA-85/MB84VD2119XA-85 • AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) CEf tCH tDF tOE OE tOEH WE tCEf * DQ7 Data In DQ7 = Valid Data DQ7 High-Z tWHWH1 or 2 DQ (DQ0 to DQ6) Data In DQ0 to DQ6 = Output Flag tBUSY tEOE RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation.) 36 DQ0 to DQ6 Valid Data High-Z MB84VD2118XA-85/MB84VD2119XA-85 • AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) Addresses tAHT tASO tAHT tAS CEf tCEPH WE tOEPH tOEH tOEH OE tDH DQ6/DQ2 Toggle Data Data tCEf* tOE Toggle Data Toggle Data Stop Toggling Output Valid tBUSY RY/BY * : DQ6 stops toggling (The device has completed the Embedded operation) . 37 MB84VD2118XA-85/MB84VD2119XA-85 • Back-to-back Read/Write Timing Diagram (Flash) Address Read Command Read Command Read Read tRC tWC tRC tWC tRC tRC BA1 BA2 (555H) BA1 BA2 (PA) BA1 BA2 (PA) tAS tAS tACC tAH tAHT tCEf CEf tOE tCEPH OE tGHWL tOEH tDF tWP WE tDS DQ Valid Output tDH Valid Input (A0H) tDF Valid Output Valid Input Valid Output Status (PD) Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address of Bank 1. BA2 : Address of Bank 2. 38 MB84VD2118XA-85/MB84VD2119XA-85 • RY/BY Timing Diagram during Write/Erase Operations (Flash) CEf The rising edge of the last write pulse WE Entire programming or erase operations RY/BY tBUSY • RESET, RY/BY Timing Diagram (Flash) WE RESET tRP tRB RY/BY tREADY 39 MB84VD2118XA-85/MB84VD2119XA-85 • Temporary Sector Unprotection (Flash) VCCf tVIDR tVLHT tVCS VID 3V 3V RESET CEf WE tVLHT tVLHT Program or Erase Command Sequence RY/BY Unprotection Period 40 MB84VD2118XA-85/MB84VD2119XA-85 • Extended Sector Protection (Flash) VCCf tVCS RESET tVLHT tVIDR tWC tWC SGAx Addresses SGAx SGAy A0 A1 A6 CEf OE TIME - OUT tWP WE Data 60H 60H 40H 01H 60H tOE SGAx : Sector Group Address to be protected SGAy : Next Group Sector Address to be protected TIME-OUT : Time-Out window = 250 µs (min.) 41 MB84VD2118XA-85/MB84VD2119XA-85 • Accelerated Program (Flash) VCC tVACCR tVCS tVLHT VACC 3V 3V WP/ACC CE WE tVLHT Program or Erase Command Sequence RY/BY Acceleration period 42 tVLHT MB84VD2118XA-85/MB84VD2119XA-85 • Read Cycle (SRAM) Parameter Symbol Parameter Description Min. Max. Unit tRC Read Cycle Time 85 ns tAA Address Access Time 85 ns tCO1 Chip Enable (CE1s) Access Time 85 ns tCO2 Chip Enable (CE2s) Access Time 85 ns tOE Output Enable Access Time 45 ns tBA LBS, UBS to Output Valid 85 ns tCOE Chip Enable (CE1s Low and CE2s High) to Output Active 5 ns tOEE Output Enable Low to Output Active 0 ns tBE UBS, LBS Enable Low to Output Active 0 ns tOD Chip Enable (CE1s High or CE2s Low) to Output High-Z 35 ns tODO Output Enable High to Output High-Z 35 ns tBD UBS, LBS Output Enable to Output High-Z 50 ns tOH Output Data Hold Time 10 ns 43 MB84VD2118XA-85/MB84VD2119XA-85 • Read Cycle (Note) (SRAM) tRC ADDRESSES tAA tOH tCO1 CE1s tCOE tOD tCO2 CE2s tOD tOE OE tODO tOEE LBS, UBS tBA tBD tBE tCOE DQ Note : WE remains HIGH for the read cycle. 44 VALID DATA OUT MB84VD2118XA-85/MB84VD2119XA-85 • Write Cycle (SRAM) Parameter Symbol Parameter Description Min. Max. Unit tWC Write Cycle Time 85 ns tWP Write Pulse Width 55 ns tCW Chip Enable to End of Write 70 ns tAW Address valid to End of Write 70 ns tBW UBS, LBS to End of Write 55 ns tAS Address Setup Time 0 ns tWR Write Recovery Time 0 ns tODW WE Low to Output High-Z 35 ns tOEW WE High to Output Active 0 ns tDS Data Setup Time 35 ns tDH Data Hold Time 0 ns 45 MB84VD2118XA-85/MB84VD2119XA-85 • Write Cycle (Note 3) (WE control) (SRAM) tWC Addresses tAS tWP tWR WE tAW tCW CE1s CE2s tCW tBW LBS, UBS tODW DOUT tOEW Note 1 Note 2 tDS DIN Note 4 tDH VALID DATA IN Note 4 Notes : 1. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 2. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 3. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 4. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 46 MB84VD2118XA-85/MB84VD2119XA-85 • Write Cycle (Note 1) (CE1s control) (SRAM) tWC Addresses tAS tWR tWP WE tAW tCW CE1s CE2s tCW tBW LBS, UBS tBE tCOE tODW DOUT tDS DIN Note 2 tDH VALID DATA IN Notes : 1. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 2. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 47 MB84VD2118XA-85/MB84VD2119XA-85 • Write Cycle (Note 1) (CE2s Control) (SRAM) tWC Addresses tAS tWP tWR WE tCW CE1s tAW CE2s tCW tBW LBS, UBS tBE tCOE tODW DOUT tDS DIN Note 2 tDH VALID DATA IN Notes : 1. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 2. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 48 MB84VD2118XA-85/MB84VD2119XA-85 • Write Cycle (Note 1) (LBs, UBs Control) (SRAM) tWC Addresses tWP tWR WE tCW CE1s tCW CE2s tAW tAS tBW LBS, UBS tBE tCOE tODW DOUT tDS DIN Note 2 tDH VALID DATA IN Notes : 1. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 2. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 49 MB84VD2118XA-85/MB84VD2119XA-85 ■ ERASE AND PROGRAMMING PERFORMANCE (Flash) Limits Parameter Unit Comment Min. Typ. Max. Sector Erase Time 1 10 s Excludes programming time prior to erasure Byte Programming Time 8 300 µs Excludes system-level overhead Word Programming Time 16 360 µs Excludes system-level overhead Chip Programming Time 50 s Excludes system-level overhead 100,000 cycle Erase/Program Cycle ■ DATA RETENTION CHARACTERISTICS (SRAM) Parameter Symbol Parameter Description Min. Typ. Max. Unit 1.5 3.6 V 0.2 7* µA VDH Data Retention Supply Voltage IDDS2 Standby Current tCDR Chip Deselect to Data Retention Mode Time 0 ns Recovery Time tRC ns tR VDH = 3.0 V Note : tRC : Read cycle time * : 4 µA Max. at TA ≤ 60 °C, 1 µA Max. at TA ≤ 40 °C • CE1s Controlled Data Retention Mode (Note 1) VCCs DATA RETENTION MODE 2.7 V See Note 2 VIH VDH CE1s GND 50 tCDR See Note 2 VCCS −0.2 V tR MB84VD2118XA-85/MB84VD2119XA-85 • CE2s Controlled Data Retention Mode (Note 3) VCCs DATA RETENTION MODE 2.7 V VDH VIH CE2s tCDR tR VIL 0.2 V GND Notes : 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs − 0.2 V or Vss to 0.2 V during data retention mode. Other input and input/output pins can be used between −0.3 V and Vccs + 0.3 V. 2. When CE1s is operating at the VIH min. level (2.2 V) , the standby current is given by ISB1s during the transition of VCCs from 3.6 to 2.2 V. 3. In CE2s controlled data retention mode, input and input/output pins can be used between −0.3 V and Vccs + 0.3 V. ■ PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN = 0 11 14 pF COUT Output Capacitance VOUT = 0 12 16 pF CIN2 Control Pin Capacitance VIN = 0 14 16 pF CIN3 WP/ACC Pin Capacitance VIN = 0 17 20 pF Note : Test conditions TA = 25 °C, f = 1.0 MHz ■ HANDLING OF PACKAGE Please handle this package carefully since the sides of packages are right angle. ■ CAUTION 1. The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2. For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector using “Extended sector protect” command. 51 MB84VD2118XA-85/MB84VD2119XA-85 ■ ORDERING INFORMATION MB84VD2118 X A -85 -PBS PACKAGE TYPE PBS = 69-ball FBGA PTS = 56-pin TSOP (I) SPEED OPTION See Product Selector Guide. Device Revision Bank Size 1 = 0.5 Mbit / 15.5 Mbit 2 = 2 Mbit / 14 Mbit 3 = 4 Mbit / 12 Mbit 4 = 8 Mbit / 8 Mbit DEVICE NUMBER/DESCRIPTION 16Mega-bit (2M × 8-bit or 1M × 16-bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 4Mega-bit (512K × 8-bit) SRAM BOOT CODE SECTOR ARCHITECTURE 84VD2118 = Top sector 84VD2119 = Bottom sector 52 MB84VD2118XA-85/MB84VD2119XA-85 ■ PACKAGE DIMENSIONS 69-ball plastic FBGA (BGA-69P-M02) 7.20(.283) 11.00±0.10(.433±.004) 1.25 +0.15 –0.10 +.006 –.004 5.60(.220)REF (Mounting height) .049 0.38±0.10 (Stand off) (.015±.004) 0.80(.031) 10 9 8 0.80(.031) 8.00±0.10 (.315±.004) 7 6 5.60(.220) REF 7.20(.283) 5 4 3 2 1 K J H G F E D C B A INDEX-MARK AREA INDEX BALL +0.10 69-Ø0.45 –0.05 +.004 69-Ø0.18 –.002 0.08(.003) M 0.10(.004) C 1999 FUJITSU LIMITED B69002S-1C-1 Dimension in mm (inches) (Continued) 53 MB84VD2118XA-85/MB84VD2119XA-85 (Continued) 56-pin plastic TSOP (I) (FPT-56P-M04) 14.00±0.20(.551±.008) 12.40±0.10(.488±.004) INDEX 0.40(.016) TYP 12.00±0.10 (.472±.004) 0.18±0.035 (.007±.001) "A" 0.10(.004) M Details of "A" part 0.25(.010) +0.05 0.145 –0.03 .006 C +.002 –.001 0.08(.003) 1.15±0.05 0.10±0.05 (.045±.002) (.004±.002) (Mounting height) (Stand off) 0°~8° 0.45/0.75 (.018/.030) 1998 FUJITSU LIMITED F56004S-1C-1 Dimension in mm (inches) 54 MB84VD2118XA-85/MB84VD2119XA-85 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0007 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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