TI ISO15DW Isolated 3.3-v full and half-duplex rs-485 transceiver Datasheet

ISO15
ISO35
www.ti.com................................................................................................................................................................ SLOS580B – MAY 2008 – REVISED JULY 2008
ISOLATED 3.3-V FULL AND HALF-DUPLEX RS-485 TRANSCEIVERS
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
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4000-VPEAK Isolation, 560-Vpeak VIORM
UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2)
1/8 Unit Load – Up to 256 Nodes on a Bus
Meets or Exceeds TIA/EIA RS-485
Requirements
Signaling Rates up to 1 Mbps
Thermal Shutdown Protection
Low Bus Capacitance – 16 pF (Typ)
50 kV/µs Typical Transient Immunity
Fail-safe Receiver for Bus Open, Short, Idle
3.3-V Inputs are 5-V Tolerant
Security Systems
Chemical Production
Factory Automation
Motor/motion Control
HVAC and Building Automation Networks
Networked Security Stations
DESCRIPTION
The ISO15 is an isolated half-duplex differential line transceiver while the ISO35 is an isolated full-duplex
differential line driver and receiver for TIA/EIA 485/422 applications.
These devices are ideal for long transmission lines since the ground loop is broken to allow for a much larger
common-mode voltage range. The symmetrical isolation barrier of the device is tested to provide 2500 Vrms of
isolation for 60s between the bus-line transceiver and the logic-level interface.
Any cabled I/O can be subjected to electrical noise transients from various sources. These noise transients can
cause damage to the transceiver and/or near-by sensitive circuitry if they are of sufficient magnitude and
duration. These isolated devices can significantly increase protection and reduce the risk of damage to
expensive control circuits.
The ISO15 and ISO35 are qualified for use from –40°C to 85°C.
GND1
GND1
1
2
16
15
Vcc2
GND2
3
4
5
6
7
8
14
13
12
A
B
Z
Y
GND2
11
10
9
DW PACKAGE
Vcc1
GND1
R
RE
DE
D
GND1
GND1
1
2
16
15
3
4
5
6
7
8
14
13
12
11
10
9
GND2
3
4
R
RE
5
DE
6
D
14
13
12
11
A
B
Z
Y
function diagram
Vcc2
5
GND2 DE
nc
6
B
D
A
3
R
nc
GND2 RE 4
GND2
GALVANIC ISOLATION
Vcc1
GND1
R
RE
DE
D
GALVANIC ISOLATIO N
function diagram
DW PACKAGE
13
12
B
A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ISO15
ISO35
SLOS580B – MAY 2008 – REVISED JULY 2008................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
–0.3 to 6
V
Voltage at any bus I/O terminal
–9 to 14
V
VIT
Voltage input, transient pulse, A, B, Y, and Z (through 100Ω, see Figure 11)
–50 to 50
V
VI
Voltage input at any D, DE or RE terminal
–0.5 to 7
V
IO
Receiver output current
±10
mA
VCC
Input supply voltage.
VO
(2)
VCC1, VCC2
Human Body Model
ESD
TJ
(1)
(2)
Electrostatic
discharge
JEDEC Standard 22,
Test Method A114-C.01
Charged Device
Model
JEDEC Standard 22,
Test Method C101
Machine Model
ANSI/ESDS5.2-1996
Bus pins and GND1
±6
Bus pins and GND2
±16
All pins
±4
kV
kV
±1
All pins
±200
V
170
°C
Maximum junction temperature
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values
RECOMMENDED OPERATING CONDITIONS
VCC
Supply Voltage, VCC1, VCC2
VOC
Voltage at either bus I/O terminal
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
RL
Differential input resistance
IO
Output current
TJ
Operating junction temperature
A, B
D, DE, RE
A with respect to B
MIN
TYP
MAX
3.15
3.3
3.6
V
–7
12
V
2
VCC
0
0.8
–12
Receiver
V
12
54
Driver
UNIT
V
Ω
60
–60
60
–8
8
–40
150
mA
°C
SUPPLY CURRENT
over recommended operating condition (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ISO35
ICC1
Logic-side supply
current
ISO15
ISO35
ICC2
Bus-side supply
current
ISO15
2
MIN
TYP
MAX
RE at 0 V or Vcc, DE at 0 V, No load (driver disabled)
8
RE at 0 V or Vcc, DE at VCC, No Load (driver enabled)
8
RE at 0 V or Vcc, DE at 0 V, No load (driver disabled)
8
RE at 0 V or Vcc, DE at VCC, No Load (driver enabled)
8
RE at 0 V or Vcc, DE at 0 V, No load (driver disabled)
15
RE at 0 V or Vcc, DE at VCC, No Load (driver enabled)
19
RE at 0 V or Vcc, DE at 0 V, No load (driver disabled)
15
RE at 0 V or Vcc, DE at VCC, No Load (driver enabled)
19
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UNIT
mA
mA
mA
mA
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ISO35
www.ti.com................................................................................................................................................................ SLOS580B – MAY 2008 – REVISED JULY 2008
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
IO = 0 mA, no load
2.5
RL = 54 Ω, See Figure 1
1.5
2
2
2.3
| VOD |
Differential output voltage magnitude
Δ|VOD|
Change in magnitude of the differential
output voltage
VOC(SS)
Steady-state common-mode output voltage
ΔVOC(SS)
Change in steady-state common-mode
output voltage
VOC(pp)
Peak-to-peak common-mode output voltage See Figure 3
II
Input current
RL = 100 Ω (RS-422), See Figure 1
Vtest from –7 V to +12 V, See Figure 2
MAX
UNIT
VCC
V
1.5
See Figure 1 and Figure 2
See Figure 3
–0.2
0
0.2
1
2.6
3
–0.1
0.1
0.5
D, DE, VI at 0 V or VCC1
V
V
V
–10
10
µA
ISO15 See receiver input current
VY or VZ = 12 V
IOZ
High-impedance state output current
IDO35
VY or VZ = 12 V, VCC = 0
VY or VZ = –7 V
90
Other
input
at 0 V
VY or VZ = –7 V, VCC = 0
VA or VB at –7 V
90
µA
–10
Other
input
at 0 V
Short-circuit output current
VA or VB at 12 V
C(OD)
Differential output capacitance
VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 12 and Figure 13
IOS
–10
–250
250
25
mA
16
pF
50
kV/µs
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr
Differential output signal rise time
tf
Differential output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
tPZH
Propagation delay, high-impedance-to-high-level output
tPLZ
Propagation delay, low-level to high-impedance output
tPZL
Propagation delay, standby-to-low-level output
MIN
TYP
MAX
UNIT
340
See Figure 4
See Figure 5
6
ns
120
185
300
120
180
300
ns
205
µs
530
See Figure 6
330
530
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µs
3
ISO15
ISO35
SLOS580B – MAY 2008 – REVISED JULY 2008................................................................................................................................................................ www.ti.com
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT(+)
Positive-going input threshold voltage
IO = –8 mA
VIT(–)
Negative-going input threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT–)
MIN
–20
–200
Output voltage
VID = 200 mV, See Figure 7
IO(Z)
High-impedance state output current
VI = –7 to 12 V, Other input = 0 V
VA or VB = 12 V, VCC = 0
IO = 8 mA
0.4
–1
VA or VB = –7 V
Other input at 0 V
mV
mV
2.4
VA or VB = 12 V
UNIT
mV
50
IO = –8 mA
VO
IA or IB Bus input current
TYP MAX
1
0.05
0.1
0.05
0.1
–0.1
–0.04
–0.03
V
µA
mA
VA or VB = –7 V, VCC = 0
–0.1
IIH
High-level input current, RE
VIH = 2 V
–10
µA
IIL
Low-level input current, RE
VIL = 0.8 V
–10
µA
RID
Differential input resistance
A, B
CD
Differential input capacitance
VI = 0.4 sin (4E6πt) + 0.5V, DE at 0 V
48
kΩ
16
pF
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH, tPHL Propagation delay
TEST CONDITIONS
MIN
TYP
MAX
ISO15
100
ISO35
100
ISO15
13
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
tr
Output signal rise time
2
4
tf
Output signal fall time
2
4
tPZH,
tPZL
Propagation delay, high-impedance-to-high-level output
Propagation delay, standby-to-low-level output
13
25
ns
tPHZ,
tPLZ
Propagation delay, high-level-to-high-impedance output
Propagation delay, low-level to high-impedance output
13
25
ns
4
ISO35
See Figure 8
UNIT
13
DE at 0 V, See Figure 9
and Figure 10
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ns
ns
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ISO35
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PARAMETER MEASUREMENT INFORMATION
VCC1
VCC2
IOA
DE
DE
A
D
D
0 or 3 V
VOD
B
GND1
375 W
A
II
0 or
VCC1
+
VOD
-
B
60 W
IOB
GND2
375 W
GND2
VI
VOA
VOB
GND1
-7 V to 12 V
GND2
Figure 1. Driver VOD Test and Current Definitions
Figure 2. Driver VOD With Common-Mode Loading Test
Circuit
VCC1
IOA
DE
27 W
A
A
VA
B
VB
II
VOD
Input
D
B
VI
VOB
GND1
VOC
27 W
IOB
GND2
GND1
VOA
VOC(SS)
VOC(PP)
VOC
GND2
Figure 3. Test Circuit and Waveform Definitions For The Driver Common-Mode Output Voltage
3V
DE
VCC1
A
D
Input
Generator
VI
B
VI
VOD
RL = 54 W
±1%
CL = 50 pF
±20%
GND1
Generator: PRR = 500 kHz, 50% duty
cycle, tr <6ns, tf <6ns, ZO = 50 W
tPHL
tPLH
VOD
50 W
50%
50%
90%
50%
10%
tr
VOD(H)
90%
50%
10%
tf
VOD(L)
CL includes fixture and
Instrumentation Capacitance
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
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ISO35
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PARAMETER MEASUREMENT INFORMATION (continued)
A
3V
VO
S1
D
3V
VI
B
DE
tPZH
CL includes fixture and
Instrumentation
capacitance
50 W
50%
0V
RL = 110 W
±20%
CL = 50 pF ±20%
Input
Generator
50%
50%
VO
VOH
90%
0V
tPHZ
Figure 5. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
3V
RL = 110W
±1%
A
S1
D
0V
3V
B
0V
tPLZ
VO
CL = 50 pF ±20%
VI
50%
tPZL
DE
Input
Generator
50%
VI
VO
50%
5V
10%
50 W
GND1
VOL
GND2
Generator: PRR = 500 kHz, 50% duty cycle,
tr <6ns, tf <6ns, ZO = 50W
CL includes fixture and
Instrumentation capacitance
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveform
A
IA
IO
R
V
VA
ID
B
VIC
VA+ V B
VO
IB
VB
2
Figure 7. Receiver Voltage and Current Definitions
3V
A
Input
Generator
VI
R
50 W
1.5 V
B
RE
Generator: PRR = 500 kHz, 50% duty cycle,
tr <6ns, tf <6ns, ZO = 50 W
VO
CL = 15 pF
±20%
CL includes fixture and
instrumentation capacitance
50%
VI
tPHL
tPLH
VO
50%
50%
tr
0V
VOH
90%
50%
10%
VOL
tf
Figure 8. Receiver Switching Test Circuit and Waveforms
6
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PARAMETER MEASUREMENT INFORMATION (continued)
R VO
B
0V
Input
Generator
VCC
A
1.5 V
VI
RE
1 kW ±1%
3V
VI
S1
50%
50%
0V
CL = 15 pF ±20%
tPHZ
tPZH
CL includes fixture
and instrumentation
capacitance
90%
50%
VO
VOH
˜˜ 0V
50 W
Generator: PRR = 500 kHz, 50% duty cycle,
tr <6ns, tf <6ns, ZO = 50W
Figure 9. Receiver Enable Test Circuit and Waveforms, Data Output High
R
B
1.5 V
Input
Generator
VCC
A
0V
VI
RE
VO 1 kW ±1%
3V
S1
VI
CL = 15 pF ±20%
50%
50%
0V
CL includes fixture
and instrumentation
capacitance
tPZL
50%
VO
50 W
tPLZ
VCC
10%
VOL
Generator: PRR = 500 kHz, 50% duty cycle,
tr <6ns, tf <6ns, ZO = 50W
Figure 10. Receiver Enable Test Circuit and Waveforms, Data Output Low
0V
RE
A
R
B
Pulse Generator
15 ms duration
1% duty cycle
tr, tf <100 ns
100 W ±1%
+
-
D
DE
3V
Note: This test is conducted to test survivability only.
Data stability at the R output is not specified.
Figure 11. Transient Over-Voltage Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC2
C = 0.1 mF VCC1
±1%
2V
C = 0.1 mF ±1%
DE
GND 1
S1
D
54 W
VOH or VOL
0.8 V
R
VOH or VOL
RE
1 kW
GND 2
GND 1
CL = 15 pF
(includes probe and
jig capacitance)
V TEST
Figure 12. Half-Duplex Common-Mode Transient Immunity Test Circuit
C = 0.1 mF V
CC1
±1%
2V
VCC2
Y
DE
GND1
D
C = 0.1 mF ±1%
54 W
S1
VOH or VOL
Z
A
0.8 V
R
VOH or VOL
1 kW
1.5 V or 0V
54 W
RE
B
0 V or 1.5 V
GND 2
GND 1
CL = 15 pF
(includes probe and
jig capacitance)
V TEST
Figure 13. Full-Duplex Common-Mode Transient Immunity Test Circuit
8
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DEVICE INFORMATION
Table 1. Driver Function Table
ENABLE
INPUT
(DE)
VCC1
VCC2
INPUT
(D)
PU
PU
H
H
H
L
PU
PU
L
H
L
H
PU
PU
X
L
Z
Z
PU
PU
X
OPEN
Z
Z
PU
PU
OPEN
H
H
L
PD
PU
X
X
Z
Z
PU
PD
X
X
Z
Z
PD
PD
X
X
Z
Z
OUTPUTS
A or Y
B or Z
Table 2. Receiver Function Table
DIFFERENTIAL INPUT
VID = (VA – VB)
ENABLE
(RE)
OUTPUT
(R)
PU
–0.01 V ≤ VID
L
H
PU
–0.2 V < VID < –0.01 V
L
?
PU
PU
VID ≤ –0.2 V
L
L
PU
PU
X
H
Z
PU
PU
X
OPEN
Z
PU
PU
Open circuit
L
H
PU
PU
Short Circuit
L
H
PU
PU
Idle (terminated) bus
L
H
PD
PU
X
X
Z
PU
PD
X
L
H
VCC1
VCC2
PU
PU
PACKAGE CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER (1)
TEST CONDITIONS
MIN
L(I01)
Minimum air gap (Clearance)
Shortest terminal to terminal distance through air
8.34
mm
L(I02)
Minimum external tracking (Creepage)
Shortest terminal to terminal distance across the
package surface
8.1
mm
CTI
Tracking resistance (Comparative Tracking
Index)
DIN IEC 60112 / VDE 0303 Part 1
≥175
V
Minimum Internal Gap (Internal Clearance)
Distance through the insulation
0.008
mm
RIO
Isolation resistance
Input to output, VIO = 500 V, all pins on each
side of the barrier tied together creating a
two-terminal device
CIO
Barrier capacitance Input to output
CI
Input capacitance to ground
(1)
TYP
MAX
UNIT
>1012
Ω
VI = 0.4 sin (4E6πt)
2
pF
VI = 0.4 sin (4E6πt)
2
pF
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
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IEC 60664-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
Basic isolation group
Material group
IIIa
Rated mains voltage ≤ 150 VRMS
I-IV
Rated mains voltage ≤ 300 VRMS
I-III
Rated mains voltage ≤ 400 VRMS
I-II
Installation classification
IEC 60747-5-2 INSULATION CHARACTERISTICS
SPECIFICATION
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPECIFICATION
UNIT
560
V
V
VIORM
Maximum working insulation
voltage
VPR
Input to output test voltage
Method b1, VPR = VIORM × 1.875,
100% Production test with t = 1 s, Partial discharge < 5 pC
1050
VIOTM
Transient overvoltage
t = 60 s
4000
V
RS
Insulation resistance
VIO = 500 V at TS
>109
Ω
Pollution degree
(1)
2
Climatic Clasification 40/125/21
REGULATORY INFORMATION
VDE
UL
Certified according to IEC 60747-5-2
Recognized under 1577 Component Recognition Program (1)
File Number: 40016131
File Number: E181974
(1)
10
Production tested ≥3000 VRMS for 1 second in accordance with UL 1577.
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IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply current
DW-16
TS
Maximum case temperature
DW-16
MIN
TYP
θJA = 212°C/W, VI = 5.5 V,
TJ = 170°C, TA = 25°C
MAX
UNIT
210
mA
150
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
Low-K Thermal Resistance (1)
168
High-K Thermal Resistance
96.1
UNIT
θJA
Junction-to-Air
θJB
Junction-to-Board Thermal Resistance
61
°C/W
θJC
Junction-to-Case Thermal Resistance
48
°C/W
PD
Device Power Dissipation
(1)
VCC1 = VCC2 = 5.25 V, TJ = 150°C, CL = 15 pF,
Input a 20 MHz 50% duty cycle square wave
°C/W
220
mW
Tested in accordance with the Low-K or High-K thermal metric defintions of EIA/JESD51-3 for leaded surface mount packages.
300
275
Safety Limiting Current - mA
250
225
200
VCC1,2 at 3.6 V
175
150
125
100
75
50
25
0
0
50
100
150
200
TC - Case Temperature - °C
Figure 14. DW-16 θJC Thermal Derating Curve per IEC 60747-5-2
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EQUIVALENT CIRCUIT SCHEMATICS
A Input
B Input
VCC
16V
VCC
36kW
16V
180kW
180kW
Input
36kW
Input
16V
16V
36kW
36kW
Y and Z Outputs
A and B Outputs
VCC
VCC
16V
16V
Output
Output
16V
16V
D, RE Input
VCC1
DE Input
VCC1
VCC1
VCC1
VCC1
1 MW
500W
500W
Input
Input
1 MW
VCC1
R Output
4W
Output
6.5W
12
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ISO15 ISO35
ISO15
ISO35
www.ti.com................................................................................................................................................................ SLOS580B – MAY 2008 – REVISED JULY 2008
TYPICAL CHARACTERISTICS CURVES
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
140
-120
No Load
o
TA = 25 C
No Load
TA = 25oC
120
-100
IO - Output Current - mA
IO - Output Current - mA
100
80
60
40
-60
-40
-20
20
0
0
0
1
2
3
4
0
5
1
2
3
VO - Output Voltage - V
VO - Output Voltage - V
Figure 15.
Figure 16.
RMS SUPPLY CURRENT
vs
SIGNALING RATE
BUS INPUT CURRENT
vs
INPUT VOLTAGE
4
60
25
No Load
o
TA = 25 C
40
II - Bus Input Current - mA
20
RMS Supply Current - mA
-80
ICC2
15
10
ICC1
5
TA = 25°C
RE = 0 V
DE = 0 V
20
0
VCC = 3.3 V
-20
-40
0
0
200
400
600
800
1000
-60
-7
-4
-1
2
5
8
11
14
VI - Bus Input Voltage - V
Signaling Rate - kbps
Figure 17.
Figure 18.
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ISO15 ISO35
13
ISO15
ISO35
SLOS580B – MAY 2008 – REVISED JULY 2008................................................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS CURVES (continued)
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
DRIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
2.5
3.6 V
13
RL = 60 W
2.3
Driver Propagation Delay - ns
VOD - Differential Output Voltage - V
2.4
14
2.2
3.3 V
2.1
2
1.9
3V
1.8
1.7
3V
11
3.6 V
10
9
8
7
1.6
1.5
-60
12
-40
-20
0
20
40
60
80 90
6
-60
-40
o
TA - Free-Air Temperature - C
Figure 19.
14
-20
0
20
40
60
80 90
o
TA - Free-Air Temperature - C
Figure 20.
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ISO15 ISO35
ISO15
ISO35
www.ti.com................................................................................................................................................................ SLOS580B – MAY 2008 – REVISED JULY 2008
APPLICATION INFORMATION
Transient Voltages
Isolation of a circuit insulates it from other circuits and earth so that noise develops across the insulation rather
than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical fast
transients that occur after installation. The transient ratings of the ISO15 and ISO35 are sufficient for all but the
most severe installations. However, some equipment manufacturers use their ESD generators to test transient
susceptibility of their equipment, and can exceed insulation ratings. ESD generators simulate static discharges
that may occur during device or equipment handling with low-energy but high voltage transients.
Figure 21 models the ISO15 and ISO35 bus IO connected to a noise generator. CIN and RIN is capacitance or
resistance across the device and any other stray or added capacitance or resistance across the A or B pin to
GND2. CISO and RISO is the capacitance and resistance between GND1 and GND2 of the ISO15 and ISO35 plus
those of any other insulation (transformer, etc.). The stray inductance is assumed to be negligible. From this
model, the voltage at the isolated bus return is,
ZISO
VGND2 = VN
ZISO + ZIN
(1)
and will always be less than 16 V from VN. If the ISO15 and ISO35 are tested as a stand-alone device, RIN = 6
‫נ‬104Ω, CIN = 16 ‫נ‬10–12 F, RISO = 109Ω and CISO = 10–12 F.
Note from Figure 21 that the resistor ratio determines the voltage ratio at low frequency and it is the inverse
capacitance ratio at high frequency. In the stand-alone case and for low frequency,
VGND2
RISO
109
=
=
VN
RISO + RIN
109 + 6x104
(2)
or essentially all of noise appears across the barrier. At high frequency,
VGND2
=
VN
1
CISO
1
CISO
+
1
CIN
1
=
CISO
CIN
1 +
=
1
1 +
1
16
= 0.94
(3)
and 94% of VN appears across the barrier. As long as RISO is greater than RIN and CISO is less than CIN, most of
transient noise appears across the isolation barrier.
It is not recommend for the user to test equipment transient susceptibility with ESD generators, or consider
product claims of ESD ratings above the barrier transient ratings of an isolated interface. ESD is best managed
through recessing or covering connector pins in a conductive connector shell and installer training.
A, B, Y, or Z
CIN
VN
RIN
16V
Bus Return (GND2)
CISO
RISO
System Ground (GND1)
Figure 21. Noise Model
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Product Folder Link(s): ISO15 ISO35
15
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ISO15DW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO15DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO15DWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO15DWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO35DW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO35DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO35DWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO35DWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO15DWR
SOIC
DW
16
2000
330.0
16.4
10.9
10.78
3.0
12.0
16.0
Q1
ISO35DWR
SOIC
DW
16
2000
330.0
16.4
10.9
10.78
3.0
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO15DWR
SOIC
DW
16
2000
358.0
335.0
35.0
ISO35DWR
SOIC
DW
16
2000
358.0
335.0
35.0
Pack Materials-Page 2
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