Renesas M38C35M9A Single-chip 8-bit cmos microcomputer Datasheet

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●LCD drive control circuit
Bias ............................................................................ 1/1, 1/2, 1/3
Duty .................................................................... 1/1, 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 32
●2 Clock generating circuit
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................... 4.0 to 5.5 V
In middle-speed mode ................................................ 2.5 to 5.5 V
In low-speed mode ...................................................... 2.5 to 5.5 V
●Power dissipation
In high-speed mode ........................................................... 32 mW
(at 8 MHz oscillation frequency)
In low-speed mode .............................................................. 45 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range .................................... – 20 to 85°C
DESCRIPTION
The 38C3 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38C3 group has a LCD drive control circuit, a 10-channel A-D
converter, and a Serial I/O as additional functions.
The various microcomputers in the 38C3 group include variations of
internal memory size and packaging. For details, refer to the section
on part numbering.
For details on availability of microcomputers in the 38C3 group, refer
to the section on group expansion.
FEATURES
●Basic machine-language instructions ....................................... 71
●The minimum instruction execution time ............................. 0.5 µs
(at 8MHz oscillation frequency)
●Memory size
ROM .................................................................. 4 K to 48 K bytes
RAM ................................................................. 192 to 1024 bytes
●Programmable input/output ports ............................................. 57
●Software pull-up/pull-down resistors
..................................................... (Ports P0–P8 except Port P51)
●Interrupts ................................................... 16 sources, 16 vectors
(includes key input interrupt)
●Timers ............................................................ 8-bit ✕ 6, 16-bit ✕ 1
●A-D converter ................................................. 10-bit ✕ 8 channels
●Serial I/O ....................................... 8-bit ✕ 1 (Clock-synchronized)
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
41
43
42
45
44
46
48
47
50
49
52
51
54
53
56
55
58
57
60
59
62
65
40
66
39
67
68
38
37
69
36
35
34
70
71
72
33
M38C34M6AXXXFP
73
32
74
31
75
30
76
77
29
28
78
27
79
26
25
24
22
23
21
20
18
19
17
16
13
14
15
12
9
10
11
8
5
6
7
4
3
P61/AN1
P60/AN0
P57/INT2
P56/INT1
P55/INT0
P54/CNTR1
P53/CNTR0
P52/PWM1
P51
RESET
P71/XcOUT
P70/XcIN
VSS
XIN
XOUT
VCC
P50/TAOUT
P87
P86
P85
P84
P83
P82
P81
2
80
1
P47/SRDY
P46/SCLK1
P45/SOUT
P44/SIN
P43/φ
P42/T3OUT
P41/T1OUT
P40/SCLK2
AVSS
VREF
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
61
64
63
P20/SEG0
P21/SEG1
P22/SEG2
P23/SEG3
P24/SEG4
P25/SEG5
P26/SEG6
P27/SEG7
P00/SEG8
P01/SEG9
P02/SEG10
P03/SEG11
P04/SEG12
P05/SEG13
P06/SEG14
P07/SEG15
P10/SEG16
P11/SEG17
P12/SEG18
P13/SEG19
P14/SEG20
P15/SEG21
P16/SEG22
P17/SEG23
PIN CONFIGURATION (TOP VIEW)
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 M38C34M6AXXXFP pin configuration
P30/SEG24
P31/SEG25
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
COM0
COM1
COM2
COM3
VL1
VL2
VL3
P80
XCIN
12 11
P7(2)
XCOUT
Subclock
output
I/O port P7
XCOUT
XCIN
Subclock
input
1
φ
I/O port P6
2 75 76 77 78 79 80
P6(8)
S
PS
PCL
(0V)
VREF
AVSS
74 73
A-D converter(10)
PCH
Y
X
A
3
4
5
6
7
P5(8)
8
9 17
CNTR0,CNTR1
I/O port P5
14
C P U
10
15
Clock generating
circuit
Reset input
RESET
Main
clock
output
XOUT
Main
clock
input
XIN
INT0–INT2
Fig. 2 Functional block diagram
Timer 6(8)
Timer 5(8)
P4(8)
I/O port P4
65 66 67 68 69 70 71 72
PWM0,PWM1
SI/O(8)
Timer 4(8)
Timer 3(8)
Timer A(16)
Timer 2(8)
Timer 1(8)
ROM
ROM corrective
RAM
(8 bytes)
13
16
ROM
corrective
circuit
(0V)
VSS
(5V)
VCC
Data bus
φ
2
T1OUT, T3OUT
FUNCTIONAL BLOCK DIAGRAM
Output port P3
33 34 35 36 37 38 39 40
P3(8)
LCD display
RAM
(16 bytes)
RAM
I/O port P2
57 58 59 60 61 62 63 64
P2(8)
LCD
drive control
circuit
Key-on wake-up
I/O port P1
41 42 43 44 45 46 47 48
P1(8)
I/O port P8
P8(8)
I/O port P0
49 50 51 52 53 54 55 56
P0(8)
18 19 20 21 22 23 24 25
VL1
VL2
VL3
COM0
COM1
COM2
29 COM3
30
31
32
26
27
28
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
VCC , VSS
VREF
Name
RESET
XIN
Power source
Analog reference
voltage
Analog power
source
Reset input
Clock input
XOUT
Clock output
VL1 – VL3
LCD power
source
Common output
AVSS
COM0 –
COM3
P00/SEG9 –
P07/SEG15
I/O port P0
P10/SEG 16 – I/O port P1
P17/SEG23
P20/SEG 0 –
P27/SEG 7
Function except a port function
• Apply voltage of 2.5 V to 5.5 V to VCC , and 0 V to VSS.
• Reference voltage input pin for A-D converter.
•
•
•
•
•
•
GND input pin for A-D converter.
Connect to V SS.
Reset input pin for active “L.”
Input and output pins for the main clock generating circuit.
Feedback resistor is built in between XIN pin and XOUT pin.
Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
• Input 0 – V L3 voltage to LCD.
• LCD common output pins.
• COM1, COM2, and COM 3 are not used at 1/1 duty ratio.
• COM2 and COM3 are not used at 1/2 duty ratio.
• COM3 is not used at 1/3 duty ratio.
• 8-bit I/O port.
• LCD segment pins
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each port to be individually
programmed as either input or output.
• Pull-down control is enabled.
I/O port P2
P30/SEG 24 – Output port P3
P37/SEG 31
P40/S CLK2
P41/T 1OUT
P42/T 3OUT
P43/φ
P44/S IN,
P45/SOUT,
P46/S CLK1,
P47/SRDY
Function
I/O port P4
• 8-bit output port.
• CMOS state output.
• Pull-down control is enabled.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
• Serial I/O function pin
• Timer output pin
• Timer output pin
• φ output pin
• Serial I/O function pins
3
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Pin
Name
P51
Input port P5
P50/TAOUT
P52/PWM 1
P53/CNTR0,
P54/CNTR1
P55/INT 0,
P56/INT 1,
P57/INT 2
P60/AN0 –
P67/AN7
I/O port P5
P70/XCOUT,
P71/X CIN
I/O port P7
P80 – P8 7
I/O port P8
I/O port P6
Function
•
•
•
•
•
•
1-bit input pin.
CMOS compatible input level.
7-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
2-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
8-bit I/O port.
TTL input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
Function except a port function
• Timer A output pin
• PWM1 output (timer output) pin
• External count I/O pins
• External interrupt input pins
• A-D conversion input pins
• Sub-clock generating circuit I/O pins
• Key input (Key-on wake-up) interrupt
input pins
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M38C3
4
M
6 A
XXX
FP
Package type
FP : 80P6N-A package
FS : 80D0 package
ROM number
Omitted in some types.
A : Standard(Note)
M : M version
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
Note : Difference between standard and M version
• Standard : Port P50 /TAOUT pin remains set to the input mode until the direction
register is set to the output mode during reset and after
reset.
• M version : Port P50 /TAOUT pin remains set to the output mode (“L” output) until
the direction register is set to the input mode during reset
and after reset.
Fig. 3 Part numbering
5
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 38C3 group as follows.
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions
Memory Size
ROM/PROM size ................................................ 16 K to 48 K bytes
RAM size ............................................................. 512 to 1024 bytes
Memory Expansion Plan
Under development
ROM size (bytes)
48K
M38C37ECA/ECM
44K
40K
36K
32K
28K
Under development
24K
M38C34M6A/M6M
20K
Planning
16K
M38C33M4
12K
8K
4K
192 256
384
512
640
768
896
1024
RAM size (bytes)
Products under development or planning : the development schedule and specification may be revised without notice.
Planning products may be stopped the development.
Fig. 4 Memory expansion plan
Currently planning products are listed below.
Table 3 Support products
Product name
M38C34M6AXXXFP
M38C37ECAXXXFP
M38C37ECAFP
M38C37ECAFS
M38C34M6MXXXFP
M38C37ECMXXXFP
M38C37ECMFP
M38C37ECMFS
6
As of April 1998
(P) ROM size (bytes)
ROM size for User in ( )
24576 (24446)
RAM size
(bytes)
640
Package
80P6N-A
49152 (49022)
1024
24576 (24446)
640
49152 (49022)
1024
80D0
80P6N-A
80D0
Remarks
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 38C3 group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the
internal system clock selection bit.
The CPU mode register is allocated at address 003B16 .
b7
b0
CPU mode register
(CPUM (CM) : address 003B 16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : RAM in the zero page is used as stack area
1 : RAM in page 1 is used as stack area
Not used (returns “1” when read)
(Do not write “0” to this bit.)
Port XC switch bit
0 : I/O port
1 : X CIN, XCOUT
Main clock ( X IN –XOUT ) stop bit
0 : Operating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN )/2 (high-speed mode)
1 : f(XIN )/8 (middle-speed mode)
Internal system clock selection bit
0 : X IN-X OUT selected (middle-/high-speed mode)
1 : X CIN-X COUT selected (low-speed mode)
Fig. 5 Structure of CPU mode register
7
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
Access to this area with only 2 bytes is possible in the special page
addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
000016
RAM size
(bytes)
Address
XXXX16
192
00FF 16
004016
256
013F 16
005016
384
01BF16
512
023F 16
640
02BF16
768
033F 16
896
03BF16
1024
043F 16
SFR area 1
LCD display RAM area
ROM corrective RAM area
(Note 1)
Zero page
005816
RAM
010016
XXXX16
Reserved area
044016
Not used
0F00 16
0FFF16
ROM area
ROM size
(bytes)
Address
YYYY16
Address
ZZZZ 16
4096
F000 16
F080 16
8192
E00016
E080 16
12288
D00016
D08016
16384
C00016
C08016
20480
B00016
B080 16
24576
A00016
A080 16
28672
900016
908016
32768
800016
808016
36864
700016
708016
40960
600016
608016
45056
500016
508016
49152
400016
408016
SFR area 2 (Note 1)
YYYY16
Reserved ROM area
(128 bytes)
ZZZZ 16
ROM
FF0016
FFDC16
Interrupt vector area
FFFE16
Reserved ROM area
FFFF 16
Note 1 : This is valid only in mask ROM version.
Fig. 6 Memory map diagram
8
Special page
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
002016 Timer 1 (T1)
002116 Timer 2 (T2)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
002216 Timer 3 (T3)
002316 Timer 4 (T4)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
002416 Timer 5 (T5)
000616 Port P3 (P3)
002616
000716
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
002716 Timer 6 PWM register (T6PWM)
002816 Timer 12 mode register (T12M)
002916 Timer 34 mode register (T34M)
000A16 Port P5 (P5)
000B16 Port P5 direction register (P5D)
002A16 Timer 56 mode register (T56M)
002B16 φ output control register (CKOUT)
000C16 Port P6 (P6)
000D16 Port P6 direction register (P6D)
002C16 Timer A register (low) (TAL)
002D16 Timer A register (high) (TAH)
000E16 Port P7 (P7)
000F16 Port P7 direction register (P7D)
002E16 Compare register (low) (CONAL)
001016 Port P8 (P8)
001116 Port P8 direction register (P8D)
003016 Timer A mode register (TAM)
003116 Timer A control register (TACON)
001216
003216 A-D control register (ADCON)
001316
001416
003316 A-D conversion register (low) (ADL)
003416 A-D conversion register (high) (ADH)
001516
003516
001616 PULL register A (PULLA)
001716 PULL register B (PULLB)
003616
001816 Port P8 output selection register (P8SEL)
001916 Serial I/O control register 1 (SIOCON1)
003816 Segment output enable register (SEG)
001A16 Serial I/O control register 2 (SIOCON2)
001B16 Serial I/O register (SIO)
002516 Timer 6 (T6)
002F16 Compare register (high) (CONAH)
003716
003916 LCD mode register (LM)
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
001C16
001D16
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
001E16
001F16
0F01 16 ROM correct enable register 1 (Note)
0F02 16 ROM correct high-order address register 1 (Note)
0F0316 ROM correct low-order address register 1 (Note)
0F0A16 ROM correct high-order address register 5 (Note)
0F0B16 ROM correct low-order address register 5 (Note)
0F0C16 ROM correct high-order address register 6 (Note)
0F04 16 ROM correct high-order address register 2 (Note)
0F0D16 ROM correct low-order address register 6 (Note)
0F05 16 ROM correct low-order address register 2 (Note)
0F0616 ROM correct high-order address register 3 (Note)
0F0E16 ROM correct high-order address register 7 (Note)
0F0F16 ROM correct low-order address register 7 (Note)
0F10 16 ROM correct high-order address register 8 (Note)
0F07 16 ROM correct low-order address register 3 (Note)
0F08 16 ROM correct high-order address register 4 (Note)
0F11 16 ROM correct low-order address register 8 (Note)
0F0916 ROM correct low-order address register 4 (Note)
Note: This register is valid only in mask ROM version.
Fig. 7 Memory map of special function register (SFR)
9
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
[Direction Registers (ports P2, P4, P50, P52–P57,
and P6–P8)]
b7
b0
PULL register A
(PULLA : address 0016 16)
The I/O ports P2, P4, P50, P52–P5 7, and P6–P8 have direction registers which determine the input/output direction of each individual
pin. Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
P00 –P07 pull-down
P10 –P17 pull-down
P20 –P27 pull-down
Not used
P70 , P71 pull-up
P80 –P87 pull-up
Not used (return “0” when read)
b7
b0
PULL register B
(PULLB : address 0017 16)
P40 –P43 pull-up
P44 –P47 pull-up
[Direction Registers (ports P0 and P1)]
P50 , P52 , P53 pull-up
P54 –P57 pull-up
Ports P0 and P1 have direction registers which determine the input/
output direction of each individual port.
Each port in a direction register corresponds to one port, each port
can be set to be input or output.
When “0” is written to the bit 0 of a direction register, that port becomes an input port. When “1” is written to that port, that port becomes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used.
P60 , P63 pull-up
P64 –P67 pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
Note : The contents of PULL register A and PULL register B
do not affect ports programmed as the output ports.
Fig. 8 Structure of PULL register A and PULL register B
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL register
B (address 001716), ports except for ports P3 and P51 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with a
program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
b7
b0
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
Port P8 Output Selection
Ports P80 to P87 can be switched to N-channel open-drain output by
setting “1” to the port P8 output selection register.
Port P8 output selection register
(P8SEL : address 0018 16)
Fig. 9 Structure of port P8 output selection register
Table 4 List of I/O port function (1)
Pin
P00 /SEG8 –
P07 /SEG15
Name
Port P0
Input/Output
Input/Output,
port unit
P10 /SEG16 –
P17 /SEG23
Port P1
Input/Output,
port unit
P20 /SEG0 –
P27 /SEG7
Port P2
Input/Output,
individual bits
P30 /SEG24 –
P37 /SEG31
Port P3
Output,
individual bits
10
I/O format
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
CMOS 3-state output
Non-port function
LCD segment output
CMOS 3-state output
LCD segment output
LCD segment output
LCD segment output
Related SFRs
Ref. No.
PULL register A
(1)
Segment output enable register
PULL register A
Segment output enable register
PULL register A
Segment output enable register
Segment output enable reg(2)
ister
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 5 List of I/O port function (2)
Pin
P40/SCLK2
Name
Port P4
Input/Output
Input/Output,
individual bits
I/O format
CMOS compatible input
level
CMOS 3-state output
Non-port function
Serial I/O function I/O
P41/T1OUT
Timer output
P42/T3OUT
Timer output
P43/φ
φ clock output
P44/SIN
P45/SOUT
P46/SCLK1
P4 7/SRDY
Serial I/O function I/O
P5 0/TAOUT
Port P5
P51
Input/Output,
individual bits
Input
P52/PWM 1
Input/Output,
individual bits
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS compatible input
level
CMOS 3-state output
Timer A output
Related SFRs
Ref. No.
Serial I/O control registers
(3)
1, 2
PULL register B
Timer 12 mode register
(4)
PULL register B
Timer 34 mode register
(4)
PULL register B
φ output control register
(5)
PULL register B
Serial I/O control registers
(6)
1, 2
(7)
PULL register B
(8)
(9)
Timer A mode register
(10)
Timer A control reigster
PULL register B
(11)
PWM output
Timer 56 mode register
PULL register B
(4)
P53/CNTR0
P54/CNTR1
External count I/O
(12)
P55/INT0
P56/INT1
P57/INT2
P60/AN0
–
P67/AN7
External interrupt input
Interrupt edge selection register
PULL register B
Interrupt edge selection register
PULL register B
A-D control register
PULL register B
Sub-clock generating
circuit I/O
CPU mode register
PULL register A
(14)
Key input (key-on
wake-up) interrupt input
Interrupt control register 2
PULL register A
(17)
LCD mode register
(16)
Port P6
Input/Output,
individual bits
Port P7
Input/Output,
individual bits
P80 – P87
Port P8
Input/Output,
individual bits
COM0 – COM3
Common
P70/XCIN
P71/XCOUT
Output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
LCD common output
A-D converter input
(12)
(13)
(15)
Notes 1: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to V SS through the input-stage gate.
2: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double function ports as function I/O ports, refer to the
applicable sections.
11
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1)Ports P0, P1, P2
(2)Port P3
VL2/VL3
VL2/VL3
VL1/VSS
VL1/VSS
Segment output enable bit
(Note)
Segment output enable bit
Direction register
Data bus
Port latch
Data bus
Port latch
Pull-down control
Pull-down control
Segment output enable bit
Segment output enable bit
Note : Port P0, P1 direction registers are only bit 0.
(4)Ports P4 1, P42, P52
(3)Port P4 0
P-channel output disable bit
Pull-up control
Serial I/O mode selection bit
Timer 1 output selection bit
Timer 3 output selection bit
Timer 6 output selection bit
Pull-up control
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
Timer 1 output
Timer 3 output
Timer 6 output
Serial I/O clock output
(6)Port P4 4
(5)Port P4 3
Pull-up control
Pull-up control
Direction register
Direction register
Data bus
Port latch
φ output control bit
φ
Fig. 10 Port block diagram (1)
12
Data bus
Port latch
Serial I/O input
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(8)Port P4 6
(7)Port P4 5
Pull-up control
P-channel output disable bit
P-channel output disable bit
Serial I/O port selection bit
Serial I/O mode selection bit
Direction register
Data bus
Pull-up control
Direction register
Port latch
Data bus
Serial I/O output
Port latch
Serial I/O clock output
Serial I/O clock input
(9)Port P4 7
(10)Port P5 0
Pull-up control
Pull-up control
SRDY output enable bit
Timer A output enable bit
(Note)
Direction register
Direction register
Data bus
Port latch
Data bus
Serial I/O ready output
Port latch
Timer A output
(12)Ports P5 3–P57
(11)Port P5 1
Pull-up control
Data bus
Direction register
Data bus
Note: The initihal value of M version becomes “1” (output).
Port latch
INT0–INT2 interrupt input
CNTR0,CNTR 1 interrupt input
Fig. 11 Port block diagram (2)
13
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(14)Port P7 0
(13)Port P6
Port selection • pull-up control
Pull-up control
Port Xc switch bit
Direction register
Data bus
Direction register
Port latch
Data bus
Port latch
A-D conversion input
Analog input pin selection bit
(15)Port P7 1
Sub-clock generating circuit input
(16)COM 0–COM3
Port selection • pull-up control
VL3
Port Xc switch bit
Direction register
VL2
VL1
Data bus
The gate input signal of each
transistor is controlled by the
LCD duty ratio and the bias
value.
Port latch
Oscillator
Port P70
Port Xc switch bit
(17)Port P8
Pull-up control
P-channel output disable bit
Direction register
Data bus
Port latch
Key input (key-on wake-up) interrupt input
Fig. 12 Port block diagram (3)
14
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by sixteen sources: six external, nine internal, and
one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Interrupts
When the active edge of an external interrupt (INT0 – INT2 , CNTR0
or CNTR1) is set or an vector interrupt source where several interrupt
source is assigned to the same vector address is switched, the corresponding interrupt request bit may also be set. Therefore, take following sequence:
(1) Disable the interrupt.
(2) Change the active edge in interrupt edge selection register.
(3) Clear the set interrupt request bit to “0.”
(4) Enable the interrupt.
15
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 Interrupt vector addresses and priority
Interrupt Source Priority
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
FFFB16
FFFA16
Interrupt Request
Generating Conditions
Reset (Note 2)
INT0
1
2
INT1
3
FFF916
FFF816
INT2
4
FFF716
FFF616
Serial I/O
5
FFF516
FFF416
Timer A
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
CNTR0
6
7
8
9
10
11
12
13
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
CNTR1
14
FFE316
FFE216
Key input (Keyon wake-up)
A-D conversion
15
FFE116
FFE016
16
FFDF16
FFDE16
At reset
At detection of either rising or falling edge of
INT0 intput
At detection of either rising or falling edge of
INT1 input
At detection of either rising or falling edge of
INT2 input
At completion of serial I/O data transmit/receive
At timer A underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At falling of port P8 (at input) input logical level
AND
At completion of A-D conversion
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
16
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(falling valid)
Valid when A-D conversion interrupt
is selected
Non-maskable software interrupt
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 13 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A 16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit 0 : Falling edge active
INT2 interrupt edge selection bit 1 : Rising edge active
Not used (return “0” when read)
CNTR0 active edge switch bit 0 : Falling edge active, rising edge count
CNTR1 active edge switch bit 1 : Rising edge active, falling edge count
b7
b0
Interrupt request register 1
(IREQ1 : address 003C 16 )
b7
b0
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Serial I/O interrupt request bit
Timer A interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Interrupt request register 2
(IREQ2 : address 003D 16 )
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Key input interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 1
(ICON1 : address 003E 16)
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Serial I/O interrupt enable bit
Timer A interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
b7
b0
Interrupt control register 2
(ICON2 : address 003F 16)
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Key input interrupt enable bit
AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 14 Structure of interrupt-related registers
17
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-on Wake-Up)
of using a key input interrupt is shown in Figure 15, where an interrupt request is generated by pressing one of the keys consisted as
an active-low key matrix which inputs to ports P80–P8 3.
A key input interrupt request is generated by applying “L” level to any
pin of port P8 that have been set to input mode. In other words, it is
generated when AND of input level goes from “1” to “0”. An example
Port PXx
“L” level output
PULL register A
Bit 5 = “1”
Port P87
direction register = “1”
✽
✽✽
✽
✽✽
✽
✽✽
✽
✽✽
✽
✽✽
✽
✽✽
Key input interrupt request
Port P87
latch
P87 output
Port P86
direction register = “1”
Port P86
latch
P86 output
Port P85
direction register = “1”
Port P85
latch
P85 output
Port P84
direction register = “1”
Port P84
latch
P84 output
P83 input
P82 input
Port P83
direction register = “0”
Port P83
latch
Port P8
Input reading circuit
Port P82
direction register = “0”
Port P82
latch
Port P81
direction register = “0”
✽
✽✽
✽
✽✽
P81 input
P80 input
Port P81
latch
Port P80
direction register = “0”
Port P80
latch
✽ P-channel transistor for pull-up
✽ ✽ CMOS output buffer
Fig. 15 Connection example when using key input interrupt and port P8 block diagram
18
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
8-Bit Timer
The 38C3 group has six built-in timers : Timer 1, Timer 2, Timer 3,
Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016,” an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1.”
The count can be stopped by setting the stop bit of each timer to “1.”
The system clock φ can be set to either the high-speed mode or lowspeed mode with the CPU mode register. At the same time, timer
internal count source is switched to either f(XIN) or f(XCIN).
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 is output from the P4 1/T1OUT pin. The waveform polarity changes each time timer 1 overflows. The active edge
of the external clock CNTR0 can be switched with the bit 6 of the
interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0,” timer 1 is set to “FF 16,” and timer 2 is
set to “0116.”
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 is output from the P42/T3OUT pin. The waveform polarity changes each time timer 3 overflows. The active edge
of the external clock CNTR1 can be switched with the bit 7 of the
interrupt edge selection register.
●Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P52/PWM1 pin.
●Timer 6 PWM1 Mode
Timer 6 can output a rectangular waveform with “H” duty cycle n/
(n+m) from the P52/PWM 1 pin by setting the timer 56 mode register
(refer to Figure 17). The n is the value set in timer 6 latch (address
0025 16) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
b7
b0
Timer 12 mode register
(T12M: address 0028 16)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/16 or f(X CIN)/16
01 : f(XCIN)
10 : f(XIN)/32 or f(X CIN)/32
11 : f(XIN)/128 or f(X CIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR 0
11 : Not available
Timer 1 output selection bit (P4 1)
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
Timer 34 mode register
(T34M: address 0029 16)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/32 or f(XCIN)/32
11 : f(XIN)/128 or f(X CIN)/128
Timer 4 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR 1
11 : Not available
Timer 3 output selection bit (P4 2)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
Timer 56 mode register
(T56M: address 002A 16)
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/16 or f(X CIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/16 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P5 2)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Fig. 16 Structure of Timer Related Register
19
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
XCIN
Timer 1 count source
“1”
Internal system clock
selection bit
1/16
XIN
“0”
RESET
Timer 1 latch (8)
1/2
1/32
“01” selection bit
FF16
Timer 1 (8)
“00”
“10”
STP instruction
Timer 1 interrupt request
Timer 1 count
stop bit
1/128
P41/T1OUT
“11”
P41 latch
1/2
Timer 1 output selection bit
Timer 2 latch (8)
“00”
P41 direction register
Timer 2 count source
selection bit
0116
Timer 2 (8)
Timer 2 interrupt request
“01”
Timer 2 count
stop bit
“10”
P53/CNTR0
Rising/Falling
active edge switch
Timer 3 latch (8)
“01”
“00”
P42/T3OUT
Timer 3 count source
selection bit
Timer 3 (8)
Timer 3 count
stop bit
“10”
P42 latch
Timer 3 interrupt request
“11”
1/2
Timer 3 output selection bit
Timer 4 latch (8)
“01”
P42 direction register
Timer 4 count source
selection bit
Timer 4 (8)
“00”
P54/CNTR1
Timer 4 interrupt request
Timer 4 count
stop bit
“10”
Rising/Falling
active edge switch
CNTR1 interrupt request
Timer 5 latch (8)
“1”
Timer 5 count source
selection bit
Timer 5 (8)
“0”
Timer 5 count
stop bit
“01”
Timer 6 count source
selection bit
Timer 5 interrupt request
Timer 6 latch (8)
Timer 6 (8)
“00”
Timer 6 count
stop bit
“10”
Timer 6 PWM register (8)
P52/PWM1
P52 latch
“1”
“0”
PWM
1/2
Timer 6 output selection bit
Timer 6 operation
mode selection bit
P52 direction register
Fig. 17 Block diagram of timer
20
Timer 6 interrupt request
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts
Timer 6
count source
Timer 6
PWM mode
n ✕ ts
m ✕ ts
(n+m) ✕ ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n+m) and period : (n+m) ✕ ts) is output.
n: setting value of Timer 6
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 18 Timing chart of timer 6 PWM1 mode
16-bit Timer
Timer A is a 16-bit timer that can be selected in one of four modes by
the timer A mode register and the timer A control register.
●Timer A
The timer A operates as down-count. When the timer contents reach
“000016”, an underflow occurs at the next count pulse and the timer
latch contents are reloaded. After that, the timer continues countdown. When the timer underflows, the interrupt request bit corresponding to the timer A is set to “1”.
(1) Timer mode
The count source can be selected by setting the timer A mode register.
types of delay time by a delay circuit.
When using this mode, set port P55 sharing the INT 0 pin to input
mode and set port P50 sharing the TAOUT pin to output mode.
It is possible to force the timer A output to be “L” using pins INT1 and
INT2 by the timer A control register.
(4) PWM mode
IGBT dummy output, an external trigger with the INT0 pin and output
control with pins INT1 and INT2 are not used. Except for those, this
mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer A set value.
The “H” term is specified by the compare register set value.
When using this mode, set port P50 sharing the TAOUT pin to output
mode.
(2) Pulse output mode
Pulses of which polarity is inverted each time the timer underflows
are output from the TAOUT pin. Except for that, this mode operates
just as in the timer mode.
When using this mode, set port P50 sharing the TAOUT pin to output
mode.
(3) IGBT output mode
After dummy output from the TA OUT pin, count starts with the INT0
pin input as a trigger. When the trigger is detected or the timer A
underflows, “H” is output from the the TAOUT pin.
When the count value corresponds with the compare register value,
the TAOUT output becomes “L”. When the INT0 signal becomes “H”,
the TAOUT output is forced to become “L”.
After noise is cleared by noise filters, judging continuous 4-time same
levels with sampling clocks to be signals, the INT0 signal can use 4
21
MITSUBISHI MICROCOMPUTERS
38C3 Group
Delay circuit
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Noise filter
(4-time same levels judgement)
INT0
XIN
Divider
Divider
Noise filter sampling
clock selection bit
Internal trigger start
“00”, “01”, “11”
1/4
Timer A count
source selection bit
Timer A write control bit
Timer A (high-order) latch (8) Timer A (low-order) latch (8)
Timer A (high-order) (8)
“1”
INT1
Data bus
Timer A
operating
mode bits “10”
1/2
1/1
1/2
1/4
1/8
External trigger delay
time selection bit
0µs
“00”
4/f(X IN) “01”
8/f(X IN) “10”
16/f(X IN) “11”
Timer A underflow
interrupt request
Timer A (low-order) (8)
TAOUT output
control bit 1
Match
“0”
Compare register (high-order) (8) Compare register (low-order) (8)
“1”
INT2
TAOUT output
control bit 2
Timer A operating
mode bits
“00”, “01”, “11”
“0”
TAOUT active
edge switch bit
“10”
“0”
R
QS
D
“1”
Q
IGBT output mode
PWM mode
P50/TAOUT
(Note) P50
direction
register
P50 latch
“0”
Q
Output selection bit
Timer A start
signal
Pulse output mode
SS
T
“1”
TAOUT active
edge switch bit
Q
Note: The initial value of M version becomes “1” (output).
Fig. 19 Block diagram of timer A
b7
b7
b0
Timer A control register
(TACON : address 0031 16)
Timer A operating mode bits
00 : Timer mode
01 : Pulse output mode
10 : IGBT output mode
11 : PWM mode
Timer A write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch onl y
Timer A count source selection bits
0 0 : f(XIN)
0 1 : f(XIN)/2
1 0 : f(XIN)/4
1 1 : f(XIN)/8
Timer A output active edge switch bit
0 : Output starts with “L” level
1 : Output starts with “H” level
Timer A count stop bit
0 : Count operating
1 : Count stop
Timer A output selection bit (P5 0)
0 : I/O port
1 : Timer A output
Noise filter sampling clock selection bit
0 : f(XIN)/2
1 : f(XIN)/4
External trigger delay time selection bits
0 0 : No delay
0 1 : ( 4/f(XIN))µs
1 0 : ( 8/f(XIN))µs
1 1 : (16/f(XIN))µs
Timer A output control bit 1 (P5 6)
0 : Not used
1 : INT1 interrupt used
Timer A output control bit 2 (P5 7)
0 : Not used
1 : INT2 interrupt used
Not used (returns “0” when read)
Fig. 20 Structure of timer A related registers
22
b0
Timer A mode register
(TAM : address 0030 16)
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts
Timer A count
source
Timer A
PWM mode
IGBT output mode
(n-m+1) ✕ ts
m ✕ ts
(n+1) ✕ ts
Note: PWM waveform (duty : (n-m+1)/(n+1) and period : (n+1) ✕ ts) is output.
n : setting value of Timer A
m : setting value of compare register
ts : period of Timer A count source
Fig. 21 Timing chart of timer A PWM, IGBT output modes
■Notes on Timer A
(1) Write order to timer A
• In the timer and pulse output modes, write to the timer A register
(low-order) first and to the timer A register (high-order) next. Do not
write to only one side.
• In the IGBT and PWM modes, write to the registers as follows:
the compare register (high- and low-order)
the timer A register (low-order)
the timer A register (high-order).
It is possible to use whichever order to write to the compare register
(high- and low-order). However, write both the compare register and
the timer A register at the same time.
(4) Set of timer A mode register
Set the write control bit to “1” (write to the latch only) when setting the
IGBT and PWM modes.
Output waveform simultaneously reflects the contents of both registers at the next underflow after writing to the timer A register (highorder).
(5) Output control function of timer A
When using the output control function (INT1 and INT2 ) in the IGBT
mode, set the levels of INT1 and INT 2 to “H” in the falling edge active
or to “L” in the rising edge active before switching to the IGBT mode.
(2) Read order to timer A
• In all modes, read to the timer A register (high-order) first and to the
timer A register (low-order) next. Read order to the compare register is not specified.
• If reading to the timer A register during write operation or writing to
it during read operation, normal operation will not be performed.
(3) Write to timer A
• When writing a value to the timer A address to write to the latch
only, the value is set into the reload latch and the timer is updated
at the next underflow. Normally, when writing a value to the timer A
address, the value is set into the timer and the timer latch at the
same time, because they are written at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, an expected value may be set in the high-order counter.
• Do not switch the timer count source during timer count operation.
Stop the timer count before switching it. Additionally, when performing write to the latch and the timer at the same time, the timer count
value may change large.
23
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
The 38C3 group has a built-in 8-bit clock synchronous serial I/O. The
XIN
1/8
Internal
system clock
“1” selection bit
“0”
P47 latch
“0”
P47/SRDY
Divider
XCIN
I/O pins of serial I/O also operate as I/O port P4, and their function is
selected by the serial I/O control register 1 (address 001916).
Internal synchronous
clock selection bits
Data bus
1/16
1/32
1/64
1/128
1/256
Synchronous clock
“1”
selection bit
SCLK
SRDY Synchronous
“1”
circuit
SRDY output selection bit
“0”
External clock
P46 latch
“0”
P46/SCLK1
“1”
Serial I/O port selection bit
Serial I/O counter (3)
P45 latch
“0”
P45/SOUT
“1”
Serial I/O port selection bit
Serial I/O shift register (8)
P44/SIN
P40 latch
“0”
P40/SCLK2
“1”
Serial I/O port selection bit
Fig. 22 Block diagram of serial I/O
24
Serial I/O
interrupt request
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O Control Registers 1, 2 (SIOCON1,
SIOCON2)] 001916, 001A16
When internal clock is selected, serial I/O starts to transfer by a write
signal to the serial I/O register (address 001B16). After 8 bits have
been transferred, the SOUT pin goes to high impedance.
When external clock is selected, the clock must be controlled externally because the contents of the serial I/O register continue to shift
while the transfer clock is input. In this case, the SOUT pin does not
go to high impedance at the completion of data transfer.
The interrupt request bit is set at the end of the transfer of 8 bits,
regardless of whether the internal or external clock is selected.
Each of the serial I/O control registers 1, 2 contains 8 bits that select
various control parameters of serial I/O.
●Operation in serial I/O mode
Either an internal clock or an external clock can be selected as the
synchronous clock for serial I/O transfer. A dedicated divider is builtin as the internal clock, giving a choice of six clocks.
b7
b0
b7
b0
Serial I/O control register 1
(SIOCON1 : address 0019 16)
Internal synchronous clock selection bits
b2 b1 b0
0 0 0 : f(X IN)/8 or f(XCIN)/8
0 0 1 : f(X IN)/16 or f(X CIN)/16
0 1 0 : f(X IN)32 or f(X CIN)/32
0 1 1 : f(X IN)/64 or f(X CIN)/64
1 1 0 : f(X IN)/128 or f(X CIN)/128
1 1 1 : f(X IN)/256 or f(X CIN)/256
Serial I/O port selection bit (P4 0, P45, P46)
0 : I/O port
1 : SOUT, SCLK1, SCLK2 signal pin
SRDY output selection bit (P4 7)
0 : I/O port
1 : SRDY signal pin
Transfer direction selection bit
0 : LSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
1 : Internal clock
P-channel output disable bit (P4 0, P45, P46)
0 : CMOS output (in output mode)
1 : N-channel open-drain (in output mode)
Serial I/O control register 2
(SIOCON2: address 001A 16)
Synchronous clock output pin selection bit
0 : SCLK1
1 : SCLK2
Not used (returns “0” when read)
Fig. 23 Structure of serial I/O control register
Synchronous clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
SOUT
(Note)
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O input
SIN
Receive enable signal
SRDY
Note: When internal clock is selected, the SOUT pin goes to high impedance after
transfer ends.
Interrupt request bit set
Fig. 24 Serial I/O timing (for LSB first)
25
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The 38C3 group has a 10-bit A-D converter. The A-D converter performs successive approximation conversion.
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 500 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
[A-D Conversion Register (AD)] 003316, 003416
One of these registers is a high-order register, and the other is a loworder register. The high-order 8 bits of a conversion result is stored in
the A-D conversion register (high-order) (address 003416 ), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
A-D conversion register (low-order) (address 003316).
During A-D conversion, do not read these registers.
b7
b0
A-D control register
(ADCON: address 0032 16)
Analog input pin selection bits
000: P6 0/AN0
001: P61/AN1
010: P6 2/AN2
011: P6 3/AN3
100: P6 4/AN4
101: P6 5/AN5
110: P6 6/AN6
111: P6 7/AN7
[A-D Control Register (ADCON)] 003216
This register controls A-D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conversion.
A-D conversion is started by setting “0” in this bit.
Not used (returns “0” when read)
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and VREF , and outputs the divided voltages.
b7
b0
[Channel Selector]
A-D conversion register (high-order)
(ADH: address 0034 16)
The channel selector selects one of the input ports P67/AN7–P60/
AN0 and inputs it to the comparator.
AD conversion result stored bits
[Comparator and Control Circuit]
b7
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to “1.”
b0
A-D conversion register (low-order)
(ADL: address 0033 16)
Not used (returns “0” when read)
AD conversion result stored bits
Fig. 25 Structure of A-D control register
Data bus
b7
b0
A-D control register
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
Channel selector
3
A-D control circuit
Comparator
A-D interrupt request
A-D conversion register (H)
A-D conversion register (L)
(Address 0034 16)
Resistor ladder
AV SS VREF
Fig. 26 Block diagram of A-D converter
26
(Address 0033 16)
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD DRIVE CONTROL CIRCUIT
The 38C3 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
• LCD display RAM
• Segment output enable register
• LCD mode register
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
Up to 128 pixels can be controlled for a LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
b7
segment output enable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the
data on the LCD panel.
Table 7 Maximum number of display pixels at each duty ratio
Duty ratio
1
2
3
4
Maximum number of display pixels
32 dots
or 8 segment LCD 4 digits
64 dots
or 8 segment LCD 8 digits
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
b0
Segment output enable register
(SEG : address 0038 16)
Segment output enable bit 0
0 : I/O ports P2 0–P23
1 : Segment output SEG 0–SEG3
Segment output enable bit 1
0 : I/O ports P2 4–P27
1 : Segment output SEG 4–SEG7
Segment output enable bit 2
0 : I/O ports P0 0–P03
1 : Segment output SEG 8–SEG11
Segment output enable bit 3
0 : I/O ports P0 4–P07
1 : Segment output SEG 12–SEG15
Segment output enable bit 4
0 : I/O ports P1 0–P13
1 : Segment output SEG 16–SEG19
Segment output enable bit 5
0 : I/O ports P1 4–P17
1 : Segment output SEG 20–SEG23
Segment output enable bit 6
0 : Output ports P3 0–P33
1 : Segment output SEG 24–SEG27
Segment output enable bit 7
0 : Output ports P3 4–P37
1 : Segment output SEG 28–SEG31
b7
b0
LCD mode register
(LM : address 0039 16)
Duty ratio selection bits
0 0 : 1 (use COM 0)
0 1 : 2 (use COM 0,COM 1)
1 0 : 3 (use COM 0–COM 2)
1 1 : 4 (use COM 0–COM 3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit.)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN )/32
1 : f(XIN )/8192 (f(X CIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 27 Structure of LCD related registers
27
28
Segment Segment
driver
driver
P36 /SEG30 P37/SEG31
Segment Segment Segment Segment
driver
driver
driver
driver
P20/SEG0 P21 /SEG1 P22/SEG2 P23 /SEG3
P04 /SEG12
Selector Selector
Selector Selector Selector Selector
Fig. 28 Block diagram of LCD controller/driver
Bias control bit
VSS VL1 VL2 VL3
Bias control
LCD display RAM
Address 004F16
Address 004116
Address 0040 16
Data bus
Common
driver
Common
driver
Common
driver
COM0 COM1 COM2 COM3
Common
driver
2
Timing controller
2
LCD circuit
divider division
ratio selection bits
Duty ratio selection bits
LCD enable bit
LCDCK
LCDCK count source
selection bit
f(XIN )/8192
“1”
(f(XCIN )/8192 in low-speed mode)
LCD
divider
f(XCIN )/32
“0”
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bias Control and Applied Voltage to LCD Power
Input Pins
To the LCD power input pins (VL1–VL3), apply the voltage value shown
in Table 8 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Table 8 Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
1/1 bias
(1-duty ratio)
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by duty
ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
When selecting 1-duty ratio, 1/1 bias can be used.
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 V LCD
VL3=VLCD
VL2=VL1 =VSS
Note 1: VLCD is the maximum value of supplied voltage for the LCD panel.
Table 9 Duty ratio control and common pins used
Duty
ratio
1
2
3
4
Duty ratio selection bit
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Common pins used
COM 0 (Note 1)
COM 0, COM1 (Note 2)
COM 0–COM2 (Note 3)
COM 0–COM3
Notes 1:COM1, COM 2, and COM3 are open.
2:COM2 and COM3 are open.
3:COM3 is open.
Contrast control
Contrast control
VL3
Contrast control
VL3
R1
VL3
R4
VL2
VL2
VL2
R2
VL1
VL1
R6
R4 = R5
R1 = R2 = R3
1/3 bias
VL1
R5
R3
1/2 bias
1/1 bias
Fig. 29 Example of circuit at each bias
29
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Display RAM
LCD Drive Timing
Address 004016 to 004F16 is the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following
equation;
f(LCDCK)=
(frequency of count source for LCDCK)
(divider division ratio for LCD)
Frame frequency=
f(LCDCK)
duty ratio
Bit
7
4
3
2
1
SEG0
SEG2
004216
004316
004416
SEG5
SEG7
SEG9
SEG4
SEG6
SEG8
004516
004616
004716
004816
SEG11
SEG13
SEG10
SEG12
SEG15
SEG17
SEG19
SEG14
SEG16
SEG18
SEG21
SEG23
SEG25
SEG20
SEG22
SEG24
004C16
004D16
004E16
004F16
COM3
30
5
SEG1
SEG3
004916
004A16
004B16
Fig. 30 LCD display RAM map
6
Address
004016
004116
0
SEG27
SEG26
SEG29
SEG28
SEG31
SEG30
COM2 COM1 COM0 COM3 COM2 COM1 COM0
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal
signal
LCDCK
timing
1/4 duty
Voltage level
VL3
VL2=VL1
VSS
COM0
COM1
COM2
COM3
VL3
VSS
SEG0
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2=VL1
VSS
COM0
COM1
COM2
VL3
VSS
SEG0
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2=VL1
VSS
COM0
COM1
VL3
VSS
SEG0
ON
COM1
OFF
ON
OFF
ON
OFF
ON
OFF
COM0
COM1
COM0
COM1
COM0
COM1
COM0
1/1 duty (1/1 bias)
VL3
COM0
VL2=VL1=VSS
VL3
SEG0
VSS
OFF
ON
Fig. 31 LCD drive waveform (1/2 bias)
31
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal signal
LCDCK timing
1/4 duty
Voltage level
VL3
VL2
VL1
VSS
COM0
COM1
COM2
COM3
VL3
SEG0
VSS
OFF
COM3
ON
COM2
COM1
OFF
COM0
COM3
ON
COM2
COM1
COM0
1/3 duty
VL3
VL2
VL1
VSS
COM0
COM1
COM2
VL3
SEG0
VSS
ON
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
ON
COM1
OFF
COM0
COM2
1/2 duty
VL3
VL2
VL1
VSS
COM0
COM1
VL3
SEG0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM1
COM0
COM1
COM0
COM1
COM0
COM1
COM0
Fig. 32 LCD drive waveform (1/3 bias)
32
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
φ CLOCK OUTPUT FUNCTION
The internal system clock φ can be output from port P43 by setting
the φ output control register. Set “1” to bit 3 of the port P4 direction
register when outputting φ clock.
b7
b0
φ output control register
(CKOUT : address 002B 16)
φ output control bit
0 : Port function
1 : φ clock output
Not used (return “0” when read)
Fig. 33 Structure of φ output control register
33
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM CORRECTION FUNCTION
The 38C3 group has the ROM correction function correcting data at
the arbitrary addresses in the ROM area.
0F0216
ROM correct high-order address register 1
0F0316
ROM correct low-order address register 1
0F0416
ROM correct high-order address register 2
[ROM correct address register] 0F0216 – 0F1116
0F0516
ROM correct low-order address register 2
This is the register to store the address performing ROM correction.
There are two types of registers to correct up to 8 addresses: one is
the register to store the high-order address and the other is to store
the low-order address.
0F0616
ROM correct high-order address register 3
0F0716
ROM correct low-order address register 3
0F0816
ROM correct high-order address register 4
0F0916
ROM correct low-order address register 4
0F0A16
ROM correct high-order address register 5
0F0B16
ROM correct low-order address register 5
[ROM correct enable register (RC1)] 0F0116
This is the register to enable the ROM correction function. When setting the bit corresponding to the ROM correction address to “1”, the
ROM correction function is enabled.
It becomes invalid to the addresses of which corresponding bit is “0”.
All bits are “0” at the initial state.
[ROM correct data]
This is the register to store a correct data for the address specified by
the ROM correct address register.
■Notes on ROM correction function
1. To use the ROM correction function, transfer data to each ROM
correct data register in the initial setting.
2. Do not specify the same addresses in the ROM correct address
register.
0F0C16 ROM correct high-order address register 6
0F0D16 ROM correct low-order address register 6
0F0E16
ROM correct high-order address register 7
0F0F16
ROM correct low-order address register 7
0F1016
ROM correct high-order address register 8
0F1116
ROM correct low-order address register 8
Fig. 34 Structure of ROM correct address register
005016
ROM correct data 1
005116
ROM correct data 2
005216
ROM correct data 3
005316
ROM correct data 4
005416
ROM correct data 5
005516
ROM correct data 6
005616
ROM correct data 7
005716
ROM correct data 8
Fig. 35 Structure of ROM correct data
b7
b0
ROM correct enable register 1(address 0F01 16)
RC1
ROM correct address 1 enable bit
0 : Disabled
1 : Enabled
ROM correct address 2 enable bit
0 : Disabled
1 : Enabled
ROM correct address 3 enable bit
0 : Disabled
1 : Enabled
ROM correct address 4 enable bit
0 : Disabled
1 : Enabled
ROM correct address 5 enable bit
0 : Disabled
1 : Enabled
ROM correct address 6 enable bit
0 : Disabled
1 : Enabled
ROM correct address 7 enable bit
0 : Disabled
1 : Enabled
ROM correct address 8 enable bit
0 : Disabled
1 : Enabled
Fig. 36 Structure of ROM correct enable register 1
34
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
Poweron
To reset the microcomputer, RESET pin should be held at an “L” level
for 2 µs or more. Then the RESET pin is returned to an “H” level (the
power source voltage should be between 2.5 V and 5.5 V, and the
oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address
FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make
sure that the reset input voltage is less than 0.5 V for V CC of 2.5 V
(switching to the high-speed mode, a power source voltage must be
between 4.0 V and 5.5 V).
RESET
VCC
(Note)
Power source
voltage
0V
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; Vcc=2.5 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 37 Reset circuit example
XIN
φ
RESET
Internal
reset
Reset address from
vector table
Address
?
Data
?
?
?
FFFC
ADL
FFFD
ADH, ADL
ADH
SYNC
XIN : about 8000 cycles
Note 1: The frequency relation of f(X IN) and f(φ) is f(XIN) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 38 Reset sequence
35
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Address Register contents
(1) Port P0
000016
0016
(34) Timer A (high-order)
002D16
FF16
(2) Port P0 direction register
000116
0016
(35) Compare register (low-order)
002E16
0016
(3) Port P1
000216
0016
(36) Compare register (high-order)
002F16
0016
(4) Port P1 direction register
000316
0016
(37) Timer A mode register
003016
0016
(5) Port P2
000416
0016
(38) Timer A control register
003116
0016
(6) Port P2 direction register
000516
0016
(39) A-D control register
003216
1016
0016
(7) Port P3
000616
0016
(40) Segment output enable register
003816
(8) Port P4
000816
0016
(41) LCD mode register
003916
0016
(9) Port P4 direction register
000916
0016
(42) Interrupt edge selection register
003A16
0016
(10) Port P5
000A16
0016
(43) CPU mode register
003B16 0 1 0 0 1 0 0 0
(11) Port P5 direction register
000B16
0016
(44) Interrupt request register 1
003C16
0016
(12) Port P6
000C16
0016
(45) Interrupt request register 2
003D16
0016
(13) Port P6 direction register
000D16
0016
(46) Interrupt control register 1
003E16
0016
(14) Port P7
000E16
0016
(47) Interrupt control register 2
003F16
0016
(15) Port P7 direction register
000F16
0016
(48) ROM correct enable register 1
0F0116
0016
(16) Port P8
001016
0016
0F0216
FF16
(17) Port P8 direction register
001116
0016
0F0316
FF16
(18) PULL register A
001616
0F16
0F0416
FF16
(19) PULL register B
001716
0016
0F0516
FF16
(20) Port P8 output selection register 001816
0016
0F0616
FF16
(21) Serial I/O control register 1
001916
0016
0F0716
FF16
(22) Serial I/O control register 2
001A16
0016
0F0816
FF16
(23) Timer 1
002016
FF16
0F0916
FF16
(24) Timer 2
002116
0116
0F0A16
FF16
(25) Timer 3
002216
FF16
0F0B16
FF16
(26) Timer 4
002316
FF16
0F0C16
FF16
(27) Timer 5
002416
FF16
0F0D16
FF16
(28) Timer 6
002516
FF16
0F0E16
FF16
(29) Timer 12 mode register
002816
0016
0F0F16
FF16
(30) Timer 34 mode register
002916
0016
0F1016
FF16
(31) Timer 56 mode register
002A16
0016
0F1116
FF16
(32) φ output control register
002B16
0016
(49) ROM correct high-order address
register 1
(50) ROM correct low-order address
register 1
(51) ROM correct high-order address
register 2
(52) ROM correct low-order address
register 2
(53) ROM correct high-order address
register 3
(54) ROM correct low-order address
register 3
(55) ROM correct high-order address
register 4
(56) ROM correct low-order address
register 4
(57) ROM correct high-order address
register 5
(58) ROM correct low-order address
register 5
(59) ROM correct high-order address
register 6
(60) ROM correct low-order address
register 6
(61) ROM correct high-order address
register 7
(62) ROM correct low-order address
register 7
(63) ROM correct high-order address
register 8
(64) ROM correct low-order address
register 8
(65) Processor status register
(33) Timer A (low-order)
002C16
FF16
(66) Program counter
(PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
X: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
In the M version, bit 0 of the port P5 direction register becomes “1.”
Fig. 39 Internal status at reset
36
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 38C3 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No external resistor is needed between XIN and X OUT since a feedback resistor
exists on-chip. However, an external feedback resistor is needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and X COUT pins function as I/O ports.
Oscillation control
(1) Stop mode
Frequency control
(1) Middle-speed mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116.”
Either XIN divided by 16 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before executing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize.
The internal system clock is the frequency of XIN divided by 8. After
reset, this mode is selected.
(2) Wait mode
(2) High-speed mode
The internal system clock is the frequency of XIN divided by 2.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of XIN and X CIN are the same as the state
before executing the WIT instruction. The internal system clock restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after the
clock is restarted.
■Notes on clock generating circuit
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3f(XCIN).
XCIN
XCOUT
Rf
XIN
XOUT
Rd
CCOUT
CCIN
CIN
COUT
Fig. 40 Ceramic resonator circuit
XCIN
XIN
XCOUT
Rf
CCIN
Rd
XOUT
open
External oscillation circuit
CCOUT
VCC
VSS
Fig. 41 External clock input circuit
37
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
“1”
“0”
Port XC switch bit
XIN
XOUT
Timer 1 count
source selection
bit
Internal system clock selection bit
(Note)
Low-speed mode
“1”
1/2
“0”
Middle-/High-speed mode
Timer 2 count
source selection
bit
“1”
Timer 1
1/2
1/4
“0”
“0”
Timer 2
“1”
Main clock division ratio selection bit
Middle-speed mode
“1”
Timing φ
(Internal system clock)
“0”
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
S
R
STP instruction
WIT
instruction
Q
R
Reset
Interrupt disable flag I
Interrupt request
Note : When using the low-speed mode, set the port X C switch bit to “1” .
Fig. 42 Clock generating circuit block diagram
38
Q
S
R
STP instruction
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
High-speed mode
“0
“1”
CM4
4 “0”
CM
6
0”
”
M “
“1 C
”
“1
Middle-speed mode
((f(φ)=1 MHz)
(f(φ) =4 MHz)
CM7=0(8 MHz selected)
CM6=0(high-speed)
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
“0”
“1
”
” CM
4
CM
“1
6
”
“0
”
CM4
“0”
CM7=0(8 MHz selected)
CM6=1(middle-speed)
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
“0”
CM 6
“1”
“1”
Middle-speed mode
(f(φ)=1 MHz)
High-speed mode
CM 6
“1”
(f(φ) =4 MHz)
CM7=0(8 MHz selected)
CM6=0(high-speed)
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
“0”
“1”
“1”
CM 7
CM 7
“0”
“0”
CM7=0(8 MHz selected)
CM6=1(middle-speed)
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
Low-speed mode
CM
1”
6
“1
”
”
“0
“
“0”
” CM
5
CM
“1
6
”
“0
”
Low-speed mode
Low-speed mode
((f(φ)=16 kHz)
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=1(8 MHz stopped)
CM4=1(32 kHz oscillating)
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
“0
”
“0
C
M
5
CM 5
“0”
”
“1
“0”
CM 5
“1”
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
“1”
(f(φ) =16 kHz)
CM 6
“1”
Low-speed mode
((f(φ)=16 kHz)
(f(φ) =16 kHz)
CM 6
“1”
“0”
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=1(8 MHz stopped)
CM4=1(32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B 16)
CM4 : Port Xc switch bit
0: I/O port function
1: X CIN-XCOUT oscillating function
CM5 : Main clock (X IN- XOUT) stop bit
0: Oscillating
1: Stopped
CM6: Main clock division ratio selection bit
0: f(X IN)/2(High-speed mode)
1: f(X IN)/8 (Middle-speed mode)
CM7: Internal system clock selection bit
0: X IN–XOUT selected (Middle-/High-speed mode)
1: X CIN–XCOUT selected (Low-speed mode)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended.
3: Timer,LCD operate in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by connecting Timer 1 and Timer 2 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs in low-speed mode.
6: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high-speed mode.
7: The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal system clock.
Fig. 43 State transitions of system clock
39
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Instruction Execution Time
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
• The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register
as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
• Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
• Using an internal clock
When using an internal clock, set the synchronous clock to the internal clock, then clear the serial I/O interrupt request bit before
executing a serial I/O transfer and serial I/O automatic transfer.
40
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to execute an instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
The frequency of the internal system clock is the same half of the XIN
frequency in high-speed mode.
At STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register
are cleared.
NOTES ON USE
Notes on Built-in EPROM Version
The P51 pin of the One Time PROM version or the EPROM version
functions as the power source input pin of the internal EPROM.
Therefore, this pin is set at low input impedance, thereby being affected easily by noise.
To prevent a malfunction due to noise, insert a resistor (approx. 5 kΩ)
in series with the P51 pin.
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM production:
1. Mask ROM Order Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies)
The built-in PROM of the blank One Time PROM version and built-in
EPROM version can be read or programmed with a general-purpose
PROM programmer using a special programming adapter.
DATA REQUIRED FOR ROM WRITING ORDERS
The following are necessary when ordering a ROM writing:
1. ROM Writing Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies)
Table 10 Programming adapter
Package
80P6N-A
80D0
Name of Programming Adapter
PCA4738F-80A
PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 44 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 44 Programming and testing of One Time PROM version
41
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 11 Absolute maximum ratings
Symbol
VCC
VI
VI
VI
VI
VI
Parameter
Power source voltage
Input voltage P00–P0 7, P1 0–P17, P2 0–P27,
P40–P4 7, P5 0–P57, P60–P67 , P70,
P71, P8 0–P8 7
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage RESET, X IN
VO
Output voltage P00–P0 7, P1 0–P17, P2 0–P27,
P30–P3 7
VO
VO
Output voltage COM0–COM3
Output voltage P40–P4 7, P5 0, P52–P5 7, P60 –P67,
P70, P7 1, P8 0–P87
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
VO
Pd
Topr
Tstg
Conditions
All voltages are based on
Vss. Output transistors
are cut off.
At output port
At segment output
Ta = 25°C
Ratings
–0.3 to 7.0
–0.3 to VCC+0.3
Unit
V
V
–0.3 to V L2
VL1 to VL3
VL2 to V CC+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VL3+0.3
–0.3 to VCC+0.3
V
V
V
V
V
V
V
V
–0.3 to V CC+0.3
300
–20 to 85
–40 to 125
V
mW
°C
°C
Table 12 Recommended operating conditions (Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
VCC
Power source voltage
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Power source voltage
A-D converter reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage
P00–P0 7, P10–P1 7, P20 –P27
“H” input voltage
P40–P4 7, P50–P5 7, P60–P6 7, P70, P71 (CM4 = 0)
“H” input voltage
P8 0–P8 7
“H” input voltage
RESET
“H” input voltage
XIN
“L” input voltage
P00–P0 7, P10–P1 7, P20 –P27
“L” input voltage
P40–P4 7, P50–P5 7, P60 –P67, P7 0, P71 (CM4 = 0)
“L” input voltage
P80–P8 7
“L” input voltage
RESET
“L” input voltage
XIN
42
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
Limits
Min.
4.0
2.5
2.5
Typ.
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
VCC
2.0
0
AVSS
0.7VCC
0.8VCC
0.4VCC
0.8VCC
0.8VCC
0
0
0
0
0
VCC
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.2VCC
0.16VCC
0.2VCC
0.2VCC
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 13 Recommended operating conditions (Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
I OH(peak)
I OH(peak)
I OL(peak)
I OL(peak)
I OL(peak)
I OH(avg)
I OH(avg)
I OL(avg)
I OL(avg)
I OL(avg)
Parameter
“H” total peak output current (Note 1)
P00–P0 7, P10–P1 7, P20 –P27, P3 0–P37
P80–P8 7, P50
“H” total peak output current (Note 1)
P40–P4 7, P52–P5 7, P60 –P67, P7 0, P71
“L” total peak output current (Note 1)
P00–P0 7, P10–P1 7, P20 –P27, P3 0–P37
“L” total peak output current (Note 1)
P80–P8 7, P50
“L” total peak output current (Note 1)
P40–P4 7, P52–P5 7, P60 –P67, P7 0, P71
“H” total average output current (Note 1)
P00–P0 7, P10–P1 7, P20 –P27, P3 0–P37
P80–P8 7, P50
“H” total average output current (Note 1)
P40–P4 7, P52–P5 7, P60 –P67, P7 0, P71
“L” total average output current (Note 1)
P00–P0 7, P10–P1 7, P20 –P27, P3 0–P37
“L” total average output current (Note 1)
P80–P8 7, P50
“L” total average output current (Note 1)
P40–P4 7, P52–P5 7, P60 –P67, P7 0, P71
“H” peak output current (Note 2)
P00–P0 7, P10–P1 7, P20 –P27, P3 0–P37
“H” peak output current (Note 2)
P40–P4 7, P50, P5 2–P57 , P60–P6 7, P70, P7 1
P80–P8 7
“L” peak output current (Note 2)
P00–P0 7, P10–P1 7, P20 –P27, P3 0–P37
“L” peak output current (Note 2)
P40–P4 7, P52–P5 7, P60 –P67, P7 0, P71
“L” peak output current (Note 2)
P80–P8 7, P50
“H” average output current (Note 3)
P00–P0 7, P10–P1 7, P20 –P27, P3 0–P37
“H” average output current (Note 3)
P40–P4 7, P50, P5 2–P57 , P60–P6 7, P70, P7 1
P80–P8 7
“L” average output current (Note 3)
P00–P0 7, P10–P1 7, P20 –P27, P3 0–P37
“L” average output current (Note 3)
P40–P4 7, P52–P5 7, P60 –P67, P7 0, P71
“L” average output current (Note 3)
P80–P8 7, P50
Min.
Limits
Typ.
Max.
–60
Unit
mA
–30
mA
40
mA
80
mA
40
mA
–30
mA
–15
mA
20
mA
40
mA
20
mA
–2.0
mA
–10
mA
5.0
mA
10
mA
30
mA
–2.0
mA
–5.0
mA
2.5
mA
5.0
mA
15
mA
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over
100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
43
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Recommended operating conditions (Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
f(CNTR 0)
Input frequency (duty cycle 50%)
f(CNTR 1)
f(X IN)
Main clock input oscillation frequency (Note 4)
f(X CIN)
Sub-clock input oscillation frequency (Notes 4, 5)
Min.
Limits
Typ.
(4.0 V ≤ VCC ≤ 5.5 V)
(VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
High-speed mode
(VCC ≤ 4.0 V)
Middle-speed mode
32.768
Max.
4.0
(2✕VCC)–4
8.0
MHz
MHz
MHz
(4✕VCC)–8
MHz
8.0
50
MHz
kHz
Notes 4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(X IN)/3.
44
Unit
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 15 Electrical characteristics (Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VOH
VOH
VOL
VOL
VOL
VT+–VTVT+–VTVT+–VTI IH
I IH
I IH
I IH
I IL
I IL
I IL
I IL
Parameter
“H” output voltage
P00–P07, P1 0–P1 7, P20–P2 7,
P30–P37
“H” output voltage
P40–P47, P5 0, P52 –P57,
P60–P67, P7 0, P7 1,
P80–P87
“L” output voltage
P00–P07, P1 0–P1 7, P20–P2 7,
P30–P37
“L” output voltage
P40–P47, P5 2–P57, P60–P6 7,
P70, P71
“L” output voltage P8 0–P87, P50
Hysteresis
INT0–INT2, CNTR0, CNTR 1, P80–P8 7
Hysteresis SCLK1, SIN
Hysteresis RESET
“H” input current
P00–P07, P1 0–P1 7, P20–P2 7
“H” input current
P40–P47, P5 0–P5 7, P60–P6 7,
P70, P71, P8 0–P8 7
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07, P1 0–P1 7, P20–P2 7, P51
“L” input current
P40–P47, P5 0, P52 –P57,
P60–P67, P7 0, P7 1, P80–P8 7
“L” input current RESET
“L” input current XIN
Test conditions
(Note)
(Note)
I OH = –2.0 mA
I OH = –0.6 mA
VCC = 2.5 V
I OH = –5 mA
I OH = –1.25 mA
I OH = –1.25 mA
VCC = 2.5 V
I OL = 2.5 mA
I OL = 1.25 mA
I OL = 1.25 mA
VCC = 2.5 V
I OL = 5.0 mA
I OL = 2.5 mA
I OL = 2.5 mA
VCC = 2.5 V
I OL = 15 mA
RESET:
VCC = 2.5 V – 5.5 V
VI = V CC
Pull-down “off”
VCC = 5.0 V, VI = VCC
Pull-down “on”
VCC = 3.0 V, VI = VCC
Pull-down “on”
VI = V CC
Min.
VCC–2.0
VCC–1.0
Max.
Unit
V
V
VCC–2.0
VCC–0.5
VCC–1.0
V
V
V
2.0
0.5
1.0
V
V
V
2.0
0.5
1.0
V
V
V
2.0
0.5
V
V
0.5
0.5
V
V
5.0
µA
30
70
140
µA
6.0
25
45
µA
5.0
µA
5.0
–5.0
µA
µA
µA
–5.0
µA
VI = V CC
VI = V CC
VI = V SS
Pull-up “off”
VCC = 5.0 V, VI = VSS
Pull-up “on”
VCC = 3.0 V, VI = VSS
Pull-up “on”
VI = V SS
VI = V SS
Limits
Typ.
4.0
–30
–70
–140
µA
–6
–25
–45
µA
–5
µA
µA
–4
Note: When “1” is set to the port XC switch bit (bit 4 of address 003B 16) of the CPU mode register, the drive ability of Port P7 0 is different from the value above
mentioned.
45
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16 Electrical characteristics (Vcc = 2.5 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VRAM
I CC
46
Parameter
RAM hold voltage
Power source current
Test conditions
When clock is stopped
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter in operating
High-speed mode, Vcc = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”,
A-D converter stopped
Low-speed mode, VCC = 3 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode, VCC = 3 V,
Ta = 25 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
(in WIT state)
Output transistors “off”
All oscillation stopped
Ta = 25 °C
(in STP state)
Output transistors “off”
Ta = 85 °C
Min.
2.0
Limits
Typ.
Unit
6.4
Max.
5.5
13
1.6
3.2
mA
15
22
µA
4.5
9.0
µA
0.1
1.0
µA
10
µA
V
mA
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 17 A-D converter characteristics
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle-speed/high-speed mode)
Symbol
Parameter
—
—
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Reference input current
Analog port input current
Ladder resistor
Tconv
IVREF
I IA
RLADDER
Test conditions
Min.
VCC = V REF = 5.12 V
VREF = 5 V
Limits
Typ.
±1
61
50
150
0.5
35
Max.
10
±2.5
62
200
5.0
Unit
Bits
LSB
tc(φ)
µA
µA
kΩ
47
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18 Timing requirements 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
t w(RESET)
t c(XIN)
t wH(XIN)
t wL(XIN)
t c(CNTR)
t wH(CNTR)
t wL(CNTR)
t wH(INT)
t wL(INT)
t c(SCLK)
t wH(SCLK)
t wL(SCLK)
t su(SIN-SCLK)
t h(SCLK-SIN)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0 , CNTR1 input cycle time
CNTR0, CNTR 1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
Limits
Typ.
Min.
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 19 Timing requirements 2 (Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
t w(RESET)
t c(XIN)
t wH(XIN)
t wL(XIN)
t c(CNTR)
t wH(CNTR)
t wL(CNTR)
t wH(INT)
t wL(INT)
t c(SCLK)
t wH(SCLK)
t wL(SCLK)
t su(SIN-SCLK)
t h(SCLK-SIN)
48
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0 , CNTR1 input cycle time
CNTR0, CNTR 1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
Limits
Min.
2
125
45
40
500/(V CC–2)
250/(VCC –2)–20
250/(VCC –2)–20
230
230
2000
950
950
400
200
Typ.
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 20 Switching characteristics 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
t wH(SCLK)
t wL(SCLK)
t d(SCLK-SOUT)
t V(SCLK-SOUT)
t r(SCLK)
t f(SCLK)
t r(CMOS)
t f(CMOS)
Limits
Parameter
Min.
t c(SCLK)/2–30
t c(SCLK)/2–30
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
CMOS output falling time
(Note 1)
(Note 1)
Typ.
Max.
140
–30
(Note 2)
(Note 2)
30
30
30
30
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P-channel output disable bit (bit 7 of address 001916 ) is “0.”
2: The XOUT , XCOUT pins are excluded.
Table 21 Switching characteristics 2 (Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
t wH(SCLK)
t wL(SCLK)
t d(SCLK-SOUT)
t V(SCLK-SOUT)
t r(SCLK)
t f(SCLK)
t r(CMOS)
t f(CMOS)
Limits
Parameter
Min.
t C(SCLK)/2–50
t C(SCLK)/2–50
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output valid time
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time
CMOS output falling time
(Note 1)
(Note 1)
Typ.
Max.
350
–30
(Note 2)
(Note 2)
20
20
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P-channel output disable bit (bit 7 of address 0019 16 ) is “0.”
2: The XOUT , XCOUT pins are excluded.
1 kΩ
Measurement output pin
Measurement output pin
100 pF
CMOS output
100 pF
N-channel open-drain output
Note: When bit 7 of the serial I/O control register 1 (address 0019 16) is “ 1.”
(N-channel open-drain output mode)
Fig. 45 Circuit for measuring output switching characteristics
49
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0,CNTR1
0.8VCC
0.2VCC
twL(INT)
twH (INT)
INT0 – INT3
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(SCLK)
tf
SCLK
tWL(SCLK)
td(SCLK-SOUT)
50
th(SCLK-SIN)
0.8VCC
0.2VCC
SIN
Fig. 46 Timing diagram
tWH(SCLK)
0.8VCC
0.2VCC
tsu(SIN-SCLK)
SOUT
tr
tv(SCLK-SOUT)
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-95B<85A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38C34M6AXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
000F16
001016
Product name
ASCII code :
‘M38C34M6A’
27512
EPROM address
000016
000F16
001016
A07F16
A08016
207F 16
208016
Data
ROM 24K-130 bytes
Data
ROM 24K-130 bytes
7FFD 16
7FFE16
7FFF 16
Product name
ASCII code :
‘M38C34M6A’
In the address space of the microcomputer,
the internal ROM area is from address A08016
to FFFD 16 . The reset vector is stored in
addresses FFFC16 and FFFD16 .
FFFD 16
FFFE 16
FFFF 16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38C34M6A” must
be entered in addresses 000016 to 000816 . And set data
“FF16” in addresses 0009 16 to 000F 16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 33 16
‘8’ = 38 16
‘C’ = 43 16
‘3’ = 33 16
‘4’ = 34 16
‘M’ = 4D16
‘6’ = 36 16
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ A ’ =4116
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
51
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-95B<85A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6AXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*=∆$8000
.BYTE∆‘M38C34M6A’
*=∆$0000
.BYTE∆‘M38C34M6A’
Note : If the name of the product written to the EPROMs does not match the name of the mask ROM confirmation form, the ROM
will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
At what frequency?
Other (
)
f(XIN) =
MHz
(2) Which function will you use the P70/XCIN and P70/XCOUT pins?
Port P70 and P71 function
XCIN-XCOUT function (external resonator)
❈ 4. Comments
(2/2)
52
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-96B<85A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38C34M6MXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
EPROM address
000016
000F16
001016
Product name
ASCII code :
‘M38C34M6M’
27512
EPROM address
000016
000F16
001016
A07F16
A08016
207F 16
208016
Data
ROM 24K-130 bytes
Data
ROM 24K-130 bytes
7FFD16
7FFE16
7FFF16
Product name
ASCII code :
‘M38C34M6M’
In the address space of the microcomputer,
the internal ROM area is from address A08016
to FFFD 16 . The reset vector is stored in
addresses FFFC16 and FFFD16.
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38C34M6M” must
be entered in addresses 0000 16 to 0008 16. And set data
“FF16 ” in addresses 000916 to 000F16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘4’ = 3416
‘M’ = 4D16
‘6’ = 3616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ M ’ =4D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
53
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-96B<85A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C34M6MXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27256
27512
The pseudo-command
*=∆$8000
.BYTE∆‘M38C34M6M’
*=∆$0000
.BYTE∆‘M38C34M6M’
Note : If the name of the product written to the EPROMs does not match the name of the mask ROM confirmation form, the ROM
will
not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
At what frequency?
Other (
)
f(XIN) =
MHz
(2) Which function will you use the P70/XCIN and P70/XCOUT pins?
Port P70 and P71 function
XCIN-XCOUT function (external resonator)
❈ 4. Comments
(2/2)
54
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-97B<85A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38C37ECAXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM programming data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
EPROM address
000016
000F16
001016
Product name
ASCII code :
‘M38C37ECA’
In the address space of the microcomputer,
the internal ROM area is from address 408016
to FFFD 16 . The reset vector is stored in
addresses FFFC16 and FFFD16.
407F 16
408016
Data
ROM 48K-132 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38C37ECA” must
be entered in addresses 0000 16 to 0008 16. And set data
“FF16 ” in addresses 000916 to 000F16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘7’ = 3716
‘E’ = 4516
‘C’ = 4316
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ A ’ =4116
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
55
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-97B<85A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C37ECAXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
The pseudo-command
*=∆$0000
.BYTE∆‘M38C37ECA’
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N) and attach it to the ROM programming confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
At what frequency?
Other (
)
f(XIN) =
MHz
(2) Which function will you use the P70/XCIN and P70/XCOUT pins?
Port P70 and P71 function
XCIN-XCOUT function (external resonator)
❈ 4. Comments
(2/2)
56
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-98B<85A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
Receipt
SINGLE-CHIP MICROCOMPUTER M38C37ECMXXXFP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
❈ Customer
TEL
(
Company
name
Date
issued
Date:
)
Issuance
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM programming data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
EPROM address
000016
000F16
001016
Product name
ASCII code :
‘M38C37ECM’
In the address space of the microcomputer,
the internal ROM area is from address 408016
to FFFD 16 . The reset vector is stored in
addresses FFFC16 and FFFD16.
407F 16
408016
Data
ROM 48K-132 bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38C37ECM” must
be entered in addresses 0000 16 to 0008 16. And set data
“FF16 ” in addresses 000916 to 000F16. The ASCII codes
and addresses are listed to the right in hesadecimal
notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘C’ = 4316
‘3’ = 3316
‘7’ = 3716
‘E’ = 4516
‘C’ = 4316
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ M ’ =4D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
57
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH52-98B<85A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38C37ECMXXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembier source program because
ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
The pseudo-command
*=∆$0000
.BYTE∆‘M38C37ECM’
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark
specification form (80P6N) and attach it to the ROM programming confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
At what frequency?
Other (
)
f(XIN) =
MHz
(2) Which function will you use the P70/XCIN and P70/XCOUT pins?
Port P70 and P71 function
XCIN-XCOUT function (external resonator)
❈ 4. Comments
(2/2)
58
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6N (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
64
41
40
65
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
25
80
1
24
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
64
41
40
65
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
25
80
1
24
C. Special Mark Required
64
41
65
40
80
25
1
24
Notes1 : If special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be
duplicated technically as close as possible.
Mitsubishi product number (6-digit, or 7-digit) and Mask
ROM number (3-digit) are always marked for sorting the
products.
2 : If special character fonts (e,g., customer’s trade mark
logo) must be used in Special Mark, check the box below.
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
Special character fonts required
59
MITSUBISHI MICROCOMPUTERS
38C3 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6N-A
Plastic 80pin 14✕20mm body QFP
EIAJ Package Code
QFP80-P-1420-0.80
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
HD
D
b2
1
ME
65
80
64
I2
E
24
HE
Recommended Mount Pad
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
41
A
40
25
c
A2
L1
b
F
A1
e
L
b2
I2
MD
ME
Detail F
y
80D0
Dimension in Millimeters
Min
Nom
Max
–
–
3.05
0.1
0.2
0
2.8
–
–
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.8
–
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
0.1
–
–
0°
10°
–
0.5
–
–
–
–
1.3
–
–
14.6
–
–
20.6
Glass seal 80pin QFN
EIAJ Package Code
–
JEDEC Code
–
21.0±0.2
Weight(g)
18.4±0.15
3.32MAX
0.8TYP
1.78TYP
0.6TYP
64
41
65
INDEX
60
0.5TYP
0.8TYP
12.0±0.15
1.2TYP
15.6±0.2
0.8TYP
40
25
80
24
1.2TYP
1
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
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Notes regarding these materials
•
•
•
•
•
•
© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Jun. 1998.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
38C3 GROUP DATA SHEET
Revision Description
First Edition
Rev.
date
980602
(1/1)
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