LINER LT3743 High current synchronous step-down led driver with three-state control Datasheet

LT3743
High Current Synchronous
Step-Down LED Driver with
Three-State Control
DESCRIPTION
FEATURES
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PWM Dimming Provides Up to 3000:1 Dimming Ratio
CTRL_SEL Dimming Provides Up to 3000:1 Dimming
Ratio Between Any Current
Three-State Current Control for Color Mixing
±6% Current Regulation Accuracy
6V to 36V Input Voltage Range
Average Current Mode Control
2µs Maximum Recovery Time Between Any Current
Regulation State
<1µA Shutdown Current
Output Voltage Regulation and Open-LED Protection
Thermally Enhanced 4mm × 5mm QFN and
28-Pin FE Package
The LT®3743 is a fixed frequency synchronous step-down
DC/DC controller designed to drive high current LEDs. The
average current mode controller will maintain inductor
current regulation over a wide output voltage range of 0V
to (VIN – 2V). LED dimming is achieved through analog
dimming on the CTRL_L, CTRL_H and CTRL_T pins and
with PWM dimming on the PWM and CTRL_SEL pins.
Through the use of externally switched load capacitors,
the LT3743 is capable of changing regulated LED current
levels within several µs, providing accurate, high speed
PWM dimming between two current levels. The switching
frequency is programmable from 200kHz to 1MHz through
an external resistor on the RT pin.
APPLICATIONS
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Additional features include voltage regulation and
overvoltage protection set with a voltage divider from the
output to the FB pin. Overcurrent protection is provided
and set by the CTRL_H pin.
DLP Projectors
High Power Architectural Lighting
Laser Diodes
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
True Color PWM is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 7199560, 7321203,
8120335 and others pending.
TYPICAL APPLICATION
92% Efficient 20A LED Driver
EN/UVLO
PWM
CTRL_SEL
82.5k
VIN
EN/UVLO
PWM
CTRL_SEL
RT
SYNC
VREF LT3743
RHOT
499Ω
100k
CTRL_L
220nF
1.1µH
SW
2.5mΩ
22µF
LG
M2
RNTC
10k
10nF
M3
SENSE+
SENSE–
PWMGH
SS
PWM
5V/DIV
330µF
×3
GND
CTRL_T
CTRL_SEL
5V/DIV
OUTPUT
20A MAXIMUM
4.7µF
VCC_INT
CTRL_H
100k
VIN
10V TO 30V
M1
HG
CBOOT
2.2nF
4.7µF
×4
1µF
SW
20V/DIV
330µF
×3
ILED
10A/DIV
M4
PWMGL
51.1k
FB
VCL
VCH
34k
8.2nF
330µF
×3
3743 TA01a
34k
8.2nF
VIN = 24V
20µs/DIV
0A TO 2A TO 20A LED CURRENT STEP
3743 TA01b
10.0k
M1, M2: SiR462DP
M3, M4: Si7234DP
3743fd
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LT3743
ABSOLUTE MAXIMUM RATINGS (Note 1)
VIN Voltage.................................................................40V
EN/UVLO Voltage.........................................................6V
VREF Voltage................................................................3V
CTRL_L, CTRL_H, CTRL_T Voltage.............................3V
PWM, CTRL_SEL Voltage............................................6V
SENSE+ Voltage.........................................................40V
SENSE– Voltage.........................................................40V
VCH, VCL Voltage..........................................................3V
SW Voltage................................................................40V
CBOOT.......................................................................46V
RT Voltage...................................................................3V
FB Voltage....................................................................3V
SS Voltage...................................................................6V
SYNC Voltage...............................................................6V
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
TSSOP............................................................... 300°C
PIN CONFIGURATION
TOP VIEW
HG
SW
CBOOT
LG
VCC_INT
VIN
TOP VIEW
28 27 26 25 24 23
22 PWMGL
GND 1
VCC_INT
1
28 LG
GND
2
27 GND
VIN
3
26 CBOOT
EN/UVLO
4
25 SW
EN/UVLO 2
21 GND
VREF
5
24 HG
VREF 3
20 GND
CTRL_T
6
23 PWMGL
GND
7
18 PWM
CTRL_H
8
CTRL_H 6
17 CTRL_SEL
CTRL_L
9
CTRL_L 7
16 SYNC
CTRL_T 4
19 PWMGH
29
GND
GND 5
SS 8
SS 10
15 RT
GND 11
FB 12
VCH
VCL
SENSE–
SENSE+
FB
GND
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
29
GND
22 GND
21 PWMGH
20 PWM
19 CTRL_SEL
18 SYNC
17 RT
SENSE+
13
16 VCH
SENSE–
14
15 VCL
FE PACKAGE
28-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 30°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
(Note 2)
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3743EUFD#PBF
LT3743EUFD#TRPBF
3743
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3743IUFD#PBF
LT3743IUFD#TRPBF
3743
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3743EFE#PBF
LT3743EFE#TRPBF
LT3743FE
28-Lead Plastic TSSOP
–40°C to 125°C
LT3743IFE#PBF
LT3743IFE#TRPBF
LT3743FE
28-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3743fd
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LT3743
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, VSYNC = 0V, VCTRL_SEL = 0V, VPWM = 2V,
unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Input Voltage Range
VIN Pin Quiescent Current (Note 3)
Non-Switching Operation
Shutdown Mode
TYP
6
VPWM = VCTRL_SEL = 0V, Not Switching, RT = 40k
VEN/UVLO = 0V
l
EN/UVLO Pin Falling Threshold
1.49
EN/UVLO Hysteresis
UNITS
36
V
1.8
0.1
2.5
1
mA
µA
1.55
1.61
V
130
mV
5.5
µA
PWM Pin Threshold
1.0
V
CTRL_SEL Threshold
1.0
V
SYNC Pin Threshold
1.0
V
EN/UVLO Pin Current
VIN = 6V, EN/UVLO = 1.45V
MAX
CTRL_H and CTRL_L Pin Control Range
0
CTRL_H and CTRL_L Pin Current
1.5
100
V
nA
Reference
Reference Voltage (VREF Pin)
l
1.96
2
2.04
l
48
51
54
V
Inductor Current Sensing
Full Range SENSE+ to SENSE–
VCTRL_H = 1.5V, VSENSE– = 6V
mV
SENSE+ Pin Current
VSENSE
– = 6V
50
nA
SENSE– Pin Current
VSENSE+ = VSENSE– = 6V
10
µA
+=V
SENSE
Internal VCC Regulator (VCC_INT Pin)
Regulation Voltage
l
4.7
5
5.2
V
NMOS FET Driver (Note 2)
Non-Overlap time HG to LG
100
ns
Non-Overlap time LG to HG
60
ns
50
ns
Minimum On-Time LG
(Note 3)
Minimum On-Time HG
(Note 3)
80
ns
Minimum Off-Time LG
(Note 3)
60
ns
High Side Driver Switch On-Resistance
Gate Pull Up
Gate Pull Down
VCBOOT – VSW = 5V
2.3
1.3
Ω
Ω
Low Side Driver Switch On-Resistance
Gate Pull Up
Gate Pull Down
VCC_INT = 5V
2.5
1.3
Ω
Ω
Switching Frequency
fSW
RT = 40kΩ
RT = 200kΩ
l
900
190
1000
200
1070
233
kHz
kHz
Soft-Start
Charging Current
5.5
µA
Voltage Regulation Amplifier
Input Bias Current
1
Feedback Regulation Voltage
nA
200
gm
VCTRL_H = 0V, VCTRL_L = 2V, VSENSE+ = 2V
l
0.945
1
µA/V
1.025
V
3743fd
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LT3743
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PWMG Control Signals
CTRL_SEL High to PWMGL Low Delay
10
40
ns
CTRL_SEL High to PWMGH High Delay
150
200
ns
CTRL_SEL Low to PWMGH Low Delay
30
60
ns
220
ns
CTRL_SEL Low to PWMGL High Delay
170
PWMGH and PWMGL Pull-up Impedance
3.2
Ω
PWMGH and PWMGL Pull-Down Impedance
1.75
Ω
Current Control Loop gm Amp
Offset Voltage
VSENSE+ = 4V, VSENSE– = 4V
Input Common Mode Range
VCM(LOW)
VCM(HIGH)
VCM(HIGH) Measured from VIN to VCM
l
–3
Differential Gain
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3743E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
3
0
2
Output Impedance
gm
0
V
V
3.5
375
475
1.7
mV
MΩ
625
µA/V
V/mV
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3743I is guaranteed to meet performance specifications over the –40°C
to 125°C operating junction temperature range.
Note 3: The minimum on and off times are guaranteed by design and are
not tested.
3743fd
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LT3743
TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Pin Current
0.5
1.64
8
0.4
6
0.3
1.58
–50°C
1.52
130°C
1.46
1.40
6
12
18
24
VIN (V)
30
IQ (µA)
10
EN/UVLO PIN CURRENT (µA)
EN/UVLO THRESHOLD (V)
EN/UVLO Threshold (Falling)
1.70
4
2
0
36
12
18
24
VIN (V)
30
3743 G01
2.01
0
6
12
18
24
VIN (V)
30
8
16
24
VIN (V)
32
VREF Current Limit
1.4
2.00
VIN = 36V
1.99
VIN = 6V
TA = 25°C
TA = 130°C
1.2
TA = –50°C
1.0
1.97
–50
36
–15
55
20
TEMPERATURE (°C)
90
3743 G04
0.8
125
6
12
18
24
VIN (V)
30
3743 G05
Oscillator Frequency
36
3743 G06
RT Pin Current Limit
Soft-Start Pin Current
90
1.5
40
1.6
1.98
TA = 25°C
TA = 130°C
TA = –50°C
0
3743 G03
ILIMIT (mA)
1.6
0.4
36
VREF Pin Voltage
2.02
VREF VOLTAGE (V)
QUIESCENT CURRENT (mA)
Quiescent Current (Non-Switching)
0.8
25°C
0
3743 G02
2.0
1.2
130°C
0.2
0.1
25°C
130°C
–50°C
6
IQ in Shutdown
7
1.2MHz
80
0.9
0.6
0.3
0
–50
55
20
TEMPERATURE (°C)
VIN = 36V
70
60
90
125
3743 G07
40
–50
5
VIN = 6V
4
50
220kHz
–15
6
ISS (µA)
900kHz
ILIMIT (µA)
FREQUENCY (MHz)
1.2
–15
55
20
TEMPERATURE (°C)
90
125
3743 G08
3
–50
–15
55
20
TEMPERATURE (°C)
90
125
3743 G09
3743fd
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LT3743
TYPICAL PERFORMANCE CHARACTERISTICS
Internal UVLO
VCC_INT UVLO
CBOOT-SW UVLO Voltage
5.0
3.00
4.00
2.75
3.75
2.50
3.50
4.0
UVLO (V)
VOLTAGE (V)
VIN (V)
4.5
2.25
3.25
2.00
3.00
1.75
2.75
3.5
3.0
–50
–15
55
20
TEMPERATURE (°C)
90
1.50
–50
125
–15
20
55
TEMPERATURE (°C)
90
VCC_INT Load Reg at 12V
OPEN-LED THRESHOLD (V)
REGULATED CURRENT (%)
VCC_INT (V)
4.4
50
0
–50
–100
0
10
20
30
40
ILOAD (mA)
50
60
–150
800
900
1000
1100
VFB (mV)
1200
3743 G13
Open-LED Timeout
13
11
125
40
30
20
90
0
125
VIN = 6V
1.5
VIN = 36V
1.0
0.5
0
0.5
1.0
1.5
2.0
VCTRL (V)
3743 G16
55
20
TEMPERATURE (°C)
MEASURED VIN – VOUT
2.0
10
90
–15
Common Mode Lockout
2.5
CM LOCKOUT (V)
VSENSE+ – VSENSE– (mV)
OPEN-LED TIMEOUT (µs)
1.1
Regulated Sense Voltage
15
55
20
TEMPERATURE (°C)
1.2
3743 G15
50
–15
1.3
1.0
–50
1300
60
17
9
–50
1.4
3743 G14
19
125
Open-LED Threshold
100
4.8
90
1.5
150
5.2
20
55
TEMPERATURE (°C)
3743 G12
Regulated Current vs VFB
6.0
5.6
–15
3743 G11
3743 G10
4.0
2.50
–50
125
3743 G17
0
–50
–15
55
20
TEMPERATURE (°C)
90
125
3743 G18
3743fd
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LT3743
TYPICAL PERFORMANCE CHARACTERISTICS
4
4
PMOS
3
2
NMOS
HG Driver RDS(ON)
5
3
PMOS
2
1
–15
55
20
TEMPERATURE (°C)
90
0
–50
125
–15
55
20
TEMPERATURE (°C)
90
120
PWMGH TO PWMGL
110
–15
55
20
TEMPERATURE (°C)
90
LG TO HG
60
30
90
HG
60
LG
30
–15
55
20
TEMPERATURE (°C)
90
0
–50
125
–15
55
20
TEMPERATURE (°C)
90
3743 G23
3
125
120
HG TO LG
0
–50
125
300
125
3743 G24
Regulation Accuracy
CTRL_H = 1.5V, VIN = 12V
6
2
4
1
2
Regulation Accuracy
CTRL_H = 0.75V, VIN = 12V
180
120
HG
60
ACCURACY (%)
LG
ACCURACY (%)
MINIMUM OFF-TIME (ns)
90
Minimum On-Time
90
Minimum Off-Time
0
–50
55
20
TEMPERATURE (°C)
150
3743 G22
240
–15
3743 G21
MINIMUM ON-TIME (ns)
140
PWMGL TO PWMGH
NMOS
0
–50
125
Non-Overlap Time
150
NON-OVERLAP TIME (ns)
DELAY (ns)
Non-Overlap PWM Signal Delay
100
–50
2
3743 G20
150
120
PMOS
1
3743 G19
130
3
NMOS
1
0
–50
LG Driver RDS(ON)
4
RDS(ON) (Ω)
5
RDS(ON) (Ω)
RDS(ON) (Ω)
PWM Driver RDS(0N)
5
0
–1
55
20
TEMPERATURE (°C)
90
125
3743 G25
–3
–2
–4
–2
–15
0
0
2.5
5.0
7.5
OUTPUT VOLTAGE (V)
10
3743 G26
–6
0
2.5
5.0
7.5
OUTPUT VOLTAGE (V)
10
3743 G27
3743fd
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LT3743
TYPICAL PERFORMANCE CHARACTERISTICS
LED Current Waveforms
(90% PWM) 0.5A to 5A
Overcurrent Threshold
LED Current Waveforms
(2000:1) 3A to 10A
120
VSENSE+ – VSENSE– (mV)
80
60
ILED
5A/DIV
40
IL
10A/DIV
20
0
CTRL_SEL
5V/DIV
CTRL_SEL
5V/DIV
SW
20V/DIV
100
ILED
5A/DIV
IL
10A/DIV
40µs/DIV
0
0.75
1.5
CTRL_H (V)
2.25
3743 G29
5µs/DIV
3743 G30
3.0
3743 G28
CTRL_SEL
5V/DIV
SW
10V/DIV
ILED
11.1A/DIV
20µs/DIV
PWM
5V/DIV
CTRL_SEL
5V/DIV
PWM
5V/DIV
CTRL_L
0.2V/DIV
SW
10V/DIV
CTRL_SEL
5V/DIV
ILED
10A/DIV
ILED
8A/DIV
3743 G31
20µs/DIV
Voltage Regulation with 10A
Regulated Inductor Current
3743 G32
40µs/DIV
VOUT
2V/DIV
IL
5A/DIV
IL
200mA/DIV
3743 G34
3743 G33
Overvoltage Lockout Operation
With Open-Load Condition
Common Mode Lockout (VIN = 7V)
VOUT
2V/DIV
100µs/DIV
LED Current Waveforms (3000:1)
Analog Dimming on CTRL_L
COUT(LOW) = 22µF, COUT(HIGH) = 1mF
LED Current Waveforms
(3000:1) 0A to 2A to 20A
LED Current Waveforms
(3000:1) 2A to 20A
IL
200mA/DIV
VOUT
2V/DIV
1ms/DIV
3743 G35
40ms/DIV
3743 G36
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LT3743
PIN FUNCTIONS
(QFN/TSSOP)
GND (Pins 1, 5, 9, 20, 21, Exposed Pad Pin 29/Pins 2, 7,
11, 22, 27, Exposed Pad Pin 29): Ground. The exposed
pad must be soldered to the PCB.
EN/UVLO (Pin 2/Pin 4): Enable Pin. The EN/UVLO pin
acts as an enable pin and turns on the internal current
bias core and subregulators at 1.55V. The pin does
not have any pull-up or pull-down, requiring a voltage
bias for normal part operation. Full shutdown occurs at
approximately 0.5V.
VREF (Pin 3/Pin 5): Buffered 2V Reference Capable of
0.5mA Drive.
CTRL_T (Pin 4/Pin 6): The thermal control input to reduce
the regulated current level for both current levels (CTRL_L
and CTRL_H).
CTRL_H (Pin 6/Pin 8): The CTRL_H pin sets the high level
regulated output current and overcurrent. The maximum
input voltage is internally clamped to 1.5V. The overcurrent
set point is equal to the high level regulated current level
set by the CTRL_H pin with an additional 23mV offset
between the SENSE+ and SENSE– pins.
CTRL_L (Pin 7/Pin 9): The CTRL_L pin sets the low level
regulated output current. It is not recommended that the
CTRL_L voltage be higher than the CTRL_H voltage.
SS (Pin 8/Pin 10): Soft-Start Pin. Place an external capacitor
to ground to limit the regulated current during start-up
conditions. The SS pin has a 5.5µA charging current. This
pin controls both of the regulated inputs determined by
CTRL_L and CTRL_H.
FB (Pin 10/Pin 12): Feedback Pin for Overvoltage Protection. The feedback voltage is 1V. Overvoltage/Open LED
is sensed through the FB pin. When the feedback voltage
exceeds 1.3V, the overvoltage lockout prevents switching and connects both output capacitors to discharge the
inductor current.
SENSE+ (Pin 11/Pin 13): SENSE+ is the inverting input of
the average current mode loop error amplifier. This pin is
connected to the external current sense resistor, RS. The
voltage drop between SENSE+ and SENSE– referenced to
the voltage drop across an internal resistor produces the
input voltages to the current regulation loop.
SENSE– (Pin 12/Pin 14): SENSE– is the noninverting input
of the average current mode loop error amplifier. The
reference current, based on CTRL_L or CTRL_H flows out
of the pin to the output (LED) side of the sense resistor, RS.
VCL (Pin 13/Pin 15): VCL provides the necessary compensation for the average current loop stability during low level
current regulation. Typical compensation values are 15k
to 80k for the resistor and 2nF to 10nF for the capacitor.
VCH (Pin 14/Pin 16): VCH provides the necessary compensation for the average current loop stability during high level
current regulation. Typical compensation values are 15k
to 80k for the resistor and 2nF to 10nF for the capacitor.
RT (Pin 15/Pin 17): A resistor to ground sets the switching
frequency between 200kHz and 1MHz. When using the
SYNC function, set the frequency to be 20% lower than
the SYNC pulse frequency. This pin is current limited to
60µA. Do not leave this pin open.
SYNC (Pin 16/Pin 18): Frequency Synchronization Pin.
This pin allows the switching frequency to be synchronized
to an external clock. The RT resistor should be chosen to
operate the internal clock at 20% slower than the SYNC
pulse frequency. The synchronization range is 240kHz to
1.2MHz. This pin should be grounded when not in use.
CTRL_SEL (Pin 17/Pin 19): The CTRL_SEL pin selects
between the high current control, CTRL_H and the low
current control, CTRL_L. When high, the VCH pin is connected to the error amp output and the PWMGH gate
signal is high. When low, the VCL pin is connected to the
error amp output and the PWMGL gate signal is high. This
pin is used for current level dimming of the LED. This pin
should be grounded when not in use.
PWM (Pin 18/Pin 20): The input pin for PWM dimming
of the LED. When low, all switching is terminated and the
output caps are disconnected. This pin should be pulled
to VCC_INT when not in use.
PWMGH (Pin 19/Pin 21): The PWMGH output pin drives
the gate of an external FET to connect one of the switching
regulator output capacitors to the load. The driver pull-up
impedance is 3.2Ω and pull-down impedance is 1.75Ω.
3743fd
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LT3743
PIN FUNCTIONS
(QFN/TSSOP)
PWMGL (Pin 22/Pin 23): The PWMGL output pin drives
the gate of an external FET to connect one of the switching
regulator output capacitors to the load. The driver pull-up
impedance is 3.2Ω and pull-down impedance is 1.75Ω.
LG (Pin 26/Pin 28): LG is the bottom FET gate drive signal that controls the state of the low side external power
FET. The driver pull-up impedance is 2.5Ω and pull-down
impedance is 1.3Ω.
HG (Pin 23/Pin 24): HG is the top FET gate drive signal
that controls the state of the high side external power
FET. The driver pull-up impedance is 2.3Ω and pull-down
impedance is 1.3Ω.
VCC_INT (Pin 27/Pin 1): A regulated 5V output for charging
the CBOOT capacitor. VCC_INT also provides the power for
the digital and switching subcircuits. Below 6V VIN, tie
this pin to the rail. VCC_INT is current limited to ≈50mA.
Shutdown operation disables the output voltage drive.
SW (Pin 24/Pin 25): The SW pin is used internally as the
lower rail for the floating high side driver. Externally, this
node connects the two power FETs and the inductor.
VIN (Pin 28/Pin 3): Input Supply Pin. Must be locally
bypassed with a 1µF low ESR capacitor to ground.
CBOOT (Pin 25/Pin 26): The CBOOT pin provides a
floating 5V regulated supply for the high side FET driver.
An external Schottky diode is required from the VCC_INT
pin to the CBOOT pin to charge the CBOOT capacitor when
the switch pin is near ground.
3743fd
10
LT3743
BLOCK DIAGRAM
(QFN Package)
VIN
VIN
402k
2
INTERNAL
REGUALTOR
AND
UVLO
133k
3
2.2nF
SYNC
16
15
28
47µF
EN/UVLO
VREF
2V REFERENCE
SYNC
OSCILLATOR
RT
82.5k
–
R
+
S
Q
PWM
COMPARATOR
VCC_INT
27
10µF
HIGH SIDE
CBOOT
DRIVER
25
HG
23
SW
SYNCRONOUS
24
CONTROLLER
LG
26
LOW SIDE
DRIVER
SENSE+
0.1µF
2.2µH
10Ω
11
–
33nF
CTRL_L
+
+
5.5µA
+
–
CTRL BUFFER
8
100nF
4
13
34k
8.2nF
14
SENSE–
FB
CTRL_T
VCL
10Ω
12
RS
5mΩ
330µF
×3
10A LED
OUTPUT
330µF
×3
40.2k
10
10k
SS
90k
VOLTAGE
REGULATOR
AMP
+
7
CTRL_H
gm AMP
gm = 475µA/V
RO = 3.5M
IOUT = 40µA
–
6
CURRENT
MIRROR
3k
+
1.5V
VIN
1V
+
VCH
34k
8.2nF
OPEN-LED
COMPARATOR
17
18
CTRL_SEL
PWM
–
2.5Ω
2.5Ω
1.3V
PWMGL
PWMGH
22
19
3743 F01
Figure 1. Block Diagram
3743fd
11
LT3743
OPERATION
The LT3743 utilizes fixed frequency, average current
mode control to accurately regulate the inductor current,
independently from the output voltage. This is an ideal
solution for applications requiring a regulated current
source including driving high current LEDs where the
forward junction voltage can range from 2V to 6V with a
dynamic resistance of 20mΩ to 40mΩ. The control loop
will regulate the current in the inductor at an accuracy
of 6%. For additional operation information, refer to the
Block Diagram in Figure 1.
The control loop has two independent reference inputs,
determined by the analog control pins, CTRL_H and
CTRL_L. When the CTRL_SEL pin is low, the control loop
uses the reference determined by the CTRL_L pin and
when high, the loop uses the reference determined by
the CTRL_H pin. The analog voltage at the CTRL_L and
CTRL_H pins is buffered and produces a reference voltage
across an internal resistor. The internal buffers have a 1.5V
clamp on the output, limiting the analog control range of
the CTRL_L and CTRL_H pins from 0V to 1.5V. The average current mode control loop uses the internal reference
voltage to regulate the inductor current, as a voltage drop
across the external sense resistor, RS.
In many applications, a rapid transition between the two
regulated current states is desirable to provide background
LED color mixing for pure colors in an RGB projector
or display. For this purpose, pulse width modulation
dimming can be achieved with both the PWM and
CTRL_SEL pins. When the PWM pin is low, the regulated
current in the inductor is zero and both output capacitors
are disconnected. When the PWM pin is high, and the
CTRL_SEL pin is low, the regulated current in the inductor
is determined by the analog voltage at the CTRL_L pin.
When the PWM and CTRL_SEL pins are both high, the
regulated current in the inductor is determined by the
analog voltage at the CTRL_H pin.
The LT3743 uses a unique switched output capacitor
topology and two independent compensation networks to
transition between the two regulated current states in less
than 2µs. When the CTRL_SEL pin is low and the PWM
pin is high, the PWMGL output pin is high, switching in
the output capacitor for the CTRL_L current level. The
CTRL_L output capacitor stores the LED forward voltage
drop when the control loop regulates the low current
level. When the CTRL_SEL pin changes to the high state,
a 150ns delay ensures that the output capacitors are not
connected at the same time. After this delay, the output
capacitor for the CTRL_H level is switched in when
PWMGH goes high and immediately delivers current to the
LED. The CTRL_H output capacitor has the voltage drop
of the LED with the regulated current determined by the
analog voltage at the CTRL_H pin. To achieve minimum
transition delay, the inductor is precharged to 70% of the
regulation current level just after the PWMGH pin goes high.
Conversely, when the PWM pin goes low, the inductor is
discharged to 70% of the low current level before normal
switching at the low current level commences. The error
amplifier for the average current mode control loop also
has a common mode lockout that regulates the inductor
current so that the error amplifier is never operated out of
the common mode range. The common mode range is with
an output voltage from 0V to 2V below the VIN supply rail.
The overcurrent set point is equal to the high level regulated
current level set by the CTRL_H pin with an additional
23mV offset between the SENSE+ and SENSE– pins. The
overcurrent is limited on a cycle-by-cycle basis; shutting
switching down once the overcurrent level is reached.
Overcurrent is not soft started.
The output voltage may be limited with a resistor divider
from the output back to the FB pin. The reference at the
FB pin is 1.0V. If the output voltage level is high enough
to engage the voltage loop, the regulated inductor current
will be reduced so that the output voltage is limited. If the
voltage at the FB pin reaches 1.3V (30% higher than the
regulation level), an internal open-LED flag is set, shutting
down switching for 13µs and switching in both output
capacitors to fully drain the inductor’s current.
During start-up, the SS pin is held low until the first time
the PWM pin goes high. Once the PWM signal goes high,
the capacitor at the SS pin is charged with a 5.5µA current
source. The internal buffers for the CTRL_L and CTRL_H
signals are limited by the voltage at the SS pin, slowly
ramping the regulated inductor current to the current
determined by the voltage at the CTRL_H or CTRL_L pins.
3743fd
12
LT3743
APPLICATIONS INFORMATION
Programming Inductor Current
Inductor Selection
The analog voltage at the CTRL_L and CTRL_H pins is
buffered and produces a reference voltage, VCTRL, across
an internal resistor. The regulated average inductor current
is determined by:
The recovery time between regulated states is critical
to maintaining accurate control of the LED current. For
this reason, sizing the inductor to have no less than 30%
peak-to-peak ripple will provide excellent recovery time
with reasonable ripple. The overcurrent set point is equal
to the high level regulated current level set by the CTRL_H
pin with an additional 23mV offset between the SENSE+
and SENSE– pins. The saturation current for the inductor
should be at least 20% higher than the maximum regulated current. The following equation sizes the inductor
to achieve a reasonable recovery time while minimizing
the inductor ripple:
IO =
VCTRL
30 •RS
where RS is the external sense resistor and IO is the average inductor current, which is equal to the LED current.
Figure 2 shows the LED current vs RS. The maximum
power dissipation in the resistor will be:
PRS
2
0.05V )
(
=
L=
RS
Table 1 contains several resistors values, the corresponding maximum current and power dissipation in the sense
resistor. Figure 3 shows the power dissipation in RS.
Table 1. Sense Resistor Values
VIN • ( VF ) – ( VF )
2
0.2 • fS •IO • VIN
where VF is the LED forward voltage drop, IO is the maximum
regulated current in the inductor and fS is the switching
frequency. Using this equation, the inductor will have
approximately 10% ripple at maximum regulated current.
MAXIMUM LED
CURRENT (A)
RESISTOR, RS (mΩ)
POWER DISSIPATION (W)
1
50
0.05
VENDOR
WEBSITE
5
10
0.25
Coilcraft
www.coilcraft.com
10
5
0.5
Sumida
www.sumida.com
25
2
1.25
Table 2. Recommended Inductor Manufacturers
Vishay
www.vishay.com
Würth Electronics
www.we-online.com
NEC-Tokin
www.nec-tokin.com
30
25
1.2
15
10
5
0
0
2
4
6
8 10 12 14 16 18 20
RS (mΩ)
3743 F02
Figure 2. RS Value Selection for LED Current
POWER DISSIPATION (W)
LED CURRENT (A)
1.4
20
1.0
0.8
0.6
0.4
0.2
0
0
2
4
6
8 10 12
RS (mΩ)
14 16 18 20
3743 F03
Figure 3. Power Dissipation in RS
3743fd
13
LT3743
APPLICATIONS INFORMATION
Switching MOSFET Selection
When selecting switching MOSFETs, the following parameters are critical in determining the best devices for
a given application: total gate charge (QG), on-resistance
(RDS(ON)), gate to drain charge (QGD), gate-to-source
charge (QGS), gate resistance (RG), breakdown voltages
(maximum VGS and VDS) and drain current (maximum ID).
The following guidelines provide information to make the
selection process easier.
Both of the switching MOSFETs need to have their maximum
rated drain currents greater than the maximum inductor
current. The following equation calculates the peak inductor current:
2

VIN • ( VF +RDIO ) – ( VF +RDIO ) 

IMAX =IO +


2 • fS •L • VIN


where VIN is the input voltage, L is the inductance value, VF
is the LED forward voltage drop, RD is the dynamic series
resistance of the LED, IO is the regulated output current
and fS is the switching frequency. During MOSFET selection, notice that the maximum drain current is temperature
dependant. Most data sheets include a table or graph of
the maximum rated drain current vs temperature.
The maximum VDS should be selected to be higher than
the maximum input supply voltage (including transient)
for both MOSFETs. The signals driving the gates of the
switching MOSFETs have a maximum voltage of 5V with
respect to the source. During start-up and recovery conditions, the gate drive signals may be as low as 3V. To
ensure that the LT3743 recovers properly, the maximum
threshold should be less than 2V. For a robust design,
select the maximum VGS greater than 7V.
Power losses in the switching MOSFETs are related to
the on-resistance, RDS(ON); the transitional loss related
to the gate resistance, RG; gate-to-drain capacitance, QGD
and gate-to-source capacitance, QGS. Power loss to the
on-resistance is an Ohmic loss, I2 RDS(ON), and usually
dominates for input voltages less than ~15V. Power losses
to the gate capacitance dominate for voltages greater than
~12V. When operating at higher input voltages, efficiency
can be optimized by selecting a high side MOSFET with
higher RDS(ON) and lower CGD. The power loss in the high
side MOSFET can be approximated by:
PLOSS = (ohmic loss) + (transition loss)
PLOSS
( VF +RDIO ) •I2 R
VIN
O DS(ON) • T
+
VIN •IOUT
• ((QGD +QGS ) • (2 •RG +RPU +RPD )) • fS
5V
where ρT is a temperature-dependant term of the MOSFET’s on-resistance. Using 70°C as the maximum ambient
operating temperature, ρT is roughly equal to 1.3. RPD and
RPU are the LT3743 high side gate driver output impedance, 1.3Ω and 2.3Ω respectively.
A good approach to MOSFET sizing is to select a high side
MOSFET, then select the low side MOSFET. The tradeoff between RDS(ON), QG, QGD and QGS for the high side
MOSFET is shown in the following example. VO is equal
to 4V. Comparing two N-channel MOSFETs, with a rated
VDS of 40V and in the same package, but with 8× different
RDS(ON) and 4.5× different QG and QGD:
M1: RDS(ON) = 2.3mΩ, QG = 45.5nC,
QGS = 13.8nC, QGD = 14.4nC , RG = 1Ω
M2: RDS(ON) = 18mΩ, QG = 10nC,
QGS = 4.5nC, QGD = 3.1nC , RG = 3.5Ω
Power loss for both MOSFETs is shown in Figure 4. Observe that while the RDS(ON) of M1 is eight times lower, the
power loss at low input voltages is equal, but four times
higher at high input voltages than the power loss for M2.
Another power loss related to switching MOSFET selection
is the power lost to driving the gates. The total gate charge,
QG, must be charged and discharged each switching cycle.
The power is lost to the internal LDO within the LT3743.
The power lost to the charging of the gates is:
PLOSS_LDO ≈ (VIN – 5V) • (QGLG + QGHG) • fS
where QGLG is the low side gate charge and QGHG is the
high side gate charge.
3743fd
14
LT3743
APPLICATIONS INFORMATION
7
2.5
MOSFET POWER LOSS (W)
MOSFET POWER LOSS (W)
6
5
TOTAL
4
TRANSITIONAL
3
2
1
0
2.0
1.5
TOTAL
1.0
TRANSITIONAL
0.5
OHMIC
OHMIC
0
10
20
30
0
40
INPUT VOLTAGE (V)
0
20
10
30
40
INPUT VOLTAGE (V)
3743 F04a
3743 F04b
Figure 4a. Power Loss Example for M1
Figure 4b. Power Loss Example for M2
Figure 4
Whenever possible, utilize a switching MOSFET that
minimizes the total gate charge to limit the internal power
dissipation of the LT3743.
Table 3. Recommended Switching FETs
VIN VOUT ID
(V) (V) (A)
TOP FET
8
4
24
4
24
2-4
20
RJK0365DPA
12
2-4
10
FDMS8680
36
4
20
Si7884BDP
24
4
40
PSMN4R030YL
BOTTOM FET MANUFACTURER
5-10 RJK0365DPA RJK0330DPB Renesas
5 RJK0368DPA RJK0332DPB www.renesas.com
RJK0346DPA
FDMS8672AS Fairchild
www.fairchildsemi.
com
SiR470DP
Vishay
www.vishay.com
RJK0346DPA NXP/Philips
www.nxp.com
Input Capacitor Selection
The input capacitor should be sized at 4µF for every 1A
of output current and placed very close to the high side
MOSFET. A small 1µF ceramic capacitor should be placed
near the VIN and ground pins of the LT3743 for optimal
noise immunity. The input capacitor should have a ripple
current rating equal to half of the maximum output current.
It is recommended that several low ESR ceramic capacitors
be used as the input capacitance. Use only type X5R or
X7R capacitors as they maintain their capacitance over a
wide range of operating voltages and temperatures.
Output Capacitor Selection
The output capacitors need to have very low ESR (equivalent
series resistance) to allow the LED current to ramp quickly.
A minimum of 50µF/A of load current should be used in
most designs. The capacitors also need to be surge rated
to the maximum output current. To achieve the lowest
possible ESR, several low ESR capacitors should be used
in parallel. Many applications benefit from the use of high
density POSCAP capacitors, which are easily destroyed
when exposed to overvoltage conditions. To prevent this,
select POSCAP capacitors that have a voltage rating that
is at least 50% higher than the regulated voltage
CBOOT Capacitor Selection
The CBOOT capacitor must be sized less than 220nF and
more than 50nF to ensure proper operation of the LT3743.
Use 220nF for high current switching MOSFETs with high
gate charge.
3743fd
15
LT3743
APPLICATIONS INFORMATION
VCC_INT Capacitor Selection
60
The bypass capacitor for the VCC_INT pin should be larger
than 5µF for stability and has no ESR requirement. It is
recommended that the ESR be lower than 50mΩ to reduce
noise within the LT3743. For driving MOSFETs with gate
charges larger than 10nC, use 0.5µF/nC of total gate charge.
VSENSE+ – VSENSE– (mV)
50
LED Current Dimming
The LT3743 provides the capability of traditional zero to full
current PWM dimming as well as PWM dimming between
two regulated LED current states. When the PWM signal
is low, no switching occurs and the output capacitors
are disconnected from ground. When PWM is high and
CTRL_SEL is low, the inductor current is regulated to the
low current state. In this state, the PWMGL signal is high,
connecting the output capacitor for the low regulated
current state. When PWM and CTRL_SEL are both high,
the inductor current is regulated to the high current state.
In this state, the PWMGH signal is high, connecting the
output capacitor for the high regulated current state. The
transition time between each of the regulated inductor
currents is determined by the inductor size, VIN and VO.
Due to the use of the switched output capacitors, the LED
current will begin to flow within 130ns of the transition on
the CTRL_SEL pin. Figure 8 shows the LED and inductor
current waveforms with the various states of the control
signals.
To adjust the regulated LED current for the two control
states, an analog voltage is applied to the CTRL_L and
CTRL_H pins. Figure 6 shows the regulated voltage across
the sense resistor for control voltages up to 2V. Figure 7
shows the CTRL_L voltage created by a voltage divider
from VREF to ground. When sizing the resistor divider,
please be aware that the VREF pin is current limited to
500µA. Above 1.5V, the control voltage has no effect on
the regulated LED current.
For the widest dimming range, use the highest switching
frequency possible and lowest PWM frequency. For configuration with the maximum PWM range, please contact
factory for optimized component selection.
40
30
20
10
0
0
0.5
1.0
VCTRL (V)
1.5
2.0
3743 F06
Figure 6. LED Current vs CTRL Voltage
VREF
LT3743
R2
CTRL_L
R1
3743 F07
Figure 7. Analog Control of LED Current
tPWM
tON(PWM)
PWM
CTRL_SEL
INDUCTOR
CURRENT
PWMGH
PWMGL
LED
CURRENT
ICTRL_H
ICTRL_L
3743 F08
Figure 8. LED Current vs CTRL Voltage
3743fd
16
LT3743
APPLICATIONS INFORMATION
MOSFET Selection for the Switched Output Capacitors
The MOSFETs used for the switched-output capacitor need
to also handle the maximum regulated current while the
capacitor is charged. The output drivers on the PWMGH
and PWMGL pins have a pull-up impedance of 3.2Ω and
a pull-down impedance of 1.75Ω. This provides adequate
gate drive for the PWM MOSFETs without the need for an
additional gate driver. If the LED forward resistance and
the difference between the two regulated currents is large
enough, then two MOSFETs are required to prevent the body
diode of the MOSFET from conducting and discharging
the capacitor for the high current state. Figure 9 shows
the output capacitor for the high current regulation state
discharged with the body diode when a single MOSFET
is used. Figure 10 shows the application circuit with a
drain-to-drain configuration for the high current output
capacitor. In this configuration, the body diode of the upper MOSFET blocks conduction and prevents discharge
of the high current output capacitor.
If the voltage between the low state and the high state is
very large (greater than the threshold of the MOSFET) then
the capacitor may once again be discharged. To account for
this, choose a MOSFET that has a threshold greater than
the voltage difference. If the voltage difference exceeds
1.5V, use the circuit shown in Figure 11. The circuit shown
will keep the capacitor from discharging to a voltage difference of approximately 2V + VTH.
ICTRL_L = 1A
ICTRL_H = 20A
VF = 3V
RD = 200mΩ
PWMGH
LT3743
PWMGL
VCC_INT
3.01k
ICTRL_L = 1A
ICTRL_H = 20A
2k
3743 F11
3.8V
3.04V
VF = 3V
RD = 40mΩ
0V
PWMGH
OFF
LT3743
Figure 11. Application for Large Differences
in Regulated Currents
Board and Interconnect Inductance
5V
PWMGL
2V
ON
3743 F09
Figure 9. Body Diode of High Current FET
Discharges the Output Capacitor
ICTRL_L = 1A
ICTRL_H = 20A
3.8V
3.04V
VF = 3V
RD = 40mΩ
PWMGH
LT3743
PWMGL
3743 F10
Figure 10. With a Drain-to-Drain Configuration, the Body
Diode of the Top FET Blocks the Current Path That Would
Discharge the High Current Output Capacitor
The board and interconnect inductance from the output
capacitors to the load also determine the rate of change
in load (LED) current. The rate of change in load current
will be:
dIL VHIGH – VLOW
=
dt
LBOARD
where dIL/dt is the rate of change in the load current,
VHIGH is the output voltage when the inductor is regulated
at the high level, and VLOW is the output voltage when the
inductor is regulated at the low state. When measuring the
LED current do not use a current probe. The core material
used in most probes adds inductance and slows the rise
time of the LED current. Instead, when measuring the
current, use a sense resistor.
3743fd
17
LT3743
APPLICATIONS INFORMATION
Voltage Regulation and Overvoltage Protection
The LT3743 uses the FB pin to regulate the output to a
maximum voltage and to provide a high speed overvoltage
lockout to avoid high voltage conditions that may damage
expensive high current LEDs. The regulated output voltage
is programmed using a resistor divider from the output
and ground (Figure 12). When the output voltage exceeds
130% of the regulated voltage level (1.3V at the FB pin),
the internal open-LED flag is set, terminating switching
and forcing both PWMGL and PWMGH signals high. The
regulated output voltage must be greater than 2V and is
set by the equation:
VOUT =1V 1+
R2
R1
VOUT
LT3743
R2
FB
R1
The internal power consumption of the LT3743 is determined by the switching frequency, VIN, and the gate
charge, QG of the external switching MOSFETs selected.
The 4mm × 5mm QFN package has a θJA of 35°C/W. The
following equation calculates the maximum switching
frequency to avoid current limit and thermal shutdown at
a given ambient operating temperature, TA:
fS ≤
(163°C – TA )
(35°C/W ) • ( VIN – 5V ) • (QGHG +QGLG )
fS ≤
60mA
(QGLG +QGHG )
Since the regulated output current flowing into the LED
may be very large, the switching frequency needs to be
carefully considered. Higher switching frequencies will
reduce the large size of high saturation current inductors,
while reducing efficiency and increasing power loss within
the LT3743.
Table 4. Switching Frequency
SWITCHING FREQUENCY (MHz)
RT (kΩ)
3743 F12
Figure 12. Output Voltage Regulation and Overvoltage Protection
Feedback Connections
1
40.2
0.750
53.6
0.5
82.5
0.3
143
0.2
221
Soft-Start
Programming Switching Frequency
The LT3743 has an operational switching frequency
range between 200kHz and 1MHz. This frequency is
programmed with an external resistor from the RT pin to
ground. Do not leave this pin open under any condition.
The RT pin is also current limited to 60µA. See Table 4
and Figure 13 for resistor values and the corresponding
switching frequencies.
1.2
1.0
FREQUENCY (MHz)
Unlike conventional voltage regulators, the LT3743 utilizes
the soft-start function to control the regulated inductor
current. The charging current is 5.5µA and reduces the
regulated current for both the high and low regulated
current states. The SS pin is latched in a discharge state
until the first PWM pulse and is reset by UVLO and thermal
shutdown.
0.8
0.6
0.4
0.2
0
0
50 100 150 200 250 300 350 400 450 500
RT (kΩ)
3743 F13
Figure 13. Frequency vs RT Resistance
3743fd
18
LT3743
APPLICATIONS INFORMATION
Thermal Shutdown
The internal thermal shutdown within the LT3743 engages
at 163°C and terminates switching, resets soft-start and
shuts down the PWMGL and PWMGH drivers. When the part
has cooled to 155°C, the internal reset is cleared and softstart is allowed to charge once the PWM signal is asserted.
The EN/UVLO pin as an absolute maximum voltage of
6V. To accommodate the largest range of applications,
there is an internal Zener diode that clamps this pin. For
applications where the supply range is greater than 4:1,
size R2 greater than 375k.
VIN
Switching Frequency Synchronization
The nominal switching frequency of the LT3743 is determined
by the resistor from the RT pin to ground and may be set
from 200kHz to 1MHz. The internal oscillator may also be
synchronized to an external clock through the SYNC pin. The
external clock applied to the SYNC pin must have a logic low
below 0.3V and a logic high higher than 1.25V. The input frequency must be 20% higher than the frequency determined
by the resistor at the RT pin. Input signals outside of these
specified parameters will cause erratic switching behavior
and subharmonic oscillations. The synchronization range
is 240kHz to 1.2MHz. Synchronization is tested at 500kHz
with a 200k RT resistor. Operation under other conditions is
guaranteed by design. When synchronizing to an external
clock, please be aware that there will be a fixed delay from the
input clock edge to the edge of switch. The SYNC pin must
be grounded if the synchronization to an external clock is not
required. When SYNC is grounded, the switching frequency
is determined by the resistor at the RT pin.
Shutdown and UVLO
The LT3743 has an internal UVLO that terminates switching,
resets all synchronous logic, and discharges the soft-start
capacitor for input voltages below 4.2V. The LT3743 also
has a precision shutdown at 1.55V on the EN/UVLO pin.
Partial shutdown occurs at 1.55V and full shutdown is
guaranteed below 0.5V with <1µA IQ in the full shutdown
state. Below 1.5V, an internal current source provides
5.5µA of pull-down current to allow for programmable
UVLO hysteresis. The following equations determine the
voltage divider resistors for programming the UVLO voltage and hysteresis as configured in Figure 14.
VHYST
5.5µA
 1.55V •R2 
R1= 

 VUVLO – 1.55V 
R2 =
VIN
LT3743
R2
EN/UVLO
R1
3743 F14
Figure 14. UVLO Configuration
LED Current Derating Using the CTRL_T Pin
The LT3743 is designed specifically for driving high
current LEDs. Most high current LEDs require derating
the maximum current based on operating temperature
to prevent damage to the LED. In addition, many
applications have thermal limitations that will require the
regulated current to be reduced based on LED and/or
board temperature. To achieve this, the LT3743 uses the
CTRL_T pin to reduce the effective regulated current in
the LED for both the high and low control currents. While
CTRL_H and CTRL_L program the regulated current in the
LED, CTRL_T can be configured to reduce this regulated
current based on the analog voltage at the CTRL_T pin.
The LED/board temperature derating is programmed using
a resistor divider with a temperature dependant resistance
(Figure 15). When the board/LED temperature rises, the
CTRL_T voltage will decrease. To reduce the regulated
current, the CTRL_T voltage must be lower than voltage
at the CTRL_L and CTRL_H pins.
RV
RV
VREF
R2
LT3743
RNTC
RNTC
RX
RNTC
RNTC
RX
CTRL_T
R1
(OPTION A TO D)
3743 F15
A
B
C
D
Figure 15. LED Current Derating vs Temperature
Using NTC Resistor
3743fd
19
LT3743
APPLICATIONS INFORMATION
Average Current Mode Control Compensation
The use of average current mode control allows for precise
regulation of the inductor and LED currents. Figure 16
shows the average current mode control loop used in the
LT3743, where the regulation current is programmed by
a current source and a 3k resistor.
To design the compensation network, the maximum compensation resistor needs to be calculated. In current mode
controllers, the ratio of the sensed inductor current ramp
to the slope compensation ramp determines the stability
of the current regulation loop above 50% duty cycle. In
the same way, average current mode controllers require
the slope of the error voltage to not exceed the PWM ramp
slope during the switch off-time.
Since the closed-loop gain at the switching frequency
produces the error signal slope, the output impedance of
the error amplifier will be the compensation resistor, RC.
MODULATOR
VCTRL • 11µA/V
3k
L
RS
LOAD
+
gm
ERROR AMP
–
RC
3743 F16
CC
Figure 16. LT3743 Average Current Mode Control Scheme
Use the following equations as a good starting point for
compensation component sizing:
RC =
fS •L • 1000V
0.002
[Ω], CC =
[F]
VO •RS
fS
where fS is the switching frequency, L is the inductance
value, VIN is the input voltage and RS is the sense resistor.
For most LED applications, a 4.7nF compensation capacitor is adequate and provides excellent phase margin with
optimized bandwidth. Please refer to Table 6 for recommended compensation values.
For applications where the load is not an LED, please call
the factory for additional compensation assistance.
Board Layout Considerations
Average current mode control is relatively immune to the
switching noise associated with other types of control
schemes. Placing the sense resistor as close as possible
to the SENSE+ and SENSE– pins avoids noise issues and
ensures the fastest LED current transition time. For currents
exceeding 5A, use 10Ω resistors in-series with SENSE+
and SENSE–, with a 33nF capacitor placed as close as
possible to the SENSE+ and SENSE– pins. Utilizing a good
ground plane underneath the switching components will
minimize interplane noise coupling. To dissipate the heat
from the switching components, increase the area of the
switching node as much as possible without negatively
affecting the radiated noise. The interconnect inductance
and resistance between the output capacitors and the LED
load directly impacts the rise time of the load current. To
reduce the inductance and resistance, make the traces as
wide as physically possible and minimize the trace length.
Table 6. Recommended Compensation Values
VIN (V)
VO (V)
IL (A)
fSW (MHz)
L (µH)
RS (mΩ)
RC (kΩ)
CC (nF)
12
4
5
0.5
1.5
5
47.5
4.7
12
4
10
0.5
1.5
5
47.5
4.7
12
5
20
0.25
1.8
2.5
38.3
8.2
24
4
2
0.5
1.0
2.5
52.3
4.7
24
4
20
0.5
1.0
2.5
52.3
4.7
3743fd
20
LT3743
TYPICAL APPLICATIONS
12V, 20A LED Driver
EN/UVLO
PWM
CTRL_SEL
82.5k
VIN
EN/UVLO
PWM
CTRL_SEL
RT
SYNC
1µF
HG
100nF
CBOOT
VREF LT3743
2.2nF
LG
22µF
VIN
12V
M1
L1
1.0µH
SW
VCC_INT
CTRL_H
50k
10Ω
M2
OUTPUT
20A MAXIMUM
2.5mΩ
10Ω
C1
330µF
×3
33nF
GND
RNTC
10k
10nF
M3
SENSE+
SENSE–
PWMGH
CTRL_T
SS
1µF
D1
C3
330µF
×3
M4
PWMGL
60.4k
FB
VCL
VCH
34k
34k
4.7nF
4.7nF
C2
330µF
×3
D1: LUMINUS PT120
L1: IHLP4040DZER1R0M01
M1: RJK0365DPA
M2: RJK0346DPA
M3, M4: Si7236DP
C1, C2, C3: PTPR330M9L (THREE IN PARALLEL)
10k
3743 TA02
Efficiency (Stepping from 2A to 20A)
94
VIN = 12V
GREEN LED
92
90
EFFIENCY (%)
RHOT
499Ω
50k
CTRL_L
220µF
88
86
84
82
80
0
20
40
60
100
80
CTRL_SEL DIMMING DUTY CYCLE (%)
3743 TA02b
3743fd
21
LT3743
TYPICAL APPLICATIONS
6V to 36V, 2A LED Driver With Shunted Output
EN/UVLO
INTVCC
CTRL_SEL
82.5k
VIN
EN/UVLO
PWM
CTRL_SEL
RT
SYNC
1µF
HG
100nF
CBOOT
VREF LT3743
2.2nF
RHOT
499Ω
CTRL_L
CONTROL
INPUT
SW
VCC_INT
LG
CTRL_H
8.2µF
VIN
6V TO 36V
Shunted Output with CTRL_H
Equal to CTRL_L
M1
L1
10µH
OUTPUT
2A MAXIMUM
25mΩ
2.2µF
22µF
CTRL_SEL
5V/DIV
IL
D1
2A/DIV
M2
ILED
1A/DIV
GND
CTRL_T
RNTC
10k
SENSE+
SENSE–
SW
2V/DIV
PWMGH
10nF
SS
PWMGL
M3
20µs/DIV
3743 TA03b
40.2k
FB
VCL
VCH
34k
34k
4.7nF
10k
D1: LUMINUS CBT-40
L1: MSS1048-103MLB
M1, M2: Si7848BDP
M3: Si2312BDS
4.7nF
3743 TA03
6V to 36V, 2A LED Driver With Current Limited Shunted Output
EN/UVLO
INTVCC
CTRL_SEL
82.5k
VIN
EN/UVLO
PWM
CTRL_SEL
RT
SYNC
1µF
HG
100nF
CBOOT
2.2nF
VREF LT3743
CONTROL
INPUT
RHOT
499Ω
CTRL_H
CTRL_L
CTRL_T
RNTC
10k
10nF
SS
8.2µF
VIN
6V TO 36V
Shunted Output with CTRL_L at GND
M1
L1
10µH
SW
25mΩ
OUTPUT
2A MAXIMUM
CTRL_SEL
5V/DIV
2.2µF
VCC_INT
LG
22µF
D1
M2
IL
2A/DIV
GND
ILED
1A/DIV
SENSE+
SENSE–
PWMGH
SW
10V/DIV
20µs/DIV
M3
PWMGL
3743 TA04b
40.2k
FB
VCL
34k
4.7nF
VCH
34k
4.7nF
D1: LUMINUS CBT-40
L1: IHLP4040DZE10R0M01
M1, M2: Si7848BDP
M3: Si2312BDS
10k
3743 TA04
3743fd
22
LT3743
TYPICAL APPLICATIONS
6V to 30V, 20A LED Driver with Switched Cathode
EN/UVLO
PWM
VCC_INT
82.5k
1µF
HG
150nF
CBOOT
VREF LT3743
2.2nF
CTRL_L
RHOT CONTROL
499Ω
INPUT
10nF
82µF
M1
L1
1.1µH
2.5mΩ
SW
VCC_INT
LG
CTRL_H
22µF
10Ω
M2
CTRL_T
SENSE+
SENSE–
PWMGL
SS
PWMGH
OUTPUT
20A MAXIMUM
10Ω
C1
330µF
×3
D1
33nF
GND
RNTC
10k
VIN
6V TO 30V
VIN
EN/UVLO
PWM
CTRL_SEL
RT
SYNC
M3
60.4k
FB
VCL
VCH
34k
4.7nF
10k
D1: LUMINUS PT121
L1: MVR1261C-112ML
3743 TA05
M1: RJK0365DPA
M2: RJK0328DPB
M3: SiR496DP
C1: PTPR330M9L (THREE IN PARALLEL)
Switched Cathode PWM Dimming (100:1) 0A to 20A
0A to 20A Efficiency
100
90
PWM
5V/DIV
EFFICIENCY (%)
80
ILED
10A/DIV
SW
10V/DIV
10µs/DIV
3743 TA05b
70
60
50
40
30
20
VIN = 12V
GREEN LED
10
0
0
20
60
80
40
PWM DIMMING DUTY CYCLE (%)
100
3743 TA05c
3743fd
23
LT3743
TYPICAL APPLICATIONS
24V, 20A 3-LED Driver
82.5k
VIN
EN/UVLO
PWM
CTRL_SEL
RT
SYNC
1µF
HG
100nF
CBOOT
VREF LT3743
2.2nF
20k
CTRL_H
60.4k
RHOT
499Ω
SW
VCC_INT
LG
GND
CTRL_L
82µF
RNTC
10k
10nF
95
L1
1.2µH
VCL
90
OUTPUT
20A MAXIMUM
2.5mΩ
470µF
20µF
M2
10Ω
10Ω
33nF
SENSE+
SENSE–
RED
LEDs
85
80
75
70
65
60
M3
PWMGL
SS
100
M1
PWMGH
CTRL_T
Efficiency
VIN
24V
EFFICIENCY (%)
EN/UVLO
PWM
VCC_INT
316k
FB
VIN = 24V
3 RED LEDs
0
20
60
40
DUTY CYCLE (%)
80
100
3743 TA07b
VCH
20k
24.3k
4.7nF
3743 TA07
L1: 1HLP5050FDER1R2M01
M1: Si7848BDP
M2, M3: RJK0330DPB
3743fd
24
LT3743
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3743fd
25
LT3743
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV I 0211
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3743fd
26
LT3743
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
2/10
Revised Features and Typical Application
1
Updated Electrical Characteristics values
3, 4
Revised values on curves G32 and G33 in the Typical Performance Characteristics section
8
Revised the Block Diagram
11
Changed value in equation and made minor text edit in the Inductor Selection section
13
Revised Table 4 values
18
Added text to Average Current Mode Control Compensation and Board Layout Considerations sections in the
Applications Information section
20
Revised all Typical Applications drawings
B
8/10
21 to 25, 28
Updated Electrical Characteristics values and conditions
3, 4
Revised Pin Functions
9, 10
Revised Block Diagram
11
Changed soft-start current in Operation section
12
Revised units for M1 and M2 equations
14
Removed 0.1MHz switching frequency from Table 4
18
Added text to Switching Frequency Synchronization, Shutdown and UVLO sections in the Applications
Information section
19
Corrected M2 and M3 part numbers on Typical Applications drawings
C
9/11
Revised Feedback Regulation Voltage listing in Electrical Characteristics section
D
11/12
Clarified VCL and VCH pins
24, 28
3
1, 2, 9, 11, 21-24
Clarified Regulated Current vs VFB graph
6
Clarified Minimum Off-Time graph
7
3743fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3743
TYPICAL APPLICATION
12V, 40A Pulsed LED Driver
EN/UVLO
PWM
CTRL_SEL
EN/UVLO
PWM
CTRL_SEL
150k
RT
SYNC
VIN
HG
4.7µF
×8
1µF
RHOT
499Ω
50k
1µF
CTRL_L
220nF
L1
1µH
CTRL_H
50k
1µF
SW
VCC_INT
LG
CTRL_T
RNTC
10k
22µF
M2
×2
GND
SENSE+
SENSE–
220µF
M1
×2
CBOOT
VREF LT3743
220µF
OUTPUT
40A MAXIMUM
1.25mΩ
10Ω
10Ω
33nF
C1
330µF
×3
SS
1µF
CTRL_SEL
5V/DIV
D1
ILED
20A/DIV
C3
330µF
×3
SW
10V/DIV
M3
M4
PWMGH
1µF
VIN = 12V
4A to 40A LED Current Step
VIN
12V
20µs/DIV
3743 TA08b
PWMGL
140k
FB
VCL
51k
5.6nF
VCH
51k
5.6nF
1nF
C2
330µF
×3
20k
3743 TA08
L1: 1HLP5050FDER1R0M01
M1, M2: RJK0330DPB
M3, M4: Si7234DP
C1, C2, C3: PTPR33OM9L
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3755/LT3755-1
High Side 40V, 1MHz LED Controller with True Color
3000:1 PWM Dimming
VIN: 4.5V to 40V, VOUT(MAX) = 60V, Dimming = 3000:1 True Color PWM™,
ISD < 1µA, 3mm × 3mm QFN16, MSOP16E
LT3756/LT3756-1
High Side 100V, 1MHz LED Controller with True Color
3000:1 PWM Dimming
VIN: 6V to 100V, VOUT(MAX) = 100V, Dimming = 3000:1 True Color PWM,
ISD < 1µA, 3mm × 3mm QFN16, MSOP16E
LTC3783
High Side 36V, 1MHz LED Controller with True Color
3000:1 PWM Dimming
VIN: 3V to 36V, VOUT(MAX) = 40V, Dimming = 3000:1 True Color PWM,
ISD < 20µA, 4mm × 5mm DFN16, TSSOP16E
LT3517
1.3A, 2.5MHz High Current LED Driver with 3000:1
Dimming
VIN: 3V to 30V, Dimming = 3000:1 True Color PWM, ISD < 1µA,
4mm × 4mm QFN16
LT3518
2.3A, 2.5MHz High Current LED Driver with 3000:1
Dimming
VIN: 3V to 30V, Dimming = 3000:1 True Color PWM, ISD < 1µA,
4mm × 4mm QFN16
LT3496
Triple Output 750mA, 2.1MHz High Current LED Driver
with 3000:1 Dimming
VIN: 3V to 30V, VOUT(MAX) = 40V, Dimming = 3000:1 True Color PWM,
ISD < 1µA, 4mm × 5mm QFN28
LT3474/LT3474-1
36V, 1A (ILED), 2MHz Step-Down LED Driver
VIN: 4V to 36V, VOUT(MAX) = 13.5V, Dimming = 400:1 True Color PWM,
ISD < 1µA, TSSOP16E
LT3475/LT3475-1
Dual 1.5A (ILED), 36V Step-Down LED Driver
VIN: 4V to 36V, VOUT(MAX) = 13.5V, Dimming = 3000:1 True Color PWM,
ISD < 1µA, TSSOP20E
LT3476
Quad Output 1.5A, 2MHz High Current LED Driver with
1000:1 Dimming
VIN: 2.8V to 16V, VOUT(MAX) = 36V, Dimming = 1000:1 True Color PWM,
ISD < 10µA, 5mm × 7mm QFN10
LT3478/LT3478-1
4.5A, 2MHz High Current LED Driver with 3000:1
Dimming
VIN: 2.8V to 36V, VOUT(MAX) = 40V, Dimming = 1000:1 True Color PWM,
ISD < 10µA, 5mm × 7mm QFN10
3743fd
28 Linear Technology Corporation
LT 1112 REV D • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
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