MITSUBISHI LSIsLSIs MITSUBISHI M5M4V4405CJ,TP-6,-7,-6S,-7S M5M4V4405CJ,TP-6,-7,-6S,-7S EDOEDO (HYPER (HYPER PAGE PAGE MODE) MODE) 4194304-BIT 4194304-BIT(1048576-WORD (1048576-WORD BY BY 4-BIT) 4-BIT) DYNAMIC DYNAMIC RAM RAM DESCRIPTION This is a family of 1048576-word by 4-bit dynamic RAMS, fabricated with the high performance CMOS process,and is ideal for large-capacity memory systems where high speed, low power dissipation , and low costs are essential. The use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application. FEATURES RAS CAS Address OE Cycle Power dissipaaccess access access access tion time time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW) Type name M5M4V4405CXX-6, -6S M5M4V4405CXX-7, -7S 60 70 15 20 30 35 15 20 110 130 264 231 PIN CONFIGURATION (TOP VIEW) DQ1 1 26 VSS DQ2 2 25 DQ4 W 3 24 DQ3 RAS 4 23 CAS A9 5 22 OE A0 9 18 A8 A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 VCC 13 14 A4 XX=J, TP Standard 26 pin SOJ, 26 pin TSOP(II) Single 3.3V±0.3V supply Low stand-by power dissipation CMOS lnput level .................................................1.8mW(Max)* CMOS lnput level ................................................180µW(Max) Low operating power dissipation M5M4V4405Cxx-6, -6S .....................................288.0mW (Max) M5M4V4405Cxx-7, -7S ....................................252.0mW (Max) Self refresh capabiility* Self refresh current ..............................................100µA(max) Extended refresh capability* Extended refresh current ....................................100µA(max) Hyper-page mode (1024-bit random access), Read-modify- write, RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR self refresh(-6S,-7S) capabilities. Early-write mode and OE and W to control output buffer impedance 1024 refresh cycles every 16.4ms (A0~A9) 1024refresh cycle every128ms (A0~A9)* *: Applicable to self refresh version (M5M4V4405Cxx-6S,-7S: option) only APPLICATION Lap top personal computer,Solid state disc, Microcomputer memory, Refresh memory for CRT PIN DESCRIPTION Pin name A0~A9 DQ1~DQ4 RAS CAS W OE VCC VSS 1 Function Address inputs Data inputs / outputs Row address strobe input Column address strobe input Write control input Output enable input Power supply (+3.3V) Ground (0V) Outline 26P0J (300mil SOJ) DQ1 1 26 VSS DQ2 2 25 DQ4 W 3 24 DQ3 RAS 4 23 CAS A9 5 22 OE A0 9 18 A8 A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 VCC 13 14 A4 Outline 26P3Z-E (300mil TSOP) MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM FUNCTION Hyper Page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1. In addition to normal read, write, and read-modify-write operations the M5M4V4405CJ,TP provide, a number of other functions, e.g., Table 1 Input conditions for each mode Inputs Input/Output Operation Read Write (Early write) Write (Delayed write) Read-modify-write RAS-only refresh Hidden refresh CAS before RAS refresh Self refresh* Stand-by RAS CAS W OE ACT ACT ACT ACT ACT ACT ACT ACT NAC ACT ACT ACT ACT NAC ACT ACT ACT DNC NAC ACT ACT ACT DNC DNC ACT DNC NAC ACT DNC ACT DNC DNC DNC NAC NAC DNC Row Column address address APD APD APD APD APD DNC DNC DNC DNC APD APD AP D APD DNC DNC DNC DNC DNC Input Output OPN APD APD APD DNC OPN DNC VLD OPN IVD VLD OPN VLD OPN OPN DNC DNC OPN Refresh Remark YES YES YES YES YES YES YES YES NO Hyper Page mode identical Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open BLOCK DIAGRAM VCC (3.3V) COLUMN ADDRESS STROBE INPUT CAS ROW ADDRESS RAS STROBE INPUT WRITE CONTROL INPUT CLOCK GENERATOR CIRCUIT W A0 ~ A9 ADDRESS INPUTS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 2 VSS (0V) COLUMN DECODER (4) DATA IN BUFFERS DQ1 DQ2 DQ3 DQ4 SENSE REFRESH AMPLIFER & I /O CONTROL ROW & COLUMN ADDRESS BUFFER ROW A 0~ A9 DECODER MEMORY CELL (4,194,304 BITS) DATA INPUTS / OUTPUTS (4) DATA OUT BUFFERS OUTPUT OE ENABLE INPUT MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 With respect to VSS 50 1000 0 ~ 70 -65 ~ 150 Ta=25 C RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) Symbol VCC VSS VIH VIL Parameter Min Supply voltage Supply voltage High-level input voltage, all inputs DQ1~DQ4 Low-level input voltage others 3.0 0 2.0 -0.3 -0.3 Unit V V V mA mW C C Limits Nom Max 3.3 0 3.6 0 (Note 1) Unit VCC+0.3 V V V 0.8 0.8 V V Note 1 : All voltage values are with respect to VSS. ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V± 0.3V, VsS=0V, unless otherwise noted) Symbol VOH VOL IOZ II ICC1 (AV) ICC2 (AV) ICC3 (AV) ICC4(AV) ICC6(AV) ICC8(AV)* ICC9(AV)* 3 Parameter Test conditions High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from VCC operating (Note 3,4,5) Supply current from VcC , stand-by (Note 6) IOH=-2mA IOL=2mA Q floating, 0V≤VOUT≤VCC 0V≤VIN≤VCC+0.3V, Other inputs pins=0V Min 2.4 (Note 2) Limits Typ 0 -5 -5 RAS, CAS cycling tRC=tWC=min. M5M4V4405C-7,-7S output open RAS=CAS =VIH, output open M5M4V4405C-6,-6S M5M4V4405C M5M4V4405C(S) RAS=CAS≥VCC -0.2V output open Max Vcc 0.4 5 5 mA 70 2 0.5 80 tRC=min. M5M4V4405C-7,-7S output open 70 Average supply current from VCC Hyper-Page-Mode (Note 3,4,5) Average supply current from VCC, CAS before RAS refresh mode (Note 3) M5M4V4405C-6,-6S RAS=VIL, CAS cycling 80 tPC=min. M5M4V4405C-7,-7S output open 70 M5M4V4405C-6,-6S CAS before RAS refresh cycling 70 tRC=min. M5M4V4405C-7,-7S output open 60 Average supply current from VCC Self-Refresh cycle (Note 6) M5M4V4405C(S) mA 0.05 * M5M4V4405C-6,-6S RAS cycling, CAS= VIH (Note 6) V V µA µA 80 Average supply current from VCC refreshing (Note 3,5) Average supply current from VCC Extended-Refresh cycle Unit mA mA mA RAS cycling CAS≤0.2V or CAS before RAS refresh cycling RAS≤0.2V or ≥VCC-0.2V CAS≤0.2V or ≥VCC-0.2V W≤0.2V (Except for RAS falling edge) or ≥VCC-0.2V OE≤0.2V or ≥VCC-0.2V A0~A9 ≤0.2V or≥VCC-0.2V DQ=open tRC=125µs, tRAS=tRAS min ~1µs 100 µA RAS=CAS≤0.2V output open 100 µA Note 2: Current flowing into an IC is positive, out is negative. 3: ICC1 (AV), ICC3 (AV), ICC4 (AV) and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Addres can be changed once or less while RAS=VIL and CAS=VIH. MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM CAPACITANCE (Ta=0~70˚C, VCC=3.3V±0.3V, Vss=0V, unless otherwise noted) Symbol CI (A) CI (CLK) CI / O Test conditions Parameter Input capacitance, address inputs Input capacitance, clock inputs Input/Output capacitance, data ports Min Limits Typ VI=VSS f=1MHz VI=25mVrms Max 5 7 7 Unit pF pF pF SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15) Symbol Limits Å@ Parameter M5M4V4405C-6,-6S Min tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE Output hold time from CAS Output hold time from RAS Output low impedance time from CAS low Output disable time after OE high Output disable time after WE low Output disable time after CAS high Output disable time after RAS high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 13) (Note 7) (Note 12) (Note 12) (Note 12,13) (Note 12,13) Max 15 60 30 33 15 5 5 5 M5M4V4405C-7,-7S Min ns ns ns ns ns 20 20 20 20 ns ns ns ns ns ns ns 5 5 5 15 15 15 15 Unit Max 20 70 35 38 20 Note 6: An initial pause of 200µs is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh or CAS before RAS refresh cycles)ÅDÅ@Å@Å@Å@Å@Å@Å@Å@Å@Å@Å@Å@Å@ Å@ Note the RAS may be cycled during the initial pause. And eight initialization cycles are required after prolonged periods (greater than tREF(max)) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 100pF, VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=2mA). The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that tRCD≥tRCD(max) and tASC≥tASC(max) and tCP≥tCP(max). 9: Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD≥tRAD(max) and tASC≤tASC(max). 11: Assumes that tCP≤tCP(max) and tASC≥tASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state(IOUT≤ | ±10µA |) and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both RAS and CAS go to high. 4 MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Hyper-Page Mode Cycles) (Ta=0~70˚C, VCC = 3.3V±0.3V, VSS =0V, unless otherwise noted, see notes 14,15) Limits Parameter Symbol M5M4V4405C-6,-6S Min tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT Refresh cycle time Refresh cycle time* RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, data to OE low Delay time, RAS high to data Delay time, CAS high to data Delay time, OE high to data Transition time Max M5M4V4405C-7,-7S Min 16.4 128 (Note 16) (Note 17) (Note 18) (Note 19) (Note 19) (Note 20) (Note 20) (Note 20) (Note 21) 40 20 5 0 10 15 0 0 10 10 0 0 15 15 15 1 Max 16.4 128 50 45 20 5 0 13 15 0 0 10 10 0 0 20 20 20 1 30 13 50 50 35 13 Unit ms ms ns ns ns ns ns ns ns ns ns ns ns 50 ns ns ns ns ns Note 14: The timing requirements are assumed tT =2ns. Å@ 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Å@ 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. Å@ 17: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA. Å@ 18: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC. Å@ 19: Either tDZC or tDZO must be satisfied. Å@ 20: Either tRDD or tCDD or tODD must be satisfied. Å@ 21: tT is measured between VIH(min) and VIL(max). Read and Refresh Cycles Limits Parameter Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read Setup time before CAS low Read hold time after CAS high Read hold time after RAS high Column address to RAS hold time Column address to CAS hold time RAS hold time after OE low CAS hold time after OE low Note 22: Either tRCH or tRRH must be satisfied for a read cycle. 5 M5M4V4405C-6,-6S (Note 22) (Note 22) Min 110 60 10 48 15 0 0 0 30 18 15 15 Max 10000 10000 M5M4V4405C-7,-7S Min 130 70 13 55 20 0 0 0 35 23 20 20 Unit Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Write Cycle (Early Write and Delayed Write) Limits Parameter Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH M5M4V4405C-6,-6S Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low (Note 24) Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low Min 110 60 10 48 10 0 10 10 10 10 0 10 Max 10000 10000 M5M4V4405C-7,-7S Min 130 70 13 55 13 Unit Max 10000 10000 0 13 13 13 13 0 13 ns ns ns ns ns ns ns ns ns ns ns ns Read-Write and Read-Modify-Write Cycles Limits Parameter Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before0 CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low OE hold time after W low M5M4V4405C-6,-6S (Note 23) (Note 24) (Note 24) (Note 24) Min 133 89 44 89 44 0 32 77 47 15 Max 10000 10000 M5M4V4405C-7,-7S Min 161 107 57 107 57 0 42 92 57 20 Unit Max 10000 10000 ns ns ns ns ns ns ns ns ns ns Note 23: tRWC is specified as tRWC(min )=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. Å@ 24: tWCS, tCWD, tRWD, tAWD, and tCPWD are specified as reference points only. If tWCS≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. IftCWD≥tCWD(min), tRWD≥tRWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD (min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate. 6 MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hyper page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25) Limits Parameter Symbol tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Hyper page mode read/write cycle time Hyper Page Mode read write / read modify write cycle time Output hold time from CAS low RAS low pulse width for read or write cycle CAS high pulse width RAS hold time after CAS precharge Delay time, CAS precharge to W low Hold time to maintain the data Hi-Z until CAS access OE Pulse Width (Hi-Z control) W Pulse Width (Hi-Z control) Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read M5M4V4405C-6,-6S (Note 26) (Note 27) (Note 28) (Note 24) Min 25 66 5 Max 77 10 33 50 7 100000 16 M5M4V4405C-7,-7S Min 30 79 5 92 13 38 60 7 7 7 32 47 50 15 30 33 Unit Max 100000 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 7 42 57 60 20 35 38 Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tHPC(min) is specified in the case of read-only and early write-only in Hyper page Mode. 27: tRAS(min) is specified as two cycles of CAS input are performed. 28: tCP(max)) is specified as a reference point only. CAS before RAS Refresh Cycle (Note 29) Limits Parameter Symbol tCSR tCHR CAS setup time before RAS low CAS hold time after RAS low tRSR tRHP tCAS Read setup time before RAS low Read hold time after RAS low CAS low pulse width M5M4V4405C-6,-6S Min 5 10 10 10 17 Max M5M4V4405C-7,-7S Min 5 15 10 15 22 Unit Max ns ns ns ns ns Note 29: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. Self Refresh Cycle* (Note 30) Limits Symbol tRASS tRPS tCHS tRSR tRHR 7 Parameter CBR self refresh RAS low pulse width CBR self refresh RAS high precharge time CBR self refresh CAS hold time Read setup time before RAS low Read hold time after RAS low M5M4V4405C-6,-6S Min 100 110 -50 10 10 Max M5M4V4405C-7,-7S Min 100 130 -50 10 15 Unit Max µs ns ns ns ns MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Test Mode Specification (Note 31) ELECTRICAL CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V±0.3V, VSS=0V, unless otherwise noted) (Note 2) Symbol ICC1 (AV) ICC3 (AV) ICC4(AV) ICC6(AV) Parameter Average supply current from VCC operating (Note 3,4,5) Average supply current from VCC refreshing (Note 3,5) Average supply current from VCC Hyper-Page-Mode (Note 3,4,5) Average supply current from VCC CAS before RAS refresh (Note 3) mode Test conditions M5M4V4405C-6,-6S M5M4V4405C-7,-7S M5M4V4405C-6,-6S M5M4V4405C-7,-7S M5M4V4405C-6,-6S M5M4V4405C-7,-7S M5M4V4405C-6,-6S M5M4V4405C-7,-7S Min Limits Typ Max RAS, CAS cycling tRC=tWC=min. output open 85 RAS cycling, CAS= VIH tRC=min. output open 85 RAS=VIL, CAS cycling tPC=min. output open 85 Unit mA 75 mA 75 mA 75 CAS before RAS refresh cycling tRC=min. output open 75 mA 65 Note 31: All previously specified electrical characteristics, switing characteristics, and timing requirements are applicable to that of test mode. SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3V±0.3V, VSS=0V, unless otherwise noted, see notes 6,14,15) Limits Parameter Symbol M5M4V4405C-6,-6S Min tCAC tRAC tAA tCPA tOEA (Note 7,8) (Note 7,9) Access time from CAS Access time from RAS Column address access time Access time from CAS precharge Access time from OE M5M4V4405C-7,-7S Max 20 Min 65 35 38 20 (Note 7,10) (Note 7,11) (Note 7) Max 25 75 40 43 25 Unit ns ns ns ns ns TIMING REQUIREMENTS (Ta=0~70˚C, VCC=3.3V±0.3V, VSS=0V, unless otherwise noted, see notes 14,15) Read and Refresh Cycles Limits Parameter Symbol tRC tRAS tCAS tCSH tRSH tRAL tCAL tORH tOCH M5M4V4405C-6,-6S Min 115 65 Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Column address to RAS hold time Column address to CAS hold time RAS hold time after OE low CAS hold time after OE low 15 53 20 35 23 20 20 Max 10000 M5M4V4405C-7,-7S Min 135 75 10000 18 60 25 40 28 25 25 Unit Max 10000 10000 ns ns ns ns ns ns ns ns ns Read-Write and Read-Modify-Write Cycles Limits Parameter Symbol tRWC tRAS tCAS tCSH tRSH tCWD tRWD tAWD 8 Read write/read modify write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low M5M4V4405C-6,-6S (Note 23) (Note 24) (Note 24) (Note 24) Min 138 94 49 94 49 37 82 52 Max 10000 10000 M5M4V4405C-7,-7S Min 166 112 62 112 62 47 97 62 Unit Max 10000 10000 ns ns ns ns ns ns ns ns MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hyper page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25) Limits Parameter Symbol tHPC tHPRWC tRAS tCPRH tCPWD tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Hyper page mode read/write cycle time Hyper Page Mode read write / read modify write cycle time RAS low pulse width for read or write cycle RAS hold time after CAS precharge Delay time, CAS precharge to W low Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read M5M4V4405C-6,-6S (Note 26) (Note 27) (Note 24) Min 30 71 82 38 55 37 52 55 20 35 38 Max 100000 M5M4V4405C-7,-7S Min 35 84 97 43 65 47 62 65 25 40 43 Unit Max 100000 ns ns ns ns ns ns ns ns ns ns ns Test Mode Set Cycle Limits Parameter Symbol tWSR tWHR 9 Write setup time before RAS low Write hold time after RAS low M5M4V4405C-6,-6S Min 10 10 Max M5M4V4405C-7,-7S Min 10 15 Unit Max ns ns MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Timing Diagrams Read Cycle (Note 32) tRC tRAS RAS tRP VIH VIL tCSH tCRP tRCD tRSH tCAS tCRP VIH CAS VIL tRAL tCAL tRAD tASR VIH A0 ~A9 VIL tRAH tASC ROW ADDRESS tASR tCAH ROW ADDRESS COLUMN ADDRESS tRRH tRCH tRCS W VIH VIL tCDD tDZC DQ1~DQ4 (INPUTS) VIH Hi-Z VIL tREZ tCAC tAA tOHR tCLZ DQ1~DQ4 (OUTPUTS) VOH VOL Hi-Z Hi-Z DATA VALID tRAC tDZO tOEA tOCH OE tWEZ tOFF tOHC tOEZ tODD VIH VIL tORH Note 32 Indicates the don't care input. VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max) Indicates the invalid output. MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Early Write Cycle tWC tRAS RAS tRP VIH VIL tCSH tCRP CAS tRCD tRSH tCAS tCRP VIH VIL tASR VIH A0~A9 VIL tASC tRAH ROW ADDRESS COLUMN ADDRESS ROW ADDRESS tWCS W tASR tCAH tWCH VIH VIL tDS DQ1~DQ4 (INPUTS) DQ1~DQ4 (OUTPUTS) OE VIH tDH DATA VALID VIL VOH VOL VIH VIL Hi-Z MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Delayed Write Cycle tWC tRP tRAS RAS VIH VIL tCRP tCSH tCRP tRSH tRCD tCAS CAS VIH VIL tASR VIH A0~A9 VIL tRAH tASC tCAH ROW ADDRESS tASR ROW ADDRESS COLUMN ADDRESS tCWL tRWL tWP tRCS W VIH VIL tWCH tDZC DQ1~DQ4 (INPUTS) tDS VIH Hi-Z tDH DATA VALID VIL tCLZ DQ1~DQ4 (OUTPUTS) VOH Hi-Z Hi-Z VOL tDZO tOEZ tODD VIH OE VIL tOEH MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle tRWC tRAS tRP VIH RAS VIL tCRP tCSH tRCD tCRP tRSH tCAS VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH tCAH tASC tASR COLUMN ADDRESS ROW ADDRESS ROW ADDRESS tAWD tCWD tRWD tRCS tCWL tRWL tWP VIH W VIL tDH tDS tDZC DQ1~DQ4 (INPUTS) VIH Hi-Z VIL DATA VALID tCAC tAA tCLZ DQ1~DQ4 (OUTPUTS) VOH VOL Hi-Z Hi-Z DATA VALID tRAC tODD tDZO tOEH tOEA tOEZ OE VIH VIL MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hyper Page Mode Read Cycle tRAS tRP VIH RAS VIL tCSH tCRP tCAS tRCD tCP tHPC tCAS tCP tRSH tCAS tASC tCAH tASC VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH tCAH tASC ROW ADDRESS COLUMN-1 COLUMN-2 tCPRH tCAH ROW ADDRESS COLUMN-3 tRAL tRCS tCAL tASR tCAL tCAL tRRH tRCH VIH W VIL tWEZ tDZC DQ1~DQ4 (INPUTS) tRDD tCDD VIH Hi-Z tCAC tAA VIL tDOH tCLZ VOH DQ1~DQ4 (OUTPUTS) VOL Hi-Z DATA VALID-1 tRAC tDZO tCAC tAA tCAC tAA tCPA tDOH DATA VALID-2 tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEA tOCH tOEZ VIH OE VIL tODD MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hyper Page Mode Early Write Cycle tRAS tRP VIH RAS VIL tCSH tCAS tRCD tCRP tRSH tCAS tCP tHPC tCAS tCP tASC tCAL tCAH tASC tCRP VIH CAS VIL tASR A0~A9 VIH VIL tRAH ROW ADDRESS tASC tCAH COLUMN-1 tWCS tWCH COLUMN-2 tWCS tWCH tCAL tCAH COLUMN-3 tWCS tWCH VIH W VIL tDS DQ1~DQ4 (INPUTS) VIH VIL VOH DQ1~DQ4 (OUTPUTS) VOL OE VIH VIL tDH DATA VALID-1 tDS tDH DATA VALID-2 Hi-Z tDS tDH DATA VALID-3 tASR ROW ADDRESS MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hyper Page Mode Read-Write, Read-Modify-Write Cycle tRAS RAS tRP VIH VIL tRWL tCSH tCRP tRCD tCRP tHPRWC tCAS tCAS tCP VIH CAS VIL tASR A0~A9 VIH VIL tRAD tRAH ROW ADDRESS tASC tCAH tASC COLUMN-1 tASR ROW ADDRESS COLUMN-2 tAWD tAWD tRCS tCWL tCAH tCWL tCWD tCWD tRCS tWP tWP VIH W VIL tCPWD tRWD tDZC DQ1~DQ4 (INPUTS) VIH tDS Hi-Z VIL tDH tDZC tDS Hi-Z DATA VALID-1 tCAC tAA tCLZ DQ1~DQ4 (OUTPUTS) VOL tCLZ Hi-Z Hi-Z DATA VALID-1 tRAC tDZO tODD tOEA VIH VIL Hi-Z DATA VALID-2 tCPA tODD tDZO tOEH tOEZ OE DATA VALID-2 tCAC tAA VOH tDH tOEZ tOEA MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hyper Page Mode Mix Cycle (1) tRP tRAS tRWL VIH RAS VIL tCRP tCSH tCRP tRCD tCAS tHPC tCAS tCP tHPRWC tCAS tCP tCWL VIH CAS VIL tRAD tASR A0~A9 VIH VIL tRAH ROW ADDRESS tASC tCAH tASC tASC COLUMN-2 COLUMN-1 tRCS tASR tCAH ROW ADDRESS COLUMN-3 tCPWD tAWD tCWD tWCH tWCS tCAL tCAL W tCAH tWP VIH VIL tDZC DQ1~DQ4 (INPUTS) VIH tDZC DATA VALID-2 tCAC VIL tDH tDS tCAC tWEZ tCLZ Hi-Z tCLZ DATA VALID-3 DATA VALID-1 tRAC tDZO tDH DATA VALID-3 tAA tAA VOH DQ1~DQ4 (OUTPUTS) VOL tDS tCPA tOEA tOCH tOEZ tDZO tOEA tOEZ VIH OE VIL tODD tODD tOEH MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hyper Page Mode Mix Cycle (2) VIH RAS VIL VIH CAS VIL tCP tASC A0~A9 tCAS tCAH tCAS tCAH tASC tASC tCAH VIH COLUMN-1 COLUMN-2 COLUMN-3 VIL tRCH tCAL tCAL tWCS W tHCWD VIL tHAWD tDH tDS tHPWD DQ1~DQ4 (INPUTS) VIH Hi-Z VIL tAA tCPA tWEZ tCLZ VOH DQ1~DQ4 (OUTPUTS) VOL DATA VALID-1 tHCOD tHAOD tHPOD VIL Hi-Z tCAC tCAC tCPA VIH tDZC DATA VALID-2 tAA OE tWCH VIH Hi-Z DATA VALID-3 tDZC tOEZ tODD tOEA MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by OE ) tRAS tRP VIH RAS VIL tCSH tRSH tCAS tHPC tCAS tRCD tCRP tCAS tCP tCP tCRP VIH CAS VIL tRAD tASR A0~A9 VIH VIL tRAH tASC ROW ADDRESS tASC tCAH COLUMN-1 tCPRH tCAH tASC tCAH COLUMN-2 tASR ROW ADDRESS COLUMN-3 tRAL tRRH tRCS tRCH VIH W VIL tWEZ tDZC DQ1~DQ4 (INPUTS) tRDD tCDD VIH Hi-Z tCAC tCAC VIL tAA tCLZ VOH DQ1~DQ4 (OUTPUTS) VOL VIH Hi-Z DATA VALID-1 tRAC tDZO tOEA tAA tCAC tAA tDOH tCLZ DATA VALID-1 DATA VALID-2 DATA VALID-3 tCPA tCPA tOEZ Hi-Z tREZ tOHR tOFF tOHC tCHOL tOCH tOEA tOEZ tOEZ OE VIL tOEPE tOEPE tODD MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by W ) tRAS tRP VIH RAS VIL tCSH tRCD tCRP tCAS tHPC tCAS tCP tRSH tCAS tCP tCRP VIH CAS VIL tRAD tASR A0~A9 VIH VIL tRAH tCAH tASC ROW ADDRESS COLUMN-1 tASC tCPRH tCAH tASC tCAH COLUMN-2 tRCH tRCS W ROW ADDRESS COLUMN-3 tRAL tRCS tASR tRRH tRCH VIH VIL tWEZ tWPE tDZC DQ1~DQ4 (INPUTS) tRDD tCDD VIH Hi-Z VIL VOH DQ1~DQ4 (OUTPUTS) VOL tCAC tCAC tAA tAA tCLZ tDOH Hi-Z DATA VALID-1 tRAC tDZO tCLZ tWEZ DATA VALID-2 tCPA tOEA tOCH tCAC tAA Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 tCPA tOEZ VIH OE VIL tODD MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM RAS-only Refresh Cycle tRC tRAS RAS tRP VIH VIL tRPC tCRP tCRP VIH CAS VIL tASR A0~A9 VIH VIL W tRAH tASR ROW ADDRESS ROW ADDRESS VIH VIL DQ1~DQ4 (INPUTS) VIH VIL VOH DQ1~DQ4 (OUTPUTS) VOL OE VIH VIL Hi-Z MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM CAS before RAS Refresh Cycle, Extended Refresh Cycle* tRC RAS tRC tRAS tRP tRP tRAS VIH VIL tRPC tCSR CAS tCHR tRPC tCSR tCRP tRPC tCHR VIH VIL tCPN tASR A0~A9 VIH ROW ADDRESS VIL COLUMN ADDRESS tRRH tRCH tRSR W tRHR tRSR tRCS tRHR VIH VIL DQ1~DQ4 (INPUTS) VIH VIL tREZ tOHR tOFF tOHC VOH DQ1~DQ4 (OUTPUTS) VOL Hi-Z tOEZ OE VIH VIL MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 33) tRC tRAS tRC tRP tRAS tRP VIH RAS VIL tCRP tRCD tRSH tCHR VIH CAS VIL tRAD tASR VIH A0~A9 VIL tRAH tASC tASR tCAH COLUMN ADDRESS ROW ADDRESS tRCS ROW ADDRESS tRRH tRAL tRCH VIH W VIL tCDD tDZC tRDD DQ1~DQ4 (INPUTS) VIH Hi-Z tREZ VIL tCAC tAA tOHR tOFF tCLZ VOH DQ1~DQ4 (OUTPUTS) VOL tOHC Hi-Z Hi-Z DATA VALID tRAC tDZO tOEA tORH VIH OE VIL Note 33: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. tOEZ tODD MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Self Refresh Cycle* (Note 30) tRP tRASS tRPS VIH RAS VIL tRPC tCRP tRPC tCSR tCHS VIH CAS VIL tCPN tASR A0~A9 VIH ROW ADDRESS VIL tRRH tRCH W tRSR tRHR tRCS VIH VIL tRDD tCDD DQ1~DQ4 (INPUTS) VIH Hi-Z VIL tREZ tOHR tOFF tOHC DQ1~DQ4 VOH (OUTPUTS) VOL Hi-Z tOEZ tODD VIH OE VIL MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Test Mode Set Cycle (Note 34) tRC tRP RAS tRAS tRP VIH VIL tRPC CAS tCSR tRPC tCHR tCRP VIH VIL tCPN tASR VIH A0~A9 ROW ADDRESS VIL tRCH tWSR tWHR COLUMN ADDRESS tRCS VIH W DQ1~DQ4 (INPUTS) VIL VIH VIL tOFF DQ1~DQ4 VOH (OUTPUTS) VOL Hi-Z tOEZ VIH OE VIL Note 34: The cycle is also avaiilable for initialization cycle, but in this case device enters test mode. The test mode function is initiated with a W and CAS before RAS cycle(WCBR cycle) as specified above timing diagram. The test mode function is terminated by either a CAS before RAS(CBR) refresh or a RAS only refresh cycle. During the test mode, the device is internally organized as 4-bits wide (256 kilobytes deep) for each DQ (input / output) port. No addressing of A0, A1(column only) is required. During a write cycle, data on the each DQ (input) pin is written in parallel into all 4-bits for each DQ port and can be written independently for each DQ port. During a read cycle, the each DQ (output) pin indicates independently a HIGH state if all 4-bits are equal, and a LOW state if any bits differ. During the test mode operation, a WCBR cycle is used to perform refresh. MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM Note 30 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width(tRASS) of RAS signal during self refresh period. 1. Distributed refresh during Read / Write operation (A) Timing Diagram Read / Write Cycle Self Refresh Cycle tRASS≥100µs tNSD Read / Write Cycle tSND RAS first refresh cycle last refresh Cycle Table 2 Read / Write Cycle Read / Write Self Refresh Self Refresh Read / Write CBR distributed refresh tNSD≤125µs tSND≤125µs RAS only distributed refresh tNSD≤16µs tSND≤16µs (B) Definition of distributed refresh tREF tREF/1024 tREF/1024 RAS refresh cycle read/write cycles refresh cycle refresh cycle read/write cycles Definition of CBR distributed refresh (Including extended refresh) The CBR distributed refresh performs more than 1024 constant period(125µs max.) CBR cycles within 128 ms. Definition of RAS only distributed refresh All combinations of nine row address signals (A0~A9) are selected during 1024 constant period(16µs max.) RAS only refresh cycles within 16.4 ms. Note: Hidden refresh may be used instead of CBR refresh. RAS/CAS refresh may be used instead of RAS only refresh. 1.1 CBR distributed refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSD (shown in table 2). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within tSND(shown in table 2). 1.2 RAS only distributed refresh Switching from read/write operation to self refresh operation. The time interval tNSD from the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16µs. Switching from self refresh operation to read/write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16µs. MITSUBISHI LSIs M5M4V4405CJ,TP-6,-7,-6S,-7S EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM 2. Burst refresh during Read/Write operation (A) Timing diagram Read / Write Self Refresh tRASS≥100µs tNSB Read / Write tSNB RAS first refresh cycles refresh cycles 1024 cycles refresh cycles 1024 cycles last refresh Cycles Table 3 Read / Write Cycle CBR burst refresh Read / Write Self Refresh Self Refresh Read / Write tNSB≤16.4ms tSNB≤16.4ms RAS only burst refresh tNSB+tSNB≤16.4ms (B) Definition of burst refresh 16.4ms RAS refresh cycles 1024cycles read/write cycles Definition of CBR burst refresh The CBR burst refresh performs more than 1024 continuous CBR cycles within 16.4 ms. Definition of RAS only burst refresh All combination of nine row address signals (A0 ~A9) are selected during 1024 continuous RAS only refresh cycles within 16.4 ms. 2.1 CBR burst refresh Switching from read/write operation to self refresh operation. The time interval ns from the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16.4 ms. Switching from self refresh operation to read/write operation. The time interval snob from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period should be set within 16.4 ms. 2.2 RAS only burst refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB(Shown in table 3). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within tSNB(shown in table 3).