CD74ACT05-Q1 HEX INVERTER WITH OPEN-DRAIN OUTPUTS SCHS350A − JANUARY 2004 − REVISED JANUARY 2008 D Qualified for Automotive Applications D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With D D D M PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y GND Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current − Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y description The CD74ACT05 contains six independent inverters. This device performs the Boolean function Y = A. The open-drain outputs require pullup resistors to perform correctly, and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. ORDERING INFORMATION† −40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA SOIC − M Tape and reel CD74ACT05QM96Q1 TOP-SIDE MARKING ACT05Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L Z logic diagram, each inverter (positive logic) A Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74ACT05-Q1 HEX INVERTER WITH OPEN-DRAIN OUTPUTS SCHS350A − JANUARY 2004 − REVISED JANUARY 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25°C −40°C TO 125°C MIN MAX MIN MAX 4.5 5.5 4.5 5.5 VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 0 VCC VO Output voltage 0 5.5 IOH High-level output current IOL ∆t/∆v 2 UNIT 2 0.8 V V 0.8 V 0 VCC V 0 5.5 V −24 −24 mA Low-level output current 24 24 mA Input transition rise or fall rate 10 10 ns/V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOL TEST CONDITIONS VI = VIH or VIL II VI = VCC or GND ICC VI = VCC or GND, ∆ICC VI = VCC − 2.1 V VCC 2 −40°C TO 125°C MIN MIN MAX IOL = 50 µA 4.5 V 0.1 IOL = 24 mA 4.5 V 0.36 IOL = 50 mA‡ 5.5 V IO = 0 UNIT MAX 0.1 0.5 V 1.65 5.5 V ±0.1 ±1 5.5 V 4 80 µA 2.4 3 mA 10 10 pF 4.5 V to 5.5 V Ci ‡ TA = 25°C µA Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 75-Ω transmission-line drive capability at 125°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74ACT05-Q1 HEX INVERTER WITH OPEN-DRAIN OUTPUTS SCHS350A − JANUARY 2004 − REVISED JANUARY 2008 ACT INPUT LOAD TABLE INPUT UNIT LOAD A 0.18 Unit load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). switching characteristics over recommended operating free-air VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A or B Y tPZL tPLZ temperature range, −40°C TO 125°C MIN MAX 2.3 9.3 2.7 10.8 UNIT ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance TYP UNIT 105 pF PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) R1 = 500 Ω S1 2 × VCC 3V 1.5 V Input 1.5 V 0V R2 = 500 Ω tPZL tPLZ ≈VCC 50% VCC Output LOAD CIRCUIT 20% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74ACT05QM96G4Q1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74ACT05QM96Q1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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