Exar MP7616JD 15 v cmos 16-bit multiplying digital-to-analog converter Datasheet

MP7616
15 V CMOS
16-Bit Multiplying
Digital-to-Analog Converter
FEATURES
•
•
•
•
•
•
•
•
•
Monolithic CMOS Construction
Full Four-Quadrant Multiplication
Excellent Stability Over Temperature and Time
TTL/5 V CMOS Compatible
Guaranteed Monotonic
Low Sensitivity to Output Amplifier Vos
Low Glitch Energy
Buffered Version: MP7626
5 V Version: MP7616B
rather than the standard binary-weighted sources. Each resistor contributes only 1/16 full scale output thus reducing the
matching accuracy requirement of the resistor and CMOS
switches from 0.0015% to 0.024%.
GENERAL DESCRIPTION
The MP7616 is a high density 16-bit CMOS multiplying Digital-to-Analog Converter. Silicon nitride passivation and untrimmed silicon chromium resistors have been combined to provide long term stability and reliability. Using the most significant
bit (MSB) segmentation technique, the MP7616 features 13-bit
(0.012%) differential and 12-bit (0.01%) integral linearity.
The decoding technique achieves an eightfold improvement
in differential linearity stability over temperature, an eightfold improvement in relative accuracy due to aging effects (long term
stability), a fourfold improvement in glitch amplitude, and a tenfold reduction in sensitivity to output amplifier offset voltage.
To achieve 13-bit linearity without laser trim, the MP7616 digitally decodes the four MSB’s into 15 equal current sources,
SIMPLIFIED BLOCK DIAGRAM
VDD
VREF
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
12-Bit
DAC
IOUT2
IOUT1
RFB
To Switches
To 12-Bit DAC
4 to 15 Decoder
1
MSB
4
16
LSB
5
Rev. 2.00
1
GND
MP7616
ORDERING INFORMATION
Package
Type
Temperature
Range
Part No.
INL
(LSB)
DNL
(LSB)
Gain Error
(% FSR)
Plastic Dip
–40 to +85°C
MP7616JN
+14
+16
+0.8
Plastic Dip
–40 to +85°C
MP7616KN
–40 to +85°C
+7
+8
+0.8
SOIC
MP7616JS
+14
+16
+0.8
SOIC
–40 to +85°C
MP7616KS
+7
+8
+0.8
MP7616JD
+14
+16
+0.8
Ceramic Dip
–40 to +85°C
Ceramic Dip
–40 to +85°C
MP7616KD
+7
+8
+0.8
Ceramic Dip
–55 to +125°C
MP7616TD*
+7
+8
+0.8
*Contact factory for non-compliant military processing
PIN CONFIGURATION
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
See Packaging Section for Package Dimensions
1
22
2
21
3
20
4
19
5
18
6
17
7
16
8
15
9
14
10
13
11
12
N/C
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 2
BIT 1 (MSB)
GND
IOUT2
IOUT1
RFB
VREF
VDD
BIT 16 (LSB)
BIT 15
BIT 14
22 Pin CDIP, PDIP (0.400”)
D22, N22
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
BIT 2
BIT 1 (MSB)
GND
IOUT2
IOUT1
RFB
VREF
VDD
BIT 16 (LSB)
BIT 15
BIT 14
N/C
24 Pin SOIC (Jedec, 0.300”)
S24
PIN OUT DEFINITIONS
DIP
1
2
3
4
5
6
7
8
9
10
11
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
NAME
N/C
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
DESCRIPTION
DIP
No Connection
Data Input Bit 3
Data Input Bit 4
Data Input Bit 5
Data Input Bit 6
Data Input Bit 7
Data Input Bit 8
Data Input Bit 9
Data Input Bit 10
Data Input Bit 11
Data Input Bit 12
Data Input Bit 13
12
13
14
15
16
17
18
19
20
21
22
Rev. 2.00
2
SOIC
13
14
15
16
17
18
19
20
21
22
23
24
NAME
N/C
BIT 14
BIT 15
BIT 16
VDD
VREF
RFB
IOUT1
IOUT2
GND
BIT 1
BIT 2
DESCRIPTION
No Connection
Data Input Bit 14
Data Input Bit 15
Data Input Bit 16 (LSB)
Positive Power Supply
Reference Input Voltage
Internal Feedback Resistor
Current Output 1
Current Output 2
Ground
Data Input Bit 1 (MSB)
Data Input Bit 2
MP7616
ELECTRICAL CHARACTERISTICS
(VDD = + 15 V, VREF = +10 V unless otherwise noted)
Parameter
Symbol
Min
25°C
Typ
Max
Tmin to Tmax
Min
Max
Units
STATIC PERFORMANCE1
Resolution (All Grades)
Integral Non-Linearity5
(Relative Accuracy)
J
K, T
Differential Non-Linearity5
J
K, T
Test Conditions/Comments
FSR = Full Scale Range
N
16
16
Bits
INL
LSB
+14
+7
+14
+7
+16
+8
+16
+8
DNL
Best Fit Straight Line Spec.
(Max INL – Min INL) / 2
LSB
% FSR
Using Internal RFB
+2.0
ppm/°C
∆Gain/∆Temperature
Non-Linearity Tempco2
+0.5
ppm/°C
Differential Linearity Tempco2
+0.5
ppm/°C
ppm/%
Gain Error
Gain Temperature
GE
Coefficient2
+0.8
TCGE
PSRR
+5
+50
+50
IOUT
+1
+10
+200
Current Settling Time
tS
2
Feedthrough at IOUT1
FT
1
2
10
Power Supply Rejection Ratio
Output Leakage Current6
|∆Gain/∆VDD| ∆VDD = + 5%
nA
DYNAMIC PERFORMANCE2
µs
mV p-p
To 0.01% of FSR; all digital inputs
low to high and high to low
VREF = 10kHz, 20 Vp-p
REFERENCE INPUT
Input Resistance
RIN
1
3
VIH
VIL
3.0
2.4
1
10
kΩ
0.8
+1.0
V
V
µA
DIGITAL INPUTS3
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
3.0
0.8
+1.0
ILKG
ANALOG OUTPUTS2
Output Capacitance
100
50
50
100
COUT1
COUT1
COUT2
COUT2
pF
pF
pF
pF
DAC Inputs all 1’s
DAC Inputs all 0’s
DAC Inputs all 1’s
DAC Inputs all 0’s
V
mA
All digital inputs = 0 V or all = 5 V
POWER SUPPLY4
Functional Voltage Range2
Supply Current
VDD
IDD
4.5
15
0.4
16
4
Rev. 2.00
3
4.5
16
4
MP7616
ELECTRICAL CHARACTERISTICS (CONT’D)
NOTES:
1
Full Scale Range (FSR) is 10V for unipolar mode.
2
Guaranteed but not production tested.
3
Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
4
Specified values guarantee functionality. Refer to other parameters for accuracy.
5
Linearity error is degraded by 65µV for every mV of voltage offset at output amplifier.
6
Output leakage current refers to IOUT1. One LSB of current constantly flows into IOUT2 (30nA at 5kΩ input impedance,
VREF = +10 V) due to ladder termination into IOUT2.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C
Package Power Dissipation Rating to 75°C
CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . 1000mW
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 13mW/°C
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +17 V
Digital Input Voltage to GND . . . . GND –0.5 to VDD +0.5 V
IOUT1, IOUT2 to GND . . . . . . . . . . . GND –0.5 to VDD +0.5 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
APPLICATION NOTES
Refer to Section 8 for Applications Information
Rev. 2.00
4
MP7616
22 LEAD CERAMIC DUAL-IN-LINE
(400 MIL CDIP)
D22
S
S1
22
12
1
11
See
Note 1
E1
E
D
Q
Base
Plane
Seating
Plane
A
L
c
e
b
INCHES
SYMBOL
A
L1
b1
NOTES
MILLIMETERS
MIN
MAX
MIN
MAX
––
.225
––
5.72
NOTES
––
b
0.014
0.023
0.356
0.584
––
b1
0.038
0.065
0.965
1.65
2
c
0.008
0.015
0.203
0.381
––
D
––
1.111
––
28.22
4
E
0.350
0.410
8.89
10.41
4
E1
0.390
0.420
9.91
10.67
7
e
0.100 BSC
2.54 BSC
5
L
0.125
0.200
3.18
5.08
––
L1
0.150
––
3.81
––
––
Q
0.015
0.070
0.381
1.78
3
S
––
0.080
––
2.03
6
0.005
––
0.13
––
6
0°
15°
0°
15°
––
S1
α
α
Rev. 2.00
5
1. Index area; a notch or a lead one identification mark
is located adjacent to lead one and is within the
shaded area shown.
2. The minimum limit for dimension b1 may be 0.023
(0.58 mm) for all four corner leads only.
3. Dimension Q shall be measured from the seating
plane to the base plane.
4. This dimension allows for off-center lid, meniscus and
glass overrun.
5. The basic lead spacing is 0.100 inch (2.54 mm) between centerlines.
6. Applies to all four corners.
7. This is measured to outside of lead, not center.
MP7616
22 LEAD PLASTIC DUAL-IN-LINE
(400 MIL PDIP)
N22
S
22
12
1
11
E1
Q1
E
D
A1
Seating
Plane
A
L
B
e
B1
α
MILLIMETERS
INCHES
SYMBOL
A
MIN
MAX
MIN
––
0.225
––
MAX
5.72
A1
0.015
––
0.38
––
B
0.014
0.023
0.356
0.584
B1 (1)
0.038
0.065
0.965
1.65
C
0.008
0.015
0.203
0.381
D
1.050
1.110
26.67
28.19
E
0.385
0.425
9.78
10.80
E1
0.330
0.380
8.38
9.65
e
0.100 BSC
L
0.115
α
2.54 BSC
0.150
2.92
3.81
0°
15°
0°
15°
Q1
0.055
0.070
1.40
1.78
S
0.040
0.080
1.02
2.03
Note:
(1)
The minimum limit for dimensions B1 may be 0.023”
(0.58 mm) for all four corner leads only.
Rev. 2.00
6
C
MP7616
24 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
S24
D
24
13
E
H
12
h x 45°
C
A
Seating
Plane
α
B
e
A1
L
INCHES
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
A
0.097
0.104
2.464
2.642
A1
0.0050
0.0115
0.127
0.292
B
0.014
0.019
0.356
0.483
C
0.0091
0.0125
0.231
0.318
D
0.602
0.612
15.29
15.54
E
0.292
0.299
7.42
7.59
e
0.050 BSC
1.27 BSC
H
0.400
0.410
10.16
10.41
h
0.010
0.016
0.254
0.406
L
0.016
0.035
0.406
0.889
α
0°
8°
0°
8°
Rev. 2.00
7
MP7616
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00
8
Similar pages