LMV116, LMV118 www.ti.com SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 LMV116/LMV118 Low Voltage, 45MHz, Rail-to-Rail Output Operational Amplifiers with Shutdown Option Check for Samples: LMV116, LMV118 FEATURES DESCRIPTION 1 • 2 • • • • • • • • • • • The LMV116 (single) rail-to-rail output voltage feedback amplifiers offer high speed (45MHz), and low voltage operation (2.7V) in addition to micropower shutdown capability (LMV118). + (VS = 2.7V, TA = 25°C, RL = 1kΩ to V /2, AV = +1. Typical Values Unless Specified). −3dB BW 45MHz Supply Voltage Range 2.7V to 12V Slew Rate 40V/μs Supply Current 600μA Power Down Supply Current 15μA Output Short Circuit Current 32mA Linear Output Current ±20mA Input Common Mode Voltage −0.3V to 1.7V Output Voltage Swing 20mV from Rails Input Voltage Noise 40nV/√Hz Input Current Noise 0.75pA/√Hz Output voltage range extends to within 20mV of either supply rail, allowing wide dynamic range especially in low voltage applications. Even with low supply current of 600μA, output current capability is kept at a respectable ±20mA for driving heavier loads. Important device parameters such as BW, Slew Rate and output current are kept relatively independent of the operating supply voltage by a combination of process enhancements and design architecture. For portable applications, the LMV118 provides shutdown capability while keeping the turn-off current to l5μA. Both turn-on and turn-off characteristics are well behaved with minimal output fluctuations during transitions. This allows the part to be used in power saving mode, as well as multiplexing applications. Miniature packages (SOT-23-5 & SOT-23-6) are further means to ease the adoption of these low power high speed devices in applications where board area is at a premium. APPLICATIONS • • • • • • High Speed Clock Buffer/Driver Active Filters High Speed Portable Devices Multiplexing Applications (LMV118) Current Sense Amplifier High Speed Transducer Amplifier Typical Application 2.7V 100k: 15.36MHz SINE WAVE R1 + LMV116/ LMV118 C1 0.1PF 47k: OUTPUT - R2 Figure 1. Non-Inverting Clock Buffer Amplifier 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated LMV116, LMV118 SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) Human Body Machine Model 2KV (3) 200V (4) VIN Differential ±2.5V Output Short Circuit Duration See − + Supply Voltage (V - V ) V+ +0.8V, V− −0.8V −65°C to +150°C Storage Temperature Range (7) +150°C Soldering Information (1) (2) (3) (4) (5) (6) (7) Infrared or Convection (20 sec) 235°C Wave Soldering Lead Temp. (10 sec) 260°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Human body model, 1.5kΩ in series with 100pF. Machine Model, 0Ω in series with 200pF. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output short circuit duration is infinite for VS < 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board. Operating Ratings (1) − + Supply Voltage (V – V ) Temperature Range (2) 2 2.5V to 12V (2) Package Thermal Resistance (1) , 12.6V Voltage at Input/Output pins Junction Temperature (5) (6) −40°C to +85°C (2) (θJA) SOT-23-5 265°C/W SOT-23-6 265°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 LMV116, LMV118 www.ti.com SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 2.7V Electrical Characteristics Unless otherwise specified, all limits specified for at TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2, and RF = 2kΩ, and RL = 1kΩ to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions VOS Input Offset Voltage 0V ≤ VCM ≤ 1.7V TC VOS Input Offset Average Drift See (3) IB Input Bias Current See (4) IOS Input Offset Current CMRR Common Mode Rejection Ratio PSRR Power Supply Rejection Ratio RIN CIN CMVR Input Common-Mode Voltage Range CMRR ≥ 50dB AVOL Large Signal Voltage Gain VO = 0.35V to 2.35V VO Min (1) (2) ±1 Max (1) Units ±5 ±6 mV ±5 μV/C −2.0 −2.2 −0.40 μA VCM Stepped from 0V to 1.55V 73 88 dB V+ = 2.7V to 3.7V or V− = 0V to −1V 72 85 dB Common Mode Input Resistance 3 MΩ Common Mode Input Capacitance 2 Output Swing High 1 −0.3 −0.1 + RL = 1kΩ to V /2 87 2.55 2.66 RL = 10kΩ to V /2 Output Swing Low RL = 1kΩ to V+/2 150 pF V dB V 40 mV 20 Sourcing to V− VID = 200mV (5) 25 35 Sinking to V+ VID = −200mV 25 32 (5) nA 2.68 RL = 10kΩ to V+/2 Output Short Circuit Current 500 1.7 73 70 + ISC Typ mA IOUT Output Current VOUT = 0.5V from rails ±20 IS Supply Current Normal Operation 600 900 Shut-down Mode (LMV118) 15 50 AV = +1, VO = 1VPP 40 V/μs MHz (6) SR Slew Rate BW −3dB BW AV = +1, VOUT = 200mVPP 45 en Input -Referred Voltage Noise f = 100kHz 40 f = 1kHz 60 in Input-Referred Current Noise f = 100kHz 0.75 f = 1kHz 1.20 ton Turn-on Time (LMV118) toff Turn-off Time (LMV118) THSD Shut-down Threshold (LMV118) IS ≤ 50μA ISD Shutdown Pin Input Current (LMV118) See (1) (2) (3) (4) (5) (6) mA nV/√Hz pA/√Hz 250 ns 560 (4) 1.95 μA ns 2.3 −20 V μA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Short circuit test is a momentary test. See Absolute Maximum Ratings, Note 6. Slew rate is the average of the rising and falling slew rates. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 3 LMV116, LMV118 SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 www.ti.com 5V Electrical Characteristics Unless otherwise specified, all limits specified for at TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, and RF = 2kΩ, and RL = 1kΩ to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (1) Typ (2) VOS Input Offset Voltage 0V ≤ VCM ≤1.7V TC VOS Input Offset Average Drift See (3) IB Input Bias Current See (4) IOS Input Offset Current CMRR Common Mode Rejection Ratio PSRR Power Supply Rejection Ratio RIN CIN CMVR Input Common-Mode Voltage Range CMRR ≥ 50dB AVOL Large Signal Voltage Gain VO = 1.5V to 3.5V 73 70 85 VO Output Swing High RL = 1kΩ to V+/2 4.80 4.95 ±1 (1) ±5 ±6 Units mV ±5 μV/C −2.0 −2.2 −0.40 μA VCM Stepped from 0V to 3.8V 77 85 dB V+ = 5V to 6V or V− = 0V to −1V 72 95 dB Common Mode Input Resistance 3 MΩ Common Mode Input Capacitance 2 1 −0.3 −0.1 + RL = 10kΩ to V /2 Output Swing Low RL = 1kΩ to V+/2 Output Short Circuit Current nA pF 4.0 200 V dB V 50 mV 20 Sourcing to V− VID = 200mV (5) 35 45 Sinking to V+ VID = −200mV 35 43 (5) 500 4.98 RL = 10kΩ to V+/2 ISC Max mA IOUT Output Current VOUT = 0.5V from rails ±20 IS Supply Current Normal Operation 600 900 Shut-down Mode (LMV118) 10 50 AV = +1, VO = 1VPP 40 V/μs MHz (6) SR Slew Rate BW −3dB BW AV = +1, VOUT = 200mVPP 45 en Input -Referred Voltage Noise f = 100kHz 40 f = 1kHz 60 in Input-Referred Current Noise f = 100kHz 0.75 f = 1kHz 1.20 ton Turn-on Time (LMV118) toff Turn-off Time (LMV118) THSD Shut-down Threshold (LMV118) IS ≤ 50μA ISD Shutdown Pin Input Current (LMV118) See (1) (2) (3) (4) (5) (6) 4 mA μA nV/√Hz pA/√Hz 210 ns 500 (4) 4.25 −20 ns 4.60 V μA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Short circuit test is a momentary test. See Absolute Maximum Ratings, Note 6. Slew rate is the average of the rising and falling slew rates. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 LMV116, LMV118 www.ti.com SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 ±5V Electrical Characteristics Unless otherwise specified, all limits specified for at TJ = 25°C, V+ = 5V, V− = −5V, VCM = VO = 0V, and RF = 2kΩ, and RL = 1kΩ to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (1) Typ (2) Max (1) Units VOS Input Offset Voltage −5V ≤ VCM ≤ 1.7V TC VOS Input Offset Average Drift See (3) IB Input Bias Current See (4) IOS Input Offset Current CMRR Common Mode Rejection Ratio PSRR Power Supply Rejection Ratio RIN CIN CMVR Input Common-Mode Voltage Range CMRR ≥ 50dB −5.3 −5.1 AVOL Large Signal Voltage Gain VO = −2V to 2V 74 71 85 dB VO Output Swing High RL = 1kΩ 4.70 4.92 V −4.70 −4.93 ±1 mV ±5 μV/C −2.0 −2.2 −0.40 μA VCM Stepped from −5V to 3.5V 78 104 dB V+ = 5V to 6V or V− = −5V to −6V 72 95 dB Common Mode Input Resistance 3 MΩ Common Mode Input Capacitance 2 3 nA pF V 4.97 RL = 1kΩ mV −4.98 RL = 10kΩ Output Short Circuit Current 500 4.0 RL = 10kΩ Output Swing Low ISC ±5 ±6 Sourcing to 0V VID = 200mV (5) 40 57 Sinking to 0V VID = −200mV 40 54 (5) mA IOUT Output Current VOUT = 0.5V from rails ±20 IS Supply Current Normal Operation 600 900 Shut-down Mode (LMV118) 15 50 AV = +1, VO = 1VPP 35 V/μs MHz (6) SR Slew Rate BW −3dB BW AV = +1, VOUT = 200mVPP 45 en Input -Referred Voltage Noise f = 100kHz 40 f = 1kHz 60 in Input-Referred Current Noise f = 100kHz 0.75 f = 1kHz 1.20 ton Turn-on Time (LMV118) toff Turn-off Time (LMV118) THSD Shut-down Threshold (LMV118) IS ≤ 50μA ISD Shutdown Pin Input Current (LMV118) See (1) (2) (3) (4) (5) (6) mA μA nV/√Hz pA/√Hz 200 ns 700 (4) 4.25 ns 4.60 −20 V μA All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Short circuit test is a momentary test. See Absolute Maximum Ratings, Note 6. Slew rate is the average of the rising and falling slew rates. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 5 LMV116, LMV118 SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 www.ti.com Connection Diagram 5 1 OUTPUT V + 6 1 OUTPUT 5 V - 2 V - 2 + + +IN + SD - - 3 4 Figure 2. SOT-23-5 (LMV116) Top View 6 V -IN +IN 3 4 -IN Figure 3. SOT-23-6 (LMV118) Top View Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 LMV116, LMV118 www.ti.com SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 Typical Performance Characteristics At TJ = 25°C. Unless otherwise specified. Supply Current vs. Supply Voltage Supply Current vs. VCM 1.4 0.9 85°C 1.2 SUPPLY CURRENT (mA) 0.8 0.7 IS (mA) 25°C 0.6 -40°C 0.5 0.4 1 85°C 0.8 25°C 0.6 0.4 -40°C 0.2 0 0.3 3 1 5 7 9 11 12 -6 -4 -2 VS (V) 2 Figure 4. Figure 5. Gain and Phase vs. Frequency CMRR vs. Frequency 70 90 60 80 4 6 VS = 5V PHASE 50 100 40 70 85°C 20 10 60 40 20 -40°C 0 PHASE (°) 85°C 30 CMRR (dB) 80 GAIN GAIN (dB) 0 VCM (V) 60 50 40 0 30 -40°C -20 VS = ±2.5V 20 RL = 2k 100k 1M 10M 10 1k 100M 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Figure 7. PSRR vs. Frequency Input Voltage Noise vs. Frequency 1000 110 100 90 +PSRR en (nV/ Hz) PSRR (dB) 80 70 60 50 -PSRR VOLTAGE 100 40 30 20 VS = ±5V 10 100 1k 10k 100k 1M 10M 10 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 7 LMV116, LMV118 SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) At TJ = 25°C. Unless otherwise specified. Input Current Noise vs. Frequency Closed Loop Frequency Response for Various Temperature 10.00 AV = +2 GAIN AV = +1 0 CURRENT 1.00 AV = +10 PHASE (°) GAIN (dB) in (pA/ Hz) -2 -4 0 PHASE 50 100 AV = +5 VS = ±5V RL = 1k: 0.10 10 1M 10M FREQUENCY (Hz) 100k 100 10k 1k 100k 200M FREQUENCY (Hz) Figure 10. Figure 11. Frequency Response for Various (AV) Large Signal Step Response GAIN 85°C 0 25°C -4 PHASE (°) GAIN (dB) -2 0 PHASE 50 AV = +1 100 VS = ±5V VS = ±2.5V -40°C RL = 1K RL = 1k: VOUT = 200mVPP VOUT = 1VPP 100k 100M 200M 10M 1M 40 ns/DIV 0.2 V/DIV FREQUENCY (Hz) Figure 12. Figure 13. Offset Voltage vs. Common Mode Voltage (A Typical Unit) Offset Voltage vs. Common Mode Voltage (A Typical Unit) 1.2 1.4 VS = 5V 85°C 25°C 1.3 1.1 1 VOS (mV) VOS (mV) 85°C 1.2 25°C -40°C 0.9 1.1 -40°C 1.0 0.9 0.8 0.8 0.7 VS = 2.7V 0.7 0.6 0 0.5 1 1.5 2 VCM (V) 1 2 3 4 5 VCM (V) Figure 14. 8 0 Figure 15. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 LMV116, LMV118 www.ti.com SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 Typical Performance Characteristics (continued) At TJ = 25°C. Unless otherwise specified. Offset Voltage vs. Common Mode Range (A Typical Unit) Input Bias Current vs. Supply Voltage -0.15 1.4 VS = ±5V 25°C 1.3 -0.17 INPUT BIAS CURRENT (PA) 85°C 1.2 VOS (mV) 1.1 -40°C 1 0.9 0.8 0.7 -0.19 -40°C -0.21 25°C -0.23 -0.25 85°C -0.27 -0.29 0.6 -0.31 0.5 -5 -3.5 -2 -0.5 1 2.5 4 0 2 6 8 Figure 16. Figure 17. Input Bias Current vs. VCM Sink Current vs. VOUT 10 12 35 -0.12 85°C -0.14 30 -0.16 -0.18 25 25°C -0.20 ISINK (mA) INPUT BIAS CURRENT (PA) 4 SUPPLY VOLTAGE (V) VCM (V) 85°C -0.22 -0.24 -0.26 20 25°C -40°C 15 10 -40°C -0.28 5 -0.30 0 -0.32 VS = 2.7V -5 -0.34 -5 -3 -1 1 3 5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VOUT (V) VCM (V) Figure 18. Figure 19. Sink Current vs. VOUT 45 85°C 40 35 30 -40°C ISINK (mA) 25°C 25 20 15 10 5 0 VS = 5V -5 -0.5 0 0.5 1 1.5 2 2.5 3 VOUT (V) Figure 20. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 9 LMV116, LMV118 SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) At TJ = 25°C. Unless otherwise specified. Souce Current vs. VOUT Souce Current vs. VOUT 50 40 85°C 85°C 45 35 40 30 ISOURCE (mA) ISOURCE (mA) 25°C 25 -40°C 20 15 10 35 25°C 30 -40°C 25 20 15 10 5 5 0 0 VS = 2.7V 0 10 VS = 5V -5 -5 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.5 1 1.5 VOUT (V) VOUT (V) Figure 21. Figure 22. Submit Documentation Feedback 2 2.5 3 Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 LMV116, LMV118 www.ti.com SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 APPLICATION NOTES CIRCUIT DESCRIPTION The LMV116 and LMV118 are based on TI’s proprietary VIP10 dielectrically isolated bipolar process. The LMV116 and LMV118 architecture features the following: • Complimentary bipolar devices with exceptionally high ft (∼8GHz) even under low supply voltage (2.7V) and low Collector bias current. • Common Emitter push-pull output stage capable of 20mA output current (at 0.5V from the supply rails) while consuming only 600μA of total supply current. This architecture allows output to reach within milli-volts of either supply rail at light loads. • Consistent performance from any supply voltage (2.7V-10V) with little variation with supply voltage for the most important specifications (e.g. BW, SR, IOUT, etc.) APPLICATION HINTS When the output swing approaches either supply rail, the output transistor will enter a Quasi-saturated state. A subtle effect of this operational region is that there is an increase in supply current in this state (up to 1 mA). The onset of Quasi-saturation region is a function of output loading (current) and varies from 100 mV at no load to about 1V when output is delivering 20 mA, as measured from supplies. Both input common mode voltage and output voltage level effect the supply current (see typical performance characteristics for plot). MICRO-POWER SHUTDOWN The LMV118 can be shutdown to save power and reduce its supply current to less than 50μA specified, by applying a voltage to the SD pin. The SD pin is “active high” and needs to be tied to V− for normal operation. This input is low current (<20μA, 4pF equivalent capacitance) and a resistor to V− (≤20kΩ) will result in normal operation. Shutdown is specified when SD pin is 0.4V or less from V+ at any operating supply voltage and temperature. In the shutdown mode, essentially all internal device biasing is turned off in order to minimize supply current flow and the output goes into Hi-Z (high impedance) mode. Complete device Turn-on and Turn-off times vary considerably relative to the output loading conditions, output voltage, and input impedance, but is generally limited to less than 1μs (see tables for actual data). During shutdown, the input stage has an equivalent circuit as shown below in Figure 23. INVERTING INPUT RS 200-400: D4 D1 D3 D2 NON-INVERTING INPUT Figure 23. As can be seen above, in shutdown, there may be current flow through the internal diodes shown, caused by input potential, if present. This current may flow through the external feedback resistor and result in an apparent output signal. In most shutdown applications the presence of this output is inconsequential. However, if the output is “forced” by another device such as in a multiplexer, the other device will need to conduct the current described in order to maintain the output potential. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 11 LMV116, LMV118 SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 www.ti.com To keep the output at or near ground during shutdown when there is no other device to hold the output low, a switch (transistor) could be used to shunt the output to ground. Figure 24 shows a circuit where a NPN bipolar is used to keep the output near ground (∼80mV): 5V - VOUT LMV118 VIN + SD V - SHUTDOWN INPUT Q1 RS 10k Figure 24. Active Pull-Down Schematic Figure 25 shows the output waveform. VOUT VS = 5V AV = +1 VIN = 3.5VPP SD 2 V/DIV 2.00 µs/DIV Figure 25. Output Held Low by Active Pull-Down Circuit If bipolar transistor power dissipation is not tolerable, the switch could be by a N-channel enhancement mode MOSFET. 2.7V SINGLE SUPPLY 2:1 MUX The schematic show in Figure 26 will function as a 2:1 MUX operating on a single 2.7V power supply, by utilizing the shutdown feature of the LMV118. 12 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 LMV116, LMV118 www.ti.com SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 1/5 74HC04 1/5 74HC04 SELECT INPUT 2k 2k 2.7V SHUTDOWN LMV118 + INPUT A RL 2.7V SHUTDOWN + INPUT B LMV118 - 2k 2k Figure 26. 2:1 MUX Operating off a 2.7V Single Supply Figure 27 shows the MUX output when selecting between a 1MHz sine and a 250kHz triangular waveform. VOUT SELECT 1 V/DIV 1 µs/DIV Figure 27. 2:1 MUX Output As can be seen in Figure 27, the output is well behaved and there are no spikes or glitches due to the switching. Switching times are approximately around 500ns based on the time when the output is considered “valid”. PRINTED CIRCUIT BOARD LAYOUT, COMPONENT VALUES SELECTION, AND EVALUATION BOARDS Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15 (SNOA367) for more information). Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 13 LMV116, LMV118 SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 www.ti.com Another important parameter, is the component values selection. Choosing large valued external resistors, will effect the closed loop behavior of the stage because of the interaction of these resistors with parasitic capacitances. These capacitors could be inherent to the device or a by-product of the board layout and component placement. Either way, keeping the resistor values lower, will diminish this interaction. On the other hand, choosing very low value resistors could load down nodes and will contribute to higher overall power dissipation. TI suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization: Device Package Evaluation Board PN LMV116 SOT-23-5 CLC730068 LMV118 SOT-23-6 CLC730116 These free evaluation boards are shipped when a device sample request is placed with TI. 14 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 LMV116, LMV118 www.ti.com SNOSA87B – OCTOBER 2003 – REVISED MAY 2013 REVISION HISTORY Changes from Revision A (May 2013) to Revision B • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LMV116 LMV118 15 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMV116MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AC1A LMV116MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AC1A LMV118MF NRND SOT-23 DBV 6 TBD Call TI Call TI -40 to 85 AD1A LMV118MF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AD1A LMV118MFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 AD1A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMV116MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 LMV116MFX/NOPB SOT-23 DBV 5 3000 178.0 LMV118MF/NOPB SOT-23 DBV 6 1000 178.0 LMV118MFX/NOPB SOT-23 DBV 6 3000 178.0 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV116MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV116MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV118MF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 LMV118MFX/NOPB SOT-23 DBV 6 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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