M48Z02 M48Z12 5 V, 16 Kbit (2 Kb x 8) ZEROPOWER® SRAM Features ■ Integrated, ultra low power SRAM and powerfail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages (VPFD = Power-fail deselect voltage): – M48Z02: VCC= 4.75 to 5.5 V; 4.5 V ≤ VPFD ≤ 4.75 V – M48Z12: VCC= 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V ■ 24 1 Self-contained battery in the CAPHAT™ DIP package ■ Pin and function compatible with JEDEC standard 2 K x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect May 2010 Doc ID 2420 Rev 7 PCDIP24 (PC) Battery CAPHAT™ 1/21 www.st.com 1 Contents M48Z02, M48Z12 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 Doc ID 2420 Rev 7 M48Z02, M48Z12 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data . . . . . . . . . 17 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Doc ID 2420 Rev 7 3/21 List of figures M48Z02, M48Z12 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. 4/21 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write enable controlled, write AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip enable controlled, write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Checking the BOK flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline . . . . . . . . . . . . . . . . . 17 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 2420 Rev 7 M48Z02, M48Z12 1 Description Description The M48Z02/12 ZEROPOWER® RAM is a 2 K x 8 non-volatile static RAM which is pin and function compatible with the DS1220. A special 24-pin, 600 mil DIP CAPHAT™ package houses the M48Z02/12 silicon with a long-life lithium button cell to form a highly integrated battery-backed memory solution. The M48Z02/12 button cell has sufficient capacity and storage life to maintain data functionality for an accumulated time period of at least 10 years in the absence of power over commercial operating temperature range. The M48Z02/12 is a non-volatile pin and function equivalent to any JEDEC standard 2 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Figure 1. Logic diagram VCC 11 8 A0-A10 W DQ0-DQ7 M48Z02 M48Z12 E G VSS AI01186 Table 1. Signal names A0-A10 Address inputs DQ0-DQ7 Data inputs / outputs E Chip enable G Output enable W WRITE enable VCC Supply voltage VSS Ground Doc ID 2420 Rev 7 5/21 Description Figure 2. M48Z02, M48Z12 DIP connections A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 3. 24 1 23 2 22 3 4 21 20 5 6 M48Z02 19 M48Z12 18 7 17 8 16 9 15 10 11 14 12 13 VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI01187 Block diagram A0-A10 LITHIUM CELL POWER VOLTAGE SENSE AND SWITCHING CIRCUITRY 2K x 8 SRAM ARRAY DQ0-DQ7 E VPFD W G VCC 6/21 VSS Doc ID 2420 Rev 7 AI01255 M48Z02, M48Z12 2 Operation modes Operation modes The M48Z02/12 also has its own power-fail detect circuit. The control circuitry constantly monitors the single 5 V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3 V, the control circuitry connects the battery which maintains data operation until valid power returns. Table 2. Operating modes Mode VCC Deselect WRITE READ 4.75 to 5.5 V or 4.5 to 5.5 V READ Deselect VSO to VPFD Deselect ≤ VSO (min)(1) (1) E G W DQ0DQ7 Power VIH X X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High Z Active X X X High Z CMOS standby X X X High Z Battery backup mode 1. See Table 10 on page 16 for details. Note: X = VIH or VIL; VSO = battery backup switchover voltage. 2.1 Read mode The M48Z02/12 is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access time (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access. Doc ID 2420 Rev 7 7/21 Operation modes Figure 4. M48Z02, M48Z12 Read mode AC waveforms tAVAV VALID A0-A10 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI01330 Note: WRITE enable (W) = high. Table 3. Read mode AC characteristics M48Z02/M48Z12 Symbol Parameter(1) –70 Min –150 Max 70 Min Max 150 –200 Min Unit Max tAVAV READ cycle time 200 ns tAVQV Address valid to output valid 70 150 200 ns tELQV Chip enable low to output valid 70 150 200 ns tGLQV Output enable low to output valid 35 75 80 ns tELQX Chip enable low to output transition 5 10 10 ns tGLQX Output enable low to output transition 5 5 5 ns tEHQZ Chip enable high to output Hi-Z 25 35 40 ns tGHQZ Output enable high to output Hi-Z 25 35 40 ns tAXQX Address transition to output transition 10 5 5 ns 1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2.2 Write mode The M48Z02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. 8/21 Doc ID 2420 Rev 7 M48Z02, M48Z12 Figure 5. Operation modes Write enable controlled, write AC waveform tAVAV VALID A0-A10 tAVWH tAVEL tWHAX E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH Figure 6. AI01331 Chip enable controlled, write AC waveforms tAVAV A0-A10 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH Doc ID 2420 Rev 7 AI01332B 9/21 Operation modes Table 4. M48Z02, M48Z12 Write mode AC characteristics M48Z02/M48Z12 Symbol Parameter(1) –70 Min –150 Max Min Max –200 Min Unit Max tAVAV WRITE cycle time 70 150 200 ns tAVWL Address valid to WRITE enable low 0 0 0 ns tAVEL Address valid to chip enable 1 low 0 0 0 ns tWLWH WRITE enable pulse width 50 90 120 ns tELEH Chip enable low to chip enable 1 high 55 90 120 ns tWHAX WRITE enable high to address transition 0 10 10 ns tEHAX Chip enable high to address transition 0 10 10 ns tDVWH Input valid to WRITE enable high 30 40 60 ns tDVEH Input valid to chip enable high 30 40 60 ns tWHDX WRITE enable high to input transition 5 5 5 ns tEHDX Chip enable high to input transition 5 5 5 ns tWLQZ WRITE enable low to output Hi-Z tAVWH Address valid to WRITE enable high 60 120 140 ns tAVEH Address valid to chip enable high 60 120 140 ns tWHQX WRITE enable high to output transition 5 10 10 ns 25 50 60 ns 1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2.3 Data retention mode With valid VCC applied, the M48Z02/12 operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as “don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z02/12 may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. The power switching circuit connects external VCC to the RAM and disconnects the battery when VCC rises above VSO. As VCC rises, the battery voltage is checked. If the voltage is too low, an internal Battery Not OK (BOK) flag will be set. The BOK flag can be checked after power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 7 on page 11 illustrates how a BOK check routine could be structured. For more information on a battery storage life refer to the application note AN1012. 10/21 Doc ID 2420 Rev 7 M48Z02, M48Z12 Figure 7. Operation modes Checking the BOK flag status POWER-UP READ DATA AT ANY ADDRESS WRITE DATA COMPLEMENT BACK TO SAME ADDRESS READ DATA AT SAME ADDRESS AGAIN IS DATA COMPLEMENT OF FIRST READ? (BATTERY OK) YES NO (BATTERY LOW) NOTIFY SYSTEM OF LOW BATTERY (DATA MAY BE CORRUPTED) WRITE ORIGINAL DATA BACK TO SAME ADDRESS CONTINUE AI00607 Doc ID 2420 Rev 7 11/21 Operation modes 2.4 M48Z02, M48Z12 VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 8. Supply voltage protection VCC VCC 0.1µF DEVICE VSS AI02169 12/21 Doc ID 2420 Rev 7 M48Z02, M48Z12 3 Maximum ratings Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol TA TSTG TSLD(1) Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Grade 1 Value Unit 0 to 70 °C –40 to 85 °C 260 °C VIO Input or output voltages –0.3 to 7 V VCC Supply voltage –0.3 to 7 V IO Output current 20 mA PD Power dissipation 1 W 1. Soldering temperature of the IC leads is to not exceed 260°C for 10 seconds. In order to protect the lithium battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 °C. Furthermore, the devices shall not be exposed to IR reflow. Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode. Doc ID 2420 Rev 7 13/21 DC and AC parameters 4 M48Z02, M48Z12 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in Table 6: Operating and AC measurement conditions. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions Parameter Supply voltage (VCC) Ambient operating temperature (TA) M48Z02 M48Z12 Unit 4.75 to 5.5 4.5 to 5.5 V 0 to 70 0 to 70 °C Load capacitance (CL) Grade 1 100 100 pF Input rise and fall times ≤5 ≤5 ns 0 to 3 0 to 3 V 1.5 1.5 V Input pulse voltages Input and output timing ref. voltages Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC testing load circuit 5V 1.8kΩ DEVICE UNDER TEST OUT 1kΩ CL = 100pF CL includes JIG capacitance Table 7. Capacitance Parameter(1)(2) Symbol CIN CIO (3) AI01019 Min Max Unit Input capacitance - 10 pF Input / output capacitance - 10 pF 1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested. 2. At 25°C, f = 1 MHz. 3. Outputs deselected. 14/21 Doc ID 2420 Rev 7 M48Z02, M48Z12 Table 8. DC and AC parameters DC characteristics Symbol ILI ILO (2) Test condition(1) Parameter Input leakage current Output leakage current Min Max Unit 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA Outputs open 80 mA E = VIH 3 mA E = VCC – 0.2 V 3 mA ICC Supply current ICC1 Supply current (standby) TTL ICC2 Supply current (standby) CMOS VIL Input low voltage –0.3 0.8 V VIH Input high voltage 2.2 VCC + 0.3 V VOL Output low voltage IOL = 2.1 mA 0.4 V VOH Output high voltage IOH = –1 mA 2.4 V 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. Outputs deselected. Figure 10. Power down/up mode AC waveforms VCC VPFD (max) VPFD (min) VSO tF tPD INPUTS tDR tR tFB RECOGNIZED tRB DON'T CARE tREC NOTE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI00606 Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system is running. Doc ID 2420 Rev 7 15/21 DC and AC parameters Table 9. M48Z02, M48Z12 Power down/up AC characteristics Parameter(1) Symbol Min Max Unit tPD E or W at VIH before power down 0 - µs tF(2) VPFD (max) to VPFD (min) VCC fall time 300 - µs tFB(3) VPFD (min) to VSS VCC fall time 10 - µs tR VPFD (min) to VPFD (max) VCC rise time 0 - µs tRB VSS to VPFD (min) VCC rise time 1 - µs tREC E or W at VIH after power up 2 - ms 1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 10. Power down/up trip points DC characteristics Parameter(1)(2) Symbol VPFD Power-fail deselect voltage VSO Battery backup switchover voltage tDR (3) Min Typ Max Unit M48Z02 4.5 4.6 4.75 V M48Z12 4.2 4.3 4.5 V Expected data retention time 3.0 10 V YEARS 1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted). 3. At 25 °C, VCC = 0 V. 16/21 Doc ID 2420 Rev 7 M48Z02, M48Z12 5 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package outline A2 A1 B1 B A L C e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 11. PCDIP24 – 24-pin plastic DIP, battery CAPHAT™, package mechanical data mm inches Symb Typ Min Max A 8.89 A1 Min Max 9.65 0.350 0.380 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 34.29 34.80 1.350 1.370 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 27.94 Typ 1.1 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 24 Doc ID 2420 Rev 7 24 17/21 Part numbering 6 M48Z02, M48Z12 Part numbering Table 12. Ordering information scheme Example: M48Z 02 –70 PC 1 Device type M48Z Supply voltage and write protect voltage 02 = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V 12 = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V Speed –70 = 70 ns (M48Z02/12) –150 = 150 ns (M48Z02/12) –200 = 200 ns (M48Z02/12) Package PC = PCDIP24 Temperature range 1 = 0 to 70°C Shipping method blank = ECOPACK® package, tubes For a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the ST sales office nearest you. 18/21 Doc ID 2420 Rev 7 M48Z02, M48Z12 7 Environmental information Environmental information Figure 12. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Please refer to the following web site address for additional information regarding compliance statements and waste recycling. Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics". Doc ID 2420 Rev 7 19/21 Revision history 8 Revision history Table 13. 20/21 M48Z02, M48Z12 Document revision history Date Revision Changes May-1999 1 First issue 09-Jul-2001 2 Reformatted; temperature information added to tables (Table 5, 6, 7, 8, 3, 4, 9, 10); Figure updated (Figure 10) 17-Dec-2001 2.1 Remove references to “clock” in document 20-May-2002 2.2 Updated VCC noise and negative going transients text 01-Apr-2003 3 22-Apr-2003 3.1 12-Dec-2005 4 Update template, Lead-free text, and remove references to ‘crystal’ and footnote (Table 8, 12) 02-Nov-2007 5 Reformatted document; added lead-free second level interconnect information to cover page and Section 5: Package mechanical data; updated Table 5, 6, 8, 9, 10, 12. 03-Dec-2008 6 Added Section 7: Environmental information; minor formatting changes. 27-May-2010 7 Updated Section 3, Table 11, text in Section 5; reformatted document. v2.2 template applied; test condition updated (Table 10) Fix error in ordering information (Table 12) Doc ID 2420 Rev 7 M48Z02, M48Z12 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 2420 Rev 7 21/21