EL5130, EL5131 ® Data Sheet June 6, 2006 300MHz Low Noise Amplifiers Features The EL5130 and EL5131 are ultra-low voltage noise, high speed voltage feedback amplifiers that are ideal for applications requiring low voltage noise, including communications and imaging. These devices offer extremely low power consumption for exceptional noise performance. Stable at gains as low as 5, these devices offer 100mA of drive performance. Not only do these devices find perfect application in high gain applications, they maintain their performance down to lower gain settings. • 300MHz -3dB bandwidth These amplifiers are available in small package options (SOT-23) as well as the industry-standard SO packages. All parts are specified for operation over the -40°C to +85°C temperature range. Ordering Information PART PART NUMBER MARKING FN7381.3 • Ultra low noise = 1.8nV/√Hz • 350V/µs slew rate • Low supply current = 4mA • Single supplies from 5V to 12V • Dual supplies from ±2.5V to ±6V • Fast disable on the EL5130 • Low cost • Pb-free plus anneal available (RoHS compliant) Applications • Imaging TAPE & REEL PACKAGE PKG. DWG. # EL5130IS 5130IS - 8 Ld SO MDP0027 EL5130ISZ (See Note) 5130ISZ - 8 Ld SO (Pb-free) MDP0027 EL5130IS-T7 5130IS 7” 8 Ld SO MDP0027 EL5130ISZ-T7 (See Note) 5130ISZ 7” 8 Ld SO (Pb-free) MDP0027 EL5130IS-T13 5130IS 13” 8 Ld SO MDP0027 EL5130ISZ-T13 (See Note) 5130ISZ 13” 8 Ld SO (Pb-free) MDP0027 EL5131IW-T7 BBAA 7” (3k pcs) 5 Ld SOT-23 MDP0038 EL5131IWZ-T7 (See Note) BRAA 7” (3k pcs) 5 Ld SOT-23 MDP0038 (Pb-free) EL5131IW-T7A BBAA 7” 5 Ld SOT-23 MDP0038 (250 pcs) EL5131IWZ-T7A BRAA (See Note) 7” 5 Ld SOT-23 MDP0038 (250 pcs) (Pb-free) • Instrumentation • Communications devices Pinouts EL5130 (8 LD SO) TOP VIEW NC 1 IN- 2 IN+ 3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 8 CE + VS- 4 7 VS+ 6 OUT 5 NC EL5131 (5 LD SOT-23) TOP VIEW OUT 1 VS- 2 IN+ 3 5 VS+ + 4 IN- CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5130, EL5131 Absolute Maximum Ratings (TA = 25°C) Slewrate between VS+ and VS-. . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . 13.2V IIN-, IIN+, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mA Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 500Ω, RG = 50Ω, CL = 5pF, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT -0.9 0.2 0.9 mV VOS Offset Voltage TCVOS Offset Voltage Temperature Coefficient Measured from TMIN to TMAX IB Input Bias Current VIN = 0V 1.5 2.27 3.3 µA IOS Input Offset Current VIN = 0V -500 100 500 nA TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX PSRR Power Supply Rejection Ratio VS = ±4.75V to ±5.25V CMRR Common Mode Rejection Ratio CMIR 0.8 µV/°C -3 nA/°C 75 90 dB VIN = ±3.0V 95 110 dB Common Mode Input Range Guaranteed by CMRR test ±3 ±3.3 V RIN Input Resistance Common mode 5 20 MΩ CIN Input Capacitance 1 pF IS Supply Current AVOL Open Loop Gain VO Output Voltage Swing 3.0 3.54 4.1 mA VOUT = ±2.5V, RL = 1kΩ to GND 10 16 kV/V RL = 1kΩ, RF = 900Ω, RG = 100Ω ±3.5 ±3.8 V RL = 150Ω ±3.5 ±3.3 V 50 100 mA ISC Short Circuit Current RL = 10Ω BW -3dB Bandwidth AV = +5, RL = 500Ω 300 MHz BW ±0.1dB Bandwidth AV = +5, RL = 500Ω 60 MHz GBWP Gain Bandwidth Product 1500 MHz PM Phase Margin RL = 1kΩ, CL = 6pF 55 ° SR Slew Rate VS = ±5V, RL = 150Ω, VOUT = ±2.5V 350 V/µs tR, tF Rise Time, Fall Time ±0.1VSTEP TBD ns tPD Propagation Delay ±0.1VSTEP TBD ns tS 0.01% Settling Time 14 ns dG Differential Gain AV = +2, RF = 1kΩ 0.01 % dP Differential Phase AV = +2, RF = 1kΩ 0.01 ° eN Input Noise Voltage f = 10kHz 1.8 nV/√Hz iN Input Noise Current f = 10kHz 1.1 pA/√Hz 2 225 FN7381.3 June 6, 2006 EL5130, EL5131 Typical Performance Curves 0 50 144 216 30 288 10 -10 1k PHASE 10k 100k 1M 10M NORMALIZED GAIN (dB) 72 PHASE (°) MAGNITUDE (dB) 70 300 5 VS=±5V 360 100M 500M 180 3 1 -60 -1 VS=±5V AV=-5 -3 RG=50Ω RL=500Ω CL=5pF -5 0.1 1 FREQUENCY (Hz) -300 1k 100 5 180 GAIN 60 -60 -1 PHASE -180 NORMALIZED GAIN (dB) VS=±5V AV=+5 3 RG=50Ω RL=500Ω CL=5pF PHASE (°) NORMALIZED GAIN (dB) 10 FIGURE 2. GAIN AND PHASE vs FREQUENCY (INVERTING) 300 5 -3 -180 FREQUENCY (MHz) FIGURE 1. OPEN LOOP GAIN AND PHASE vs FREQUENCY 1 60 GAIN PHASE (°) 90 VS=±5V RG=50Ω 3 RL=500Ω CL=5pF 1 AV=+5 -1 AV=+10 -3 AV=+20 -5 0.1 1 10 -300 1k 100 -5 0.1 1 FREQUENCY (MHz) VS=±5V AV=+5 3 RG=50Ω CL=5pF NORMALIZED GAIN (dB) 5 VS=±5V RG=50Ω 180 RL=500Ω CL=5pF 60 -60 AV=+5 AV=+10 -180 1 RL=1kΩ -1 RL=500Ω RL=150Ω -3 AV=+20 1 10 100 RL=100Ω 1k FREQUENCY (MHz) FIGURE 5. PHASE vs FREQUENCY FOR VARIOUS AV+ 3 1k FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS AV+ 300 -300 0.1 100 FREQUENCY (MHz) FIGURE 3. GAIN AND PHASE vs FREQUENCY (NON-INVERTING) NORMALIZED GAIN (dB) 10 -5 0.1 1 10 100 1k FREQUENCY (MHz) FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS RL (AV=+5) FN7381.3 June 6, 2006 EL5130, EL5131 5 5 VS=±5V AV=+10 3 RG=50Ω CL=5pF VS=±5V AV=+5 3 RL=500Ω CL=5pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) Typical Performance Curves 1 -1 RL=1kΩ RL=500Ω -3 RL=150Ω RF=1kΩ RF=500Ω 1 -1 RF=200Ω -3 RF=100Ω RL=100Ω -5 0.1 1 10 100 -5 0.1 1k 1 FREQUENCY (MHz) 5 VS=±5V AV=+10 3 RL=500Ω CL=5pF VS=±5V AV=+5 3 RG=50Ω RL=500Ω NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1k FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RF (AV=+5) 5 1 RF=2.25kΩ RF=1.125kΩ RF=450Ω -3 100 FREQUENCY (MHz) FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS RL (AV=+10) -1 10 CL=22pF CL=15pF 1 CL=10pF -1 CL=6pF -3 RF=225Ω -5 0.1 1 10 100 -5 0.1 1k 1 FREQUENCY (MHz) VS=±5V AV=+5 3 RG=50Ω RL=500Ω CL=5pF CL=47pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 5 VS=±5V AV=+10 3 RG=50Ω RL=500Ω CL=33pF 1 CL=22pF CL=12pF -3 1 10 100 1k FREQUENCY (MHz) FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CL (AV=+10) 4 1k FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS CL (AV=+5) 5 -5 0.1 100 FREQUENCY (MHz) FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RF (AV=+10) -1 10 CIN=8.2pF CIN=4.7pF 1 CIN=2.7pF -1 CIN=1pF -3 -5 0.1 1 10 100 1k FREQUENCY (MHz) FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS CIN- (AV=+5) FN7381.3 June 6, 2006 EL5130, EL5131 Typical Performance Curves 5 VS=±5V AV=+10 3 RG=50Ω RL=500Ω CL=5pF CIN=25pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 5 CIN=18pF 1 CIN=15pF -1 CIN=10pF -3 VS=±5V AV=+5 3 RG=50Ω RL=500Ω CL=5pF VS=±6 1 VS=±2.5 -1 VS=±3 VS=±4 -3 VS=±5 -5 0.1 1 10 100 -5 0.1 1k FREQUENCY (MHz) VS=±5V AV=+5 3 RG=50Ω RL=500Ω CL=5pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 5 VS=±5V AV=+10 3 RG=50Ω RL=500Ω VS=±6 VS=±2.5 VS=±3 -3 100 1k FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS ±VS (AV=+5) 5 -1 10 FREQUENCY (MHz) FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS CIN(AV=+10) 1 1 VS=±4 1 -1 -3dB @ 360MHz -3 VS=±5 -5 0.1 1 10 100 -5 1k 1 FREQUENCY (MHz) 100 1k FREQUENCY (MHz) FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS VS± (AV=+10) FIGURE 16. FREQUENCY RESPONSE (-3dB ROLL-OFF) 0.5 -40 VS=±5V AV=+5 0.3 RG=50Ω RL=500Ω CL=5pF VS=±5V AV=+5 -60 RG=50Ω RL=500Ω GAIN (dB) NORMALIZED GAIN (dB) 10 0.1 -0.1 -80 -100 -0.1dB @ 230MHz -0.3 -0.5 -120 1 10 100 1k FREQUENCY (MHz) FIGURE 17. FREQUENCY RESPONSE (0.1dB GAIN FLATNESS) 5 -140 0.1 1 10 100 FREQUENCY (MHz) FIGURE 18. INPUT AND OUTPUT ISOLATION FOR DISABLE AMPLIFIER FN7381.3 June 6, 2006 EL5130, EL5131 Typical Performance Curves 10 -10 -10 VS+ -30 VS- VS=±5V AV=+5 -30 RL=150Ω CMRR (dB) PSRR (dB) AV=+10 VS=±5V -50 VS- -70 -50 -70 -90 VS+ -90 1k 10k 100k 1M 10M -110 0.01 100M 500M 0.1 FREQUENCY (Hz) 1k FIGURE 20. CMRR vs FREQUENCY 10 VOLTAGE NOISE (nV/√Hz) 5 4 GROUP DELAY (ns) 100 10 FREQUENCY (MHz) FIGURE 19. PSRR vs FREQUENCY 3 2 1 0 1 1 10 100 1 10 1k 100 FREQUENCY (MHz) 1k 10k 100k FREQUENCY (Hz) FIGURE 21. GROUP DELAY vs FREQUENCY FIGURE 22. INPUT VOLTAGE NOISE HARMONIC DISTORITON (dBc) CURRENT NOISE (pA/√Hz) -30 10 1 10 100 1k 10k FREQUENCY (Hz) FIGURE 23. INPUT CURRENT NOISE 6 100k VS=±5V AV=+5 -40 RG=50Ω RL=500Ω CL=5pF VOUT=2VP-P -50 THD 2ND HD -60 3RD HD -70 -80 0.5 1 10 20 FUNDAMENTAL FREQUENCY (MHz) FIGURE 24. HARMONIC DISTORITON vs FREQUENCY (AV=+5) FN7381.3 June 6, 2006 EL5130, EL5131 -30 -30 VS=±5V AV=+10 -40 RG=50Ω RL=500Ω -50 CL=5pF VOUT=2VP-P VS=±5V AV=+5 -40 RG=50Ω RL=500Ω -50 CL=5pF THD THD (dBc) HARMONIC DISTORITON (dBc) Typical Performance Curves 2ND HD -60 -70 THD FIN=5MHz -60 -70 3RD HD -80 THD FIN=1MHz -80 -90 0.5 1 10 -90 20 0 1 2 3 4 5 6 7 OUTPUT VOLTAGE (VP-P) FUNDAMENTAL FREQUENCY (MHz) FIGURE 25. HARMONIC DISTORTION vs FREQUENCY (AV=+10) FIGURE 26. THD vs OUTPUT VOLTAGE (WORST HARMONIC) 100 5 OUTPUT SWING GAIN (dB) AV=+5 VS=±5V OUTPUT IMPEDANCE (Ω) THD FIN=10MHz 10 1 0.1 VS=±5V AV=+5 3 RG=50Ω RL=500Ω CL=5pF VOUT=0.5VP-P VOUT=1VP-P 1 -1 VOUT=2VP-P VOUT=4VP-P -3 VOUT=6VP-P 0.01 10k 100k 1M 10M -5 0.1 100M 1 150 150 100 100 RISE TIME 4ns 0 -50 INPUT 40mVP-P VS=±5V AV=+5 RG=50Ω RL=500Ω CL=5pF -100 -150 -20 -10 0 10 20 30 40 50 0 OUTPUT 200mVP-P VS=±5V AV=+5 RG=50Ω RL=500Ω CL=5pF FALL TIME 4ns INPUT 40mVP-P -50 -100 50 TIME (ns) FIGURE 29. SMALL SIGNAL PULSE RESPONSE/RISE TIME 7 1k FIGURE 28. OUTPUT SWING vs FREQUENCY AMPLITUDE (mV) AMPLITUDE (mV) FIGURE 27. OUTPUT IMPEDANCE vs FREQUENCY OUTPUT 200mVP-P 100 FREQUENCY (MHz) FREQUENCY (Hz) 50 10 -150 270 280 290 300 310 320 330 TIME (ns) FIGURE 30. SMALL SIGNAL PULSE REPONSE/FALL TIME FN7381.3 June 6, 2006 EL5130, EL5131 Typical Performance Curves 2 1 AMPLITUDE (mV) AMPLITUDE (mV) 2 INPUT 400mVP-P 0 OUTPUT 2VP-P RISE TIME 4.4ns VS=±5V AV=+5 RG=50Ω RL=500Ω CL=5pF -1 -2 -20 -10 0 10 20 30 40 50 1 OUTPUT 2VP-P 0 INPUT 400mVP-P VS=±5V -1 AV=+5 RG=50Ω RL=500Ω CL=5pF -2 30 40 50 TIME (ns) 2 2 SLEW RATE 275V/µs AMPLITUDE (mV) AMPLITUDE (mV) 3 0 -1 VS=±5V AV=+5 RG=50Ω RL=500Ω CL=5pF -2 -3 -20 -10 0 10 20 70 80 90 100 FIGURE 32. LARGE SIGNAL PULSE RESPONSE/RISE TIME 3 OUTPUT 4VP-P 60 TIME (ns) FIGURE 31. LARGE SIGNAL PULSE RESPONSE/RISE TIME 1 FALL TIME 4.4ns 30 40 50 1 0 OUTPUT 4VP-P -1 VS=±5V AV=+5 RG=50Ω -2 RL=500Ω CL=5pF -3 510 520 530 TIME (ns) SLEW RATE 281V/µs 540 550 560 570 580 TIME (ns) FIGURE 33. SLEW RATE (POSITIVE) FIGURE 34. SLEW RATE (NEGATIVE) AV=+10 VS=±5V AV=+10 VS=±5V CH1 CH1 CH2 CH2 CH1=1V CH2=200mV CH1=1V CH2=200mV 200ns/DIV FIGURE 35. ENABLE RESPONSE/TURN-ON TIME 8 200ns/DIV FIGURE 36. DISABLE RESPONSE/TURN-OFF TIME FN7381.3 June 6, 2006 EL5130, EL5131 Typical Performance Curves 3.6 SUPPLY CURRENT (mA) 20 IP3 (dBm) 10 0 VS=±5V -10 AV=+5 RG=50Ω RL=500Ω CL=5pF -20 0.1 1 100 10 RG=50Ω RL=500Ω CL=5pF 3.5 AV=+10 AV=+5 3.4 3.3 3.2 2.5 1k 3.5 3 4.5 4 5 5.5 6 SUPPLY VOLTAGE (V) FREQUENCY (MHz) FIGURE 37. THIRD-ORDER INTERCEPT POINT FIGURE 38. SUPPLY CURRENT vs SUPPLY VOLTAGE DIFFERENTIAL PHASE (°) 0.01 -0.01 -0.03 -10 0 10 20 30 40 50 60 70 80 90 100 0.03 0.01 -0.01 -0.03 -10 0 10 20 30 40 50 60 70 80 90 100 IRE IRE FIGURE 39. DIFFERENTIAL GAIN ERRORS FIGURE 40. DIFFERENTIAL PHASE ERRORS -20 AMPLITUDE (dBm) DIFFERENTIAL GAIN (%) 0.03 VS=±5V AV=+5 RG=50Ω -50 RL=500Ω CL=5pF f1 f1 -80 2f2-f1 2f1-f2 -110 -140 400 440 480 520 560 600 FREQUENCY (kHz) FIGURE 41. IP3 9 FN7381.3 June 6, 2006 EL5130, EL5131 Typical Performance Curves JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 1 909mW θ 0.8 JA = 0.6 435mW 0.4 SO 8 11 0° C/ W θJ 0.2 0 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 1.2 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 0 25 SO T23 -5 A =23 0°C /W 75 85 100 50 0.7 625mW 0.6 θ JA = 0.5 391mW 0.4 0.3 SO 8 16 0° C/ W θJ 125 150 0.2 FIGURE 42. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 0 SO A =2 0.1 AMBIENT TEMPERATURE (°C) 10 0.8 0 25 50 T23 -5 56° C/W 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 43. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7381.3 June 6, 2006 EL5130, EL5131 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference N 8 14 16 Rev. L 2/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 11 FN7381.3 June 6, 2006 EL5130, EL5131 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A 6 N 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 SOT23-5 SOT23-6 TOLERANCE A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference Rev. E 3/00 3 NOTES: D 2X SYMBOL 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. C A2 SEATING PLANE 3. This dimension is measured at Datum Plane “H”. A1 0.10 C 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). NX 6. SOT23-5 version has no center lead (shown as a dashed line). (L1) H A GAUGE PLANE c L 0.25 0° +3° -0° All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7381.3 June 6, 2006