Microchip MCP608TI/SN 2.5v to 5.5v micropower cmos op amp Datasheet

MCP606/7/8/9
2.5V to 5.5V Micropower CMOS Op Amps
Features
Description
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The MCP606/7/8/9 family of operational amplifiers (op
amps) from Microchip Technology Inc. are unity-gain
stable with low offset voltage (250 µV, max.).
Performance characteristics include rail-to-rail output
swing capability and low input bias current (80 pA at
+85°C, max.). These features make this family of op
amps well suited for single-supply, precision, highimpedance, battery-powered applications.
Low Input Offset Voltage: 250 µV (max.)
Rail-to-Rail Output
Low Input Bias Current: 80 pA (max. at 85°C)
Low Quiescent Current: 25 µA (max.)
Power Supply Voltage: 2.5V to 5.5V
Unity-Gain Stable
Chip Select (CS) Capability: MCP608
Industrial Temperature Range: -40°C to +85°C
No Phase Reversal
Available in Single, Dual and Quad Packages
Typical Applications
• Battery Power Instruments
• High-Impedance Applications
- Photodiode Amplifier
- pH Probe Buffer Amplifier
- Infrared Detectors
- Precision Integrators
- Charge Amplifier for Piezoelectric
Transducers
• Strain Gauges
• Medical Instruments
• Test Equipment
Package Types
NC
VIN–
VIN+
VSS
• SPICE Macro Models (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
Typical Application
IL
RF
50 kΩ
To Load
(VLP)
2.5V
to
5.5V
VOUT
RSEN
10Ω
MCP606
MCP606
SOT-23-5
MCP606
PDIP, SOIC,TSSOP
Available Tools
RG
5 kΩ
The single MCP606 is available in standard 8-lead
PDIP, SOIC and TSSOP packages, as well as in a
SOT-23-5 package. The single MCP608 with Chip
Select (CS) is offered in standard 8-lead PDIP, SOIC
and TSSOP packages. The dual MCP607 is offered in
standard 8-lead PDIP, SOIC and TSSOP packages.
Finally, the quad MCP609 is offered in standard
14-lead PDIP, SOIC and TSSOP packages. All devices
are fully specified from -40°C to +85°C, with power
supplies from 2.5V to 5.5V.
To Load
(VLM)
1
2
3
4
8
7
6
5
NC
VDD
VOUT
NC
MCP607
PDIP, SOIC,TSSOP
VOUTA
VINA–
VINA+
VSS
1
2
3
4
8
7
6
5
VOUT 1
VSS 2
VIN+ 3
5 VDD
4 VIN–
MCP608
PDIP, SOIC,TSSOP
NC 1
VDD
VOUTB VIN– 2
VINB– VIN+ 3
VINB+ VSS 4
8
7
6
5
CS
VDD
VOUT
NC
MCP609
PDIP, SOIC,TSSOP
VOUTA
VINA–
VINA+
VDD
VINB+
VINB–
VOUTB
1
2
3
4
5
6
7
14 VOUTD
13 VIND–
12 VIND+
11 VSS
10 VINC+
9 VINC–
8 VOUTC
Low-Side Battery Current Sensor
© 2005 Microchip Technology Inc.
DS11177D-page 1
MCP606/7/8/9
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Absolute Maximum Ratings †
VDD – VSS .......................................................................7.0V
All Inputs and Outputs ................... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ) ......................... +150°C
ESD protection on all pins (HBM;MM) ...................2 kV; 200V
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2,
VOUT ≈ VDD/2 and RL = 100 kΩ to VDD/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
Input Offset Voltage
VOS
-250
—
+250
ΔVOS/ΔTA
—
±1.8
—
PSRR
80
93
—
Input Bias Current
IB
—
1
—
pA
At Temperature
IB
—
—
80
pA
Input Offset Bias Current
IOS
—
1
—
pA
Common Mode Input Impedance
ZCM
—
1013||6
—
Ω||pF
Differential Input Impedance
ZDIFF
—
1013||6
—
Ω||pF
Common Mode Input Range
VCMR
VSS – 0.3
VDD – 1.1
V
CMRR ≥ 75 dB
Common Mode Rejection Ratio
CMRR
75
91
—
dB
VDD = 5V,
VCM = -0.3V to 3.9V
DC Open-Loop Gain
(Large-signal)
AOL
105
121
—
dB
RL = 25 kΩ to VDD/2,
VOUT = 50 mV to VDD – 50 mV
DC Open-Loop Gain
(Large-signal)
AOL
100
118
—
dB
RL = 5 kΩ to VDD/2,
VOUT = 0.1V to VDD – 0.1V
VOL, VOH
VSS + 15
—
VDD – 20
mV
RL = 25 kΩ to VDD/2,
0.5V output overdrive
VOL, VOH
VSS + 45
—
VDD – 60
mV
RL = 5 kΩ to VDD/2,
0.5V output overdrive
VOUT
VSS + 50
—
VDD – 50
mV
RL = 25 kΩ to VDD/2,
AOL ≥ 105 dB
VOUT
VSS + 100
—
VDD – 100
mV
RL = 5 kΩ to VDD/2,
AOL ≥ 100 dB
ISC
—
7
—
mA
VDD = 2.5V
ISC
—
17
—
mA
VDD = 5.5V
VDD
2.5
—
5.5
V
IQ
—
18.7
25
µA
Input Offset Drift with Temperature
Power Supply Rejection Ratio
µV
µV/°C TA = -40°C to +85°C
dB
Input Bias Current and Impedance
TA = +85°C
Common Mode
Open-Loop Gain
Output
Maximum Output Voltage Swing
Linear Output Voltage Range
Output Short Circuit Current
Power Supply
Supply Voltage
Quiescent Current per Amplifier
DS11177D-page 2
IO = 0
© 2005 Microchip Technology Inc.
MCP606/7/8/9
AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
155
—
kHz
Phase Margin
PM
—
62
—
°
Slew Rate
SR
—
0.08
—
V/µs
G=1
f = 0.1 Hz to 10 Hz
G = +1
Noise
Input Noise Voltage
Eni
—
2.8
—
µVP-P
Input Noise Voltage Density
eni
—
38
—
nV/√Hz
f = 1 kHz
Input Noise Current Density
ini
—
3
—
fA/√Hz
f = 1 kHz
MCP608 CHIP SELECT (CS) CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Logic Threshold, Low
VIL
VSS
—
0.2 VDD
V
CS Input Current, Low
ICSL
-0.1
0.01
—
µA
CS Logic Threshold, High
VIH
0.8 VDD
—
VDD
V
CS Input Current, High
ICSH
—
0.01
0.1
µA
CS = VDD
ISS
-2
-0.05
—
µA
CS = VDD
IO(LEAK)
—
10
—
nA
CS = VDD
CS Low to Amplifier Output Turn-on Time
tON
—
9
100
µs
CS = 0.2VDD to VOUT = 0.9(VDD/2),
G = +1 V/V, RL = 1 kΩ to VSS
CS High to Amplifier Output Hi-Z
tOFF
—
0.1
—
µs
CS = 0.8VDD to VOUT = 0.1(VDD/2),
G = +1 V/V, RL = 1 kΩ to VSS
VHYST
—
0.6
—
V
VDD = 5.0V
CS Low Specifications
CS = 0.2VDD
CS High Specifications
CS Input High, GND Current
Amplifier Output Leakage, CS High
CS Dynamic Specifications
CS Hysteresis
VIL
CS
VIH
tON
VOUT
Hi-Z
tOFF
Hi-Z
ISS -50 nA (typ.) -18.7 µA (typ.)
-50 nA (typ.)
ICS -50 nA (typ.)
-50 nA (typ.)
FIGURE 1-1:
Timing Diagram for the CS
Pin on the MCP608.
© 2005 Microchip Technology Inc.
DS11177D-page 3
MCP606/7/8/9
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
Operating Temperature Range
TA
-40
—
+85
°C
—
+125
Storage Temperature Range
TA
°C
-65
—
+150
°C
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Thermal Resistance, 5L-SOT23
θJA
—
256
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-TSSOP
θJA
—
124
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
120
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Note 1:
The MCP606/7/8/9 operate over this extended temperature range, but with reduced performance. In any case, the
Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
DS11177D-page 4
© 2005 Microchip Technology Inc.
MCP606/7/8/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
25%
5%
Input Offset Voltage (µV)
25%
Input Offset Voltage (µV)
Input Offset Voltage at
10
9
10
9
Input Offset Voltage Drift Magnitude (µV/°C)
FIGURE 2-5:
Input Offset Voltage Drift
Magnitude at VDD = 2.5V.
24
TA = +85°C
TA = +25°C
TA = -40°C
Quiescent Current
per Amplifier (µA)
Quiescent Current
per Amplifier (µA)
22
20
18
16
14
12
10
8
6
4
2
0
8
5%
0%
250
200
150
100
50
0
-50
-100
-150
-200
0%
8
2%
10%
7
4%
6
6%
15%
5
8%
20%
4
10%
3
12%
1200 Samples
VDD = 2.5V
2
1200 Samples
VDD = 2.5V
FIGURE 2-2:
VDD = 2.5V.
7
FIGURE 2-4:
Input Offset Voltage Drift
Magnitude at VDD = 5.5V.
Input Offset Voltage at
0
14%
Input Offset Voltage Drift Magnitude (µV/°C)
Percentage of Occurances
16%
-250
Percentage of Occurances
FIGURE 2-1:
VDD = 5.5V.
6
0%
250
200
150
100
50
0
-50
-100
-150
-200
0%
5
2%
10%
4
4%
3
6%
15%
2
8%
20%
1
10%
1200 Samples
VDD = 5.5V
0
12%
1200 Samples
VDD = 5.5V
1
14%
Percentage of Occurances
16%
-250
Percentage of Occurances
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
22
VDD = 5.5V
20
18
16
VDD = 2.5V
14
12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-3:
Quiescent Current vs.
Power Supply Voltage.
© 2005 Microchip Technology Inc.
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-6:
Quiescent Current vs.
Ambient Temperature.
DS11177D-page 5
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
120
Input Offset Voltage (µV)
VDD =2.5V
VDD = 5.5V
300
200
100
Representative Part
20
0
90
0
Gain
60
-45
Phase
40
-90
20
-135
0
-180
-20
0.01 0.1
FIGURE 2-8:
vs. Frequency.
Open-Loop Phase (°)
Open-Loop Gain (dB)
45
5.0
4.5
50
80
40
60
30
40
20
20
10
VDD = 5.0V
-50
-25
0
25
50
75
0
100
FIGURE 2-11:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
Input Noise Voltage Density
(nV/—Hz)
Channel-to-Channel
Separation (dB)
60
Phase Margin
100
Ambient Temperature (°C)
Open-Loop Gain and Phase
130
120
110
100
90
FIGURE 2-9:
Channel-to-Channel
Separation (MCP607 and MCP609 only).
70
GBWP
120
10 100 1k 10k 100k 1M
Frequency (Hz)
Referred to Input
80
100
1k
10k
1.E+02
1.E+03
1.E+04
Frequency (Hz)
80
140
0
-225
1
140
DS11177D-page 6
Gain Bandwidth Product
(kHz)
160
RL = 25 kΩ
80
4.0
FIGURE 2-10:
Input Offset Voltage vs.
Common Mode Input Voltage.
Phase Margin (°)
FIGURE 2-7:
Input Offset Voltage vs.
Ambient Temperature.
100
3.5
Common Mode Input Voltage (V)
Ambient Temperature (°C)
120
3.0
100
2.5
75
2.0
50
1.5
25
1.0
0
40
0.5
-25
60
-20
0
-50
TA = +85°C
TA = +25°C
TA = -40°C
80
0.0
400
VDD = 5.5V
100
-0.5
Input Offset Voltage (µV)
500
100k
1.E+05
1000
100
10
0.1 1.E+0
1
10 1.E+0
100 1.E+0
1k 1.E+0
10k 1.E+0
100k
1.E1.E+0
01
0
Frequency
1
2 (Hz)
3
4
5
FIGURE 2-12:
vs. Frequency.
Input Noise Voltage Density
© 2005 Microchip Technology Inc.
MCP606/7/8/9
100
Input Bias and Offset Currents
(pA)
Input Bias and Offset Currents
(pA)
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
VDD = 5.5V
VCM = VDD
10
IB
1
| IOS |
0.1
60
40
20
10
-10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-16:
Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
120
VDD = 5.5V
115
110
VDD = 2.5V
105
1k
10k
1.E+03
1.E+04
Load Resistance (Ω)
FIGURE 2-14:
Load Resistance.
130
120
110
100
Power Supply Voltage (V)
FIGURE 2-17:
DC Open-Loop Gain vs.
Power Supply Voltage.
100
PSRRPSRR+
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
100k
1.E+05
DC Open-Loop Gain vs.
120
80
CMRR
60
40
20
0
0.1
1.E-01
RL = 25 kΩ
140
90
100
100
1.E+02
CMRR and PSRR (dB)
DC Open-Loop Gain (dB)
150
CMRR and PSRR (dB)
DC Open-Loop Gain (dB)
135
125
IOS
0
Ambient Temperature (°C)
130
IB
30
25 30 35 40 45 50 55 60 65 70 75 80 85
FIGURE 2-13:
Input Bias Current, Input
Offset Current vs. Ambient Temperature.
TA = +85°C
VDD = 5.5V
50
95
PSRR
90
CMRR
85
80
75
1
1.E+00
FIGURE 2-15:
Frequency.
10
100
1.E+01
1.E+02
Frequency (Hz)
1k
1.E+03
CMRR, PSRR vs.
© 2005 Microchip Technology Inc.
10k
1.E+04
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-18:
Temperature.
CMRR, PSRR vs. Ambient
DS11177D-page 7
MCP606/7/8/9
1000
VDD - VOH, VDD = 2.5V
VOL - VSS, VDD = 2.5V
100
VDD - VOH, VDD = 5.5V
VOL - VSS, VDD = 5.5V
10
1
0.1
1
10
Output Current (mA)
Output Voltage Headroom;
VDD – VOH and VSS – VOL (mV)
Output Voltage Headroom;
VDD – VOH and VOL – VSS (mV)
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
30
20
15
10
1
0.1
100
1.E+02
1k
10k
1.E+03
1.E+04
Frequency (Hz)
0
0.08
High to Low
0.04
0.02
0.00
-25
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-21:
Temperature.
DS11177D-page 8
100
5
G = +2 V/V
VDD = 5.0V
4
3
2
VIN
1
VOUT
0
FIGURE 2-23:
The MCP606/7/8/9 Show
No Phase Reversal.
Output Short Circuit Current
Magnitude (mA)
Low to High
-50
0
25
50
75
Ambient Temperature (°C)
Time (100 µs/div)
0.12
0.06
-25
-1
100k
1.E+05
FIGURE 2-20:
Maximum Output Voltage
Swing vs. Frequency.
0.10
VDD – VOH, VDD = 2.5V
VOL – VSS, VDD = 2.5V
5
FIGURE 2-22:
Output Voltage Headroom
vs. Ambient Temperature at RL = 5 kΩ.
Input and Output Voltages (V)
VDD = 2.5V
RL = 5 kΩ
25
6
VDD = 5.5V
VDD – VOH, VDD = 5.5V
VOL – VSS, VDD = 5.5V
-50
10
Maximum Output Voltage
Swing (V)
35
100
FIGURE 2-19:
Output Voltage Headroom
vs. Output Current Magnitude.
Slew Rate (V/µs)
40
Slew Rate vs. Ambient
100
25
+ISC , VDD = 5.5V
| -ISC |, VDD = 5.5V
20
15
10
5
+ISC , VDD = 2.5V
| -ISC |, VDD = 2.5V
0
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-24:
Output Short Circuit Current
Magnitude vs. Ambient Temperature.
© 2005 Microchip Technology Inc.
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = 25°C, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
5.0
VDD = 5.0V
4.5
4.0
Output Voltage (V)
Output Voltge (V)
4.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VDD = 5.0V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
Time (50 µs/div)
Time (50 µs/div)
FIGURE 2-25:
Pulse Response.
Large-signal, Non-inverting
FIGURE 2-28:
Pulse Response.
RL = 25 kΩ
Output Voltage (20 mV/div)
Output Voltage (20 mV/div)
VDD = 5.0V
Time (50 µs/div)
Time (50 µs/div)
Small-signal, Non-inverting
FIGURE 2-29:
Response.
3.5
3.0
2.5
2.0
1.5
CS Input
High to Low
CS Input
Low to High
1.0
0.5
5.0
VDD = 5.0V
Hysteresis
0.0
Amplifier Output Hi-Z
-0.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CS Input Voltage (V)
FIGURE 2-27:
(MCP608 only).
Chip Select (CS) Hysteresis
© 2005 Microchip Technology Inc.
Small-signal, Inverting Pulse
15
G = +1 V/V
RL = 1 kΩ to VSS
4.5
Amplifier Output Active
Output Voltage (V)
Internal CS Switch Output (V)
FIGURE 2-26:
Pulse Response.
Large-signal, Inverting
4.0
10
5
CS
3.5
3.0
2.5
-10
2.0
-15
1.5
1.0
0.5
0
-5
Output Enabled
-20
VOUT
Output
Hi-Z
Output
Hi-Z
0.0
Chip Select Voltage (V)
5.0
-25
-30
-35
Time (5 µs/div)
FIGURE 2-30:
Amplifier Output Response
Times vs. Chip Select (CS) Pulse
(MCP608 only).
DS11177D-page 9
MCP606/7/8/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE.
MCP606
(PDIP, SOIC,
TSSOP)
MCP606
(SOT-23-5)
MCP607
MCP608
MCP609
Symbol
6
1
1
6
1
VOUT, VOUTA
Output (op amp A)
2
4
2
2
2
VIN–, VINA–
Inverting Input (op amp A)
Non-inverting Input (op amp A)
3.1
3
3
3
3
3
VIN+, VINA+
7
5
4
7
4
VDD
—
—
5
—
5
VINB+
—
—
6
—
6
VINB–
Inverting Input (op amp B)
Positive Power Supply
Non-inverting Input (op amp B)
—
—
7
—
7
VOUTB
Output (op amp B)
—
—
—
—
8
VOUTC
Output (op amp B)
—
—
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
—
10
VINC+
Non-inverting Input (op amp C)
4
2
8
4
11
VSS
—
—
—
—
12
VIND+
Non-inverting Input (op amp D)
—
—
—
—
13
VIND–
Inverting Input (op amp D)
—
—
—
—
14
VOUTD
Output (op amp D)
—
—
—
8
—
CS
Chip Select
1, 5, 8
—
—
1, 5
—
NC
No Internal Connection
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Description
Analog Inputs
3.4
Negative Power Supply
Digital Input
The Chip Select (CS) pin is a Schmitt-triggered, CMOS
logic input. It is used to place the MCP608 op amp in a
Low-power mode, with the output(s) in a Hi-Z state.
The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents.
3.3
Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 2.5V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the output pins are at voltages
between VSS and VDD; while the input pins are at
voltages between VSS – 0.3V and VDD + 0.3V.
Typically, these parts are used in a single-supply
(positive) configuration. In this case, VSS is connected
to ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts can
share a bulk capacitor with nearby analog parts
(typically 1 µF or larger) within 100 mm of the VDD pin.
DS11177D-page 10
© 2005 Microchip Technology Inc.
MCP606/7/8/9
4.0
APPLICATIONS INFORMATION
The MCP606/7/8/9 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process
These op amps are unity-gain stable and suitable for a
wide range of general purpose applications.
4.1
linear region. To verify linear operation in this range, the
large-signal DC Open-Loop Gain (AOL) is measured at
points inside the supply rails. The measurement must
meet the specified AOL conditions in the specification
table.
4.3
Inputs
The MCP606/7/8/9 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-23 shows the input voltage
exceeding the supply voltage without any phase reversal.
The inputs of the MCP606/7/8/9 op amps connect to a
differential PMOS input stage. The Common Mode
Input Voltage Range (VCMR) includes ground in singlesupply systems (VSS), but does not include VDD. This
means that the amplifier input behaves linearly as long
as the Common Mode Input Voltage (VCM) is kept within
the specified VCMR limits (VSS – 0.3V to VDD – 1.1V at
+25°C).
Input voltages that exceed the Absolute Maximum
Voltage Range (VSS – 0.3V to VDD + 0.3V) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 4-1.
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage-feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain-peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-2) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
RISO
CL
VIN
MCP60X
VOUT
VIN
( Maximum expected VIN ) – V DD
R IN ≥ -----------------------------------------------------------------------------2 mA
V SS – ( Minimum expected V IN )
R IN ≥ --------------------------------------------------------------------------2 mA
FIGURE 4-1:
Resistor (RIN).
4.2
FIGURE 4-2:
Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-3 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
Input Current-Limiting
Rail-to-Rail Output
There are two specifications that describe the outputswing capability of the MCP606/7/8/9 family of op amps.
The first specification (Maximum Output Voltage Swing)
defines the absolute maximum swing that can be
achieved under the specified load conditions. For
instance, the output voltage swings to within 15 mV of
the negative rail with a 25 kΩ load to VDD/2. Figure 2-23
shows how the output voltage is limited when the input
goes beyond the linear region of operation.
The second specification that describes the outputswing capability of these amplifiers (Linear Output
Voltage Range) defines the maximum output swing that
can be achieved while the amplifier still operates in its
© 2005 Microchip Technology Inc.
10k
10000
Recommended RISO (:)
RIN
VOUT
MCP60X
1k
1000
GN = +1
GN = +2
GN t +4
100
10p
100
10
100
1000
10000
100p
1n
10n
Normalized Load Capacitance; CL/GN (F)
FIGURE 4-3:
Recommended RISO Values
for Capacitive Loads.
DS11177D-page 11
MCP606/7/8/9
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and simulations with the MCP606/7/8/9 SPICE macro model are
helpful.
4.4
MCP608 Chip Select (CS)
1.
2.
The MCP608 is a single op amp with Chip Select (CS).
When CS is pulled high, the supply current drops to
50 nA (typ.) and flows through the CS pin to VSS. When
this happens, the amplifier output is put into a highimpedance state. By pulling CS low, the amplifier is
enabled. If the CS pin is left floating, the amplifier may
not operate properly. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
4.5
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other nearby analog parts.
4.6
Non-inverting Gain and Unity-gain Buffer:
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
Inverting Gain and Transimpedance Gain
(convert current to voltage, such as photo
detectors) amplifiers:
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP606/7/8/9 family’s bias current at 25°C (1 pA, typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in Figure 4-4.
VIN-
VIN+
4.7
Application Circuits
4.7.1
LOW-SIDE BATTERY CURRENT
SENSOR
The MCP606/7/8/9 op amps can be used to sense the
load current on the low-side of a battery using the
circuit in Figure 4-5. In this circuit, the current from the
power supply (minus the current required to power the
MCP606) flows through a sense resistor (RSEN), which
converts it to voltage. This is gained by the the amplifier
and resistors, RG and RF . Since the non-inverting input
of the amplifier is at the load’s negative supply (VLM),
the gain from RSEN to VOUT is RF/RG .
V OUT = VLM + IL R
RG
5 kΩ
DS11177D-page 12
Example Guard Ring Layout
RF
50 kΩ
2.5V
to
5.5V
To Load
(VLP)
VOUT
RSEN
10Ω
FIGURE 4-5:
Sensor.
FIGURE 4-4:
for Inverting Gain.
( RF ⁄ RG )
IL
VSS
Guard Ring
SEN
MCP606
To Load
(VLM)
Low Side Battery Current
Since the input bias current and input offset voltage of
the MCP606 are low, and the input is capable of swinging below ground, there is very little error generated by
the amplifier. The quiescent current is very low, which
helps conserve battery power. The rail-to-rail output
makes it possible to read very low currents.
© 2005 Microchip Technology Inc.
MCP606/7/8/9
4.7.2
PHOTODIODE AMPLIFIERS
Sensors that produce an output current and have high
output impedance can be connected to a transimpedance amplifier. The transimpedance amplifier converts
the current into voltage. Photodiodes are one sensor
that produce an output current.
The key op amp characteristics that are needed for
these circuits are: low input offset voltage, low input
bias current, high input impedance and an input
common mode range that includes ground. The low
input offset voltage and low input bias current support
a very low voltage drop across the photodiode; this
gives the best photodiode linearity. Since the
photodiode is biased at ground, the op amp’s input
needs to function well both above and below ground.
4.7.2.1
operate at a much higher speed. This reverse bias also
increases the dark current and current noise, however.
Resistor R2 converts the current into voltage. Capacitor
C2 limits the bandwidth and helps stabilize the circuit
when D1’s junction capacitance is large.
VB < 0
V OUT = I D1 R 2
C2
R2
VOUT
ID1
VDD
Light
Photo-Voltaic Mode
D1
Figure 4-6 shows a transimpedance amplifier with a
photodiode (D1) biased in the Photo-voltaic mode (0V
across D1), which is used for precision photodiode
sensing.
As light impinges on D1, charge is generated, causing
a current to flow in the reverse bias direction of D1. The
op amp’s negative feedback forces the voltage across
the D1 to be nearly 0V. Resistor R2 converts the current
into voltage. Capacitor C2 limits the bandwidth and
helps stabilize the circuit when D1’s junction
capacitance is large.
V OUT = I D1 R
VB
FIGURE 4-7:
Photodiode (in Photoconductive mode) and Transimpedance
Amplifier.
4.7.3
2
R2
VOUT
R
2R
⎛
1 + ---------1- ⎞ + V
VOUT = ( V 1 – V 2 ) ⎜1 + -----⎟
REF
R2 RG ⎠
⎝
VDD
Light
D1
TWO OP AMP INSTRUMENTATION
AMPLIFIER
The two op amp instrumentation amplifier shown in
Figure 4-8 serves the function of taking the difference
of two input voltages, level-shifting it and gaining it to
the output. This configuration is best suited for higher
gains (i.e., gain > 3 V/V). The reference voltage (VREF)
is typically at mid-supply (VDD/2) in a single-supply
environment.
C2
ID1
MCP606
MCP606
RG
R1
R2
R2
R1
VREF
FIGURE 4-6:
Photodiode (in Photo-voltaic
mode) and Transimpedance Amplifier.
4.7.2.2
Photo-Conductive Mode
Figure 4-6 shows a transimpedance amplifier with a
photodiode (D1) biased in the Photo-conductive mode
(D1 is reverse biased), which is used for high-speed
applications.
As light impinges on D1, charge is generated, causing
a current to flow in the reverse bias direction of D1.
Placing a negative bias on D1 significantly reduces its
junction capacitance, which allows the circuit to
© 2005 Microchip Technology Inc.
V2
VOUT
½
MCP607
½
MCP607
V1
FIGURE 4-8:
Amplifier.
Two op amp Instrumentation
The key specifications that make the MCP606/7/8/9
family appropriate for this application circuit are low
input bias current, low offset voltage and high commonmode rejection.
DS11177D-page 13
MCP606/7/8/9
4.7.4
THREE OP AMP
INSTRUMENTATION AMPLIFIER
4.7.5
PRECISION GAIN WITH GOOD
LOAD ISOLATION
A classic, three op amp instrumentation amplifier is
illustrated in Figure 4-9. The two input op amps provide
differential signal gain and a common mode gain of +1.
The output op amp is a difference amplifier, which
converts its input signal from differential to a single
ended output; it rejects common mode signals at its
input. The gain of this circuit is simply adjusted with one
resistor (RG). The reference voltage (VREF) is typically
referenced to mid-supply (VDD/2) in single-supply
applications.
In Figure 4-10, the MCP606 op amps, R1 and R2
provide a high gain to the input signal (VIN). The
MCP606’s low offset voltage makes this an accurate
circuit.
2R ⎞ ⎛ R 4⎞
⎛
V
( V – V ) ⎜1 + ---------2 ⎟ ⎜ ------⎟ + V
OUT =
1
2 ⎝
REF
R ⎠ ⎝ R 3⎠
G
V
= V IN (1 + R 2 ⁄ R 1 )
OUT
V2
The MCP601 is configured as a unity-gain buffer. It
isolates the MCP606’s output from the load, increasing
the high-gain stage’s precision. Since the MCP601 has
a higher output current, with the two amplifiers being
housed in separate packages, there is minimal change
in the MCP606’s offset voltage due to loading effect.
MCP606
VIN
½
MCP607
MCP601
VOUT
R3
R4
VOUT
R2
RG
FIGURE 4-10:
Load Isolation.
MCP606
R2
R1
R2
Precision Gain with Good
VREF
R3
V1
R4
½
MCP607
FIGURE 4-9:
Three op amp
Instrumentation Amplifier.
DS11177D-page 14
© 2005 Microchip Technology Inc.
MCP606/7/8/9
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP606/7/8/9 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP606/7/8/9
op amps is available on our web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
The FilterLab software is an innovative tool that
simplifies analog active-filter (using op amps) design. It
is available free of charge from our web site at
www.microchip.com. The FilterLab software tool
provides full schematic diagrams of the filter circuit with
component values. It also outputs the filter circuit in
SPICE format, which can be used with the macro
model to simulate actual filter performance.
© 2005 Microchip Technology Inc.
DS11177D-page 15
MCP606/7/8/9
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SOT-23-5
XXNN
SB25
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
XXXXXXXX
XXXXYYWW
NNN
Example:
XXXX
YYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
Note:
DS11177D-page 16
Example:
MCP606
e3
SN^^0545
256
8-Lead TSSOP
e3
Example:
MCP606
e3
I/P^^256
0545
8-Lead SOIC (150 mil)
*
Example:
606
I545
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2005 Microchip Technology Inc.
MCP606/7/8/9
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP609)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXNNN
YYWW
14-Lead SOIC (150 mil) (MCP609)
MCP609
e3
I/P^^256
0545
Example:
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP609)
MCP609
e3
I/SL^^
0545256
Example:
XXXXXXXX
YYWW
609IST
0545
NNN
256
© 2005 Microchip Technology Inc.
DS11177D-page 17
MCP606/7/8/9
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
E
E1
p
B
p1
n
D
1
α
c
A
Units
Dimension Limits
n
Number of Pins
p
Pitch
p1
Outside lead pitch (basic)
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
φ
L
β
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
.035
.035
.000
.102
.059
.110
.014
0
.004
.014
0
0
A2
A1
INCHES*
NOM
5
.038
.075
.046
.043
.003
.110
.064
.116
.018
5
.006
.017
5
5
MAX
.057
.051
.006
.118
.069
.122
.022
10
.008
.020
10
10
MILLIMETERS
NOM
5
0.95
1.90
0.90
1.18
0.90
1.10
0.00
0.08
2.60
2.80
1.50
1.63
2.80
2.95
0.35
0.45
0
5
0.09
0.15
0.35
0.43
0
5
0
5
MIN
MAX
1.45
1.30
0.15
3.00
1.75
3.10
0.55
10
0.20
0.50
10
10
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-178
Drawing No. C04-091
DS11177D-page 18
© 2005 Microchip Technology Inc.
MCP606/7/8/9
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
§
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2005 Microchip Technology Inc.
DS11177D-page 19
MCP606/7/8/9
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS11177D-page 20
© 2005 Microchip Technology Inc.
MCP606/7/8/9
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
A2
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B
α
β
MIN
INCHES
NOM
MAX
8
.026
.033
.002
.246
.169
.114
.020
0
.004
.007
0
0
.035
.004
.251
.173
.118
.024
4
.006
.010
5
5
.043
.037
.006
.256
.177
.122
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
8
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
2.90
3.00
3.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
© 2005 Microchip Technology Inc.
DS11177D-page 21
MCP606/7/8/9
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
14
.100
.155
.130
MAX
MILLIMETERS
NOM
14
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
18.80
19.05
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.740
.750
.760
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
eB
Overall Row Spacing
§
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS11177D-page 22
MAX
4.32
3.68
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
15
© 2005 Microchip Technology Inc.
MCP606/7/8/9
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
A1
L
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.150
.337
.010
.016
0
.008
.014
0
0
INCHES*
NOM
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.347
.020
.050
8
.010
.020
15
15
MILLIMETERS
NOM
14
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
5.99
3.81
3.90
8.56
8.69
0.25
0.38
0.41
0.84
0
4
0.20
0.23
0.36
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
© 2005 Microchip Technology Inc.
DS11177D-page 23
MCP606/7/8/9
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
β
A1
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Molded Package Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
φ
c
B1
α
β
MIN
.033
.002
.246
.169
.193
.020
0
.004
.007
0
0
INCHES
NOM
14
.026
.035
.004
.251
.173
.197
.024
4
.006
.010
5
5
A2
MAX
.043
.037
.006
.256
.177
.201
.028
8
.008
.012
10
10
MILLIMETERS*
NOM
MAX
14
0.65
1.10
0.85
0.90
0.95
0.05
0.10
0.15
6.25
6.38
6.50
4.30
4.40
4.50
4.90
5.00
5.10
0.50
0.60
0.70
0
4
8
0.09
0.15
0.20
0.19
0.25
0.30
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS11177D-page 24
© 2005 Microchip Technology Inc.
MCP606/7/8/9
APPENDIX A:
REVISION HISTORY
Revision D (February 2005)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
Added Section 3.0 “Pin Descriptions”.
Updated Section 4.0 “Applications Information”.
Added Section 4.3 “Capacitive Loads”
Updated Section 5.0 “Design Tools” to
include FilterLab® and to point to the latest
SPICE macro model.
Corrected and updated Section 6.0 “Packaging
Information”.
Added Section Appendix A: “Revision History”.
Revision C (January 2001)
Revision B (May 2000)
Revision A (January 2000)
• Original Release of this Document.
© 2005 Microchip Technology Inc.
DS11177D-page 25
MCP606/7/8/9
NOTES:
DS11177D-page 26
© 2005 Microchip Technology Inc.
MCP606/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
c)
Device
Temperature Range
Package
MCP606 = Single Op Amp
MCP606T = Single Op Amp
Tape and Reel (SOIC, TSSOP)
MCP607 = Dual Op Amp
MCP607T = Dual Op Amp
Tape and Reel (SOIC, TSSOP)
MCP608 = Single Op Amp with CS
MCP608T = Single Op Amp with CS
Tape and Reel (SOIC, TSSOP)
MCP609 = Quad Op Amp
MCP609T = Quad Op Amp
Tape and Reel (SOIC, TSSOP)
I
OT
P
SN
SL
ST
=
d)
e)
f)
MCP606-I/P:
Industrial Temperature,
8LD PDIP package.
MCP606-I/SN: Industrial Temperature,
8LD SOIC package.
MCP606T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
MCP606-I/ST:
Industrial Temperature,
8LD TSSOP package.
MCP606-I/OT: Industrial Temperature,
5LD SOT-23 package.
MCP606T-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT-23 package.
a)
MCP607-I/P:
b)
MCP607T-I/P:
a)
MCP608-I/SN:
Industrial Temperature,
8LD PDIP package.
Industrial Temperature,
8LD PDIP package.
-40°C to +85°C
=
=
=
=
=
© 2005 Microchip Technology Inc.
Plastic SOT-23, 5-lead
Plastic DIP (300 mil Body), 8-lead & 14-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP, 8-lead & 14-lead
b)
Industrial Temperature,
8LD SOIC package.
MCP608T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
a)
MCP609-I/P:
b)
MCP609T-I/P:
Industrial Temperature,
14LD PDIP package.
Industrial Temperature,
14LD PDIP package.
DS11177D-page 27
MCP606/7/8/9
NOTES:
DS11177D-page 28
© 2005 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance and WiperLock are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005 Microchip Technology Inc.
DS11177D-page 29
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
India - New Delhi
Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark - Ballerup
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
Japan - Kanagawa
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
France - Massy
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Germany - Ismaning
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
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Fax: 852-2401-3431
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
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Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Italy - Milan
Tel: 39-0331-742611
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Netherlands - Drunen
Tel: 31-416-690399
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England - Berkshire
Tel: 44-118-921-5869
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Tel: 886-3-572-9526
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Los Angeles
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Tel: 949-462-9523
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Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
10/20/04
DS11177D-page 30
© 2005 Microchip Technology Inc.