AD AD8209WBRMZ-R7 High voltage, precision difference amplifier Datasheet

High Voltage,
Precision Difference Amplifier
AD8209
±8000 V HBM ESD
AEC-Q100 qualified
EMI filters included
High common-mode voltage range
−2 V to +45 V operating
−24 V to +80 V survival
Buffered output voltage
Gain = 14 V/V
Low-pass filter (single-pole or two-pole)
Wide operating temperature range
8-lead MSOP: −40°C to +125°C
Excellent ac and dc performance
±1 mV voltage offset
−5 ppm/°C typical gain drift
80 dB CMRR minimum dc to 10 kHz
FUNCTIONAL BLOCK DIAGRAM
VS
A1
EMI
FILTER
IN+
EMI
FILTER
IN–
EMI
FILTER
A2
AD8209
+
G=7
–
+
G=2
–
GND
OUT
08461-001
FEATURES
Figure 1.
APPLICATIONS
High-side current sensing
Motor controls
Solenoid controls
Power management
Low-side current sensing
Diagnostic protection
GENERAL DESCRIPTION
The AD8209 is a single-supply difference amplifier ideal for
amplifying and low-pass filtering small differential voltages in the
presence of a large common-mode voltage. The input commonmode voltage range extends from −2 V to +45 V at a single +5 V
supply. The AD8209 is qualified per AEC-Q100 specifications. The
amplifier offers enhanced input overvoltage and ESD protection,
and includes EMI filtering.
performance, minimizing errors in the application. Typical offset
and gain drift in the MSOP package are less than 5 μV/°C and
10 ppm/°C, respectively. The device also delivers a minimum
CMRR of 80 dB from dc to 10 kHz.
The AD8209 features an externally accessible 100 kΩ resistor at
the output of the preamplifier (A1), which can be used for lowpass filtering and for establishing gains other than 14.
Automotive applications demand robust, precision components for
improved system control. The AD8209 provides excellent ac and dc
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
AD8209
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 11
Applications ....................................................................................... 1
High-Side Current Sensing with a Low-Side Switch ............. 11
Functional Block Diagram .............................................................. 1
High-Rail Current Sensing ....................................................... 11
General Description ......................................................................... 1
Low-Side Current Sensing ........................................................ 11
Revision History ............................................................................... 2
Gain Adjustment ........................................................................ 12
Specifications..................................................................................... 3
Gain Trim .................................................................................... 12
Absolute Maximum Ratings............................................................ 4
Low-Pass Filtering ...................................................................... 13
ESD Caution .................................................................................. 4
High Line Current Sensing with LPF and Gain Adjustment ......14
Pin Configuration and Function Descriptions ............................. 5
Outline Dimensions ....................................................................... 15
Typical Performance Characteristics ............................................. 6
Ordering Guide .......................................................................... 15
Theory of Operation ...................................................................... 10
REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8209
SPECIFICATIONS
TOPR = −40°C to +125°C, TA = 25°C, VS = 5 V, RL = 25 kΩ (RL is the output load resistor), unless otherwise noted.
Table 1.
Parameter
SYSTEM GAIN
Initial
Error vs. Temperature
Gain Drift
VOLTAGE OFFSET
Initial Input Offset (Referred to Input [RTI])
Input Offset (RTI) Over Temperature
Voltage Offset vs. Temperature
INPUT
Input Impedance
Differential
Common Mode
VCM (Continuous)
CMRR 2
PREAMPLIFIER (A1)
Gain
Gain Error
Output Voltage Range
Output Resistance
OUTPUT BUFFER (A2)
Gain
Gain Error
Output Voltage Range 4
Input Bias Current
Output Resistance
DYNAMIC RESPONSE
System Bandwidth
Slew Rate
NOISE
0.1 Hz to 10 Hz
Spectral Density, 1 kHz (RTI)
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current vs. Temperature
PSRR
TEMPERATURE RANGE
For Specified Performance at TOPR
Test Conditions 1
Min
Typ
Max
Unit
0
±0.3
−20
V/V
%
ppm/°C
VCM = 0.15 V, TA
VCM = 0 V, TOPR
VCM = 0 V, TOPR
−20
±2
±4
+20
mV
mV
μV/°C
440
220
+45
VCM = −2 V to +45 V, dc
f = dc to 10 kHz, 3 TOPR
360
180
−2
80
80
kΩ
kΩ
V
dB
dB
14
0.075 V ≤ VOUT ≤ (VS − 0.1 V), dc, TOPR
TOPR
400
200
100
7
0.05 V ≤ VOUT ≤ (VS − 0.1 V), dc, TOPR
−0.3
0.05
97
100
+0.3
VS − 0.1
103
2
0.075 V ≤ VOUT ≤ (VS − 0.1 V), dc, TOPR
RL = 25 kΩ, differential Input (V) = 0 V, TOPR
TOPR
RL = 1 kΩ, frequency = dc
2
V/V
%
V
nA
Ω
80
1
kHz
V/μs
20
500
μV p-p
nV/√Hz
−0.3
0.075
VIN = 0.01 V p-p, VOUT = 0.14 V p-p
VIN = 0.28 V, VOUT = 4 V step
+0.3
VS − 0.1
50
4.5
Typical, TA
VOUT = 0.1 V dc, VS = 5 V, TOPR
VS = 4.5 V to 5.5 V, TOPR
2.7
−40
1
5.5
1.6
66
V/V
%
V
kΩ
80
+125
V
mA
mA
dB
°C
VCM = input common-mode voltage.
Source imbalance < 2 Ω.
3
The AD8209 preamplifier exceeds 80 dB CMRR at 10 kHz. However, because the output is available only by way of the 100 kΩ resistor, even a small amount of pin-topin capacitance between the IN pins and the A1 and A2 pins might couple an input common-mode signal larger than the greatly attenuated preamplifier output. The
effect of pin-to-pin coupling can be neglected in all applications by using a filter capacitor from Pin 3 to GND.
4
The output voltage range of the AD8209 varies depending on the load resistance and temperature. For additional information on this specification, refer to Figure 12
and Figure 13.
2
Rev. 0 | Page 3 of 16
AD8209
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Continuous Input Voltage (Common Mode)
Differential Input Voltage
Reversed Supply Voltage Protection
ESD Human Body Model
Operating Temperature Range
Storage Temperature Range
Output Short-Circuit Duration
Lead Temperature Range (Soldering 10 sec)
Rating
12 V
−24 V to +80 V
±12 V
0.3 V
±8000 V
−40°C to +125°C
−65°C to +150°C
Indefinite
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 4 of 16
AD8209
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
8
2
7
3
A1 3
AD8209
TOP VIEW
(Not to Scale)
A2 4
+IN
7
VS
6
NC
5
OUT
NC = NO CONNECT
4
5
08461-003
GND 2
8
08461-002
–IN 1
Figure 3. Metallization Photograph
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
−IN
GND
A1
A2
OUT
NC
VS
+IN
Coordinates
X
Y
−322
+563
−321
+208
−321
−51
−321
−214
+321
−388
+322
+322
+363
+561
Description
Inverting Input
Ground
Preamplifier (A1) Output
Buffer (A2) Input
Buffer (A2) Output
No Connect
Supply
Noninverting Input
Rev. 0 | Page 5 of 16
AD8209
TYPICAL PERFORMANCE CHARACTERISTICS
0.70
1500
0.55
1250
0.40
1000
0.25
750
GAIN ERROR (ppm)
0.10
–0.05
–0.20
–0.35
500
250
0
–250
–0.50
–500
–0.65
08461-004
TEMPERATURE (°C)
–1000
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
TEMPERATURE (°C)
Figure 4. Typical Offset Drift vs. Temperature
Figure 7. Typical Gain Error vs. Temperature
30
0.47
TOTAL INPUT BIAS CURRENT (mA)
25
20
15
GAIN (dB)
08461-005
–750
–0.80
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
10
5
0
–5
–10
0.42
0.37
0.32
0.27
0.22
0.17
0.12
0.07
0.02
–15
10k
100k
FREQUENCY (Hz)
1M
–0.03
08461-022
–20
1k
–2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
INPUT COMMON-MODE (V)
Figure 5. Typical Small-Signal Bandwidth
08461-006
VOSI (mV)
TOPR = −40°C to +125°C, TA = 25°C, VS = 5 V, RL = 25 kΩ (RL is the output load resistor), unless otherwise noted.
Figure 8. Total Input Bias Current vs. Common-Mode Voltage,
with +IN and –IN Pins Connected (Shorted)
–35
140
130
+125°C
+25°C
110
–40°C
90
80
70
60
50
–30
–40°C
–25
+25°C
+125°C
–20
–15
30
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
–10
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
A2 INPUT VOLTAGE (V)
2.0 2.2
2.4
08461-007
40
08461-012
CMRR (dB)
100
A2 INPUT BIAS CURRENT (nA)
120
Figure 9. Input Bias Current of A2 vs. Input Voltage and Temperature
Figure 6. Typical CMRR vs. Frequency
Rev. 0 | Page 6 of 16
AD8209
2.0
11.5
1.8
11.0
10.5
OUTPUT VOLTAGE RANGE (V)
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
1.6
1.4
1.2
1.0
0.8
0.6
0.4
6.0
0.2
5.0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
08461-008
5.5
0
0
Figure 10. Maximum Output Sink Current vs. Temperature
0.5
1.0
1.5
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
2.5
3.5
4.5
5.5
6.5
7.5
8.5
OUTPUT SINK CURRENT (mA)
Figure 13. Output Voltage Range from GND vs. Output Sink Current
6.3
6.0
5.8
INPUT
100mV/DIV
5.5
1
5.3
OUTPUT
5.0
4.8
500mV/DIV
4.5
2
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
08461-018
4.3
08461-009
MAXIMUM OUTPUT SOURCE CURRENT (mA)
6.5
4.1
–40
TIME (2µs/DIV)
Figure 11. Maximum Output Source Current vs. Temperature
Figure 14. Rise Time
5.0
4.2
100mV/DIV
3.8
INPUT
3.4
1
500mV/DIV
3.0
2.6
2.2
OUTPUT
1.8
2
08461-017
OUTPUT VOLTAGE RANGE (V)
4.6
1.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
OUTPUT SOURCE CURRENT (mA)
08461-010
1.4
0
08461-011
MAXIMUM OUTPUT SINK CURRENT (mA)
12.0
TIME (2µs/DIV)
Figure 12. Output Voltage Range of A2 vs. Output Source Current
Figure 15. Fall Time
Rev. 0 | Page 7 of 16
AD8209
200mV/DIV
2
3
2V/DIV
INPUT
2V/DIV
3
0.01%/DIV
08461-016
OUTPUT
08461-014
2
TIME (2µs/DIV)
TIME (20µs/DIV)
Figure 16. Differential Overload Recovery, Rising
Figure 19. Settling Time, Falling
500
+125°C
+25°C
–40°C
200mV/DIV
400
INPUT
300
COUNT
3
2V/DIV
200
2
OUTPUT
0
–4
TIME (2µs/DIV)
–3
Figure 17. Differential Overload Recovery, Falling
–2
–1
0
VOS (mV)
1
2
3
4
10
15
20
08461-019
08461-013
100
Figure 20. Offset Distribution
180
150
120
2V/DIV
COUNT
2
0.01%/DIV
90
60
3
0
–20
TIME (20µs/DIV)
–15
–10
–5
0
5
OFFSET DRIFT (µV/°C)
Figure 21. Offset Drift Distribution
Figure 18. Settling Time, Rising
Rev. 0 | Page 8 of 16
08461-020
08461-015
30
AD8209
1400
1200
800
600
400
200
0
–20
–15
–10
–5
0
5
GAIN DRIFT (ppm/°C)
10
15
20
08461-021
COUNT
1000
Figure 22. Gain Drift Distribution
Rev. 0 | Page 9 of 16
AD8209
THEORY OF OPERATION
The AD8209 is a single-supply difference amplifier typically used
to amplify a small differential voltage in the presence of rapidly
changing, high common-mode voltages.
The AD8209 consists of two amplifiers (A1 and A2), a resistor
network, a small voltage reference, and a bias circuit (not shown);
see Figure 23.
The set of input attenuators preceding A1 consist of RA, RB, and
RC, which feature a combined series resistance of approximately
400 kΩ ± 20%. The purpose of these resistors is to attenuate the
input voltage to match the input voltage range of A1. This balanced
resistor network attenuates the common-mode signal by a ratio
of 1/14. The A1 amplifier inputs are held within the power supply
range, even as Pin 1 and Pin 8 exceed the supply or fall below the
common (ground). A reference voltage of 350 mV biases the
attenuator above ground, allowing Amplifier A1 to operate in
the presence of negative common-mode voltages.
The input resistor network also attenuates normal (differential)
mode voltages. Therefore, A1 features a gain of 97 V/V to provide
a total system gain, from ±IN to the output of A1, equal to 7 V/V,
as shown in the following equation:
by connecting A1 to A2 and placing a capacitor to ground (see
Figure 32).
The value of RF1 and RF2 is 10 kΩ, providing a gain of 2 V/V for
Amplifier A2. When connecting Pin A1 and Pin A2 together, the
AD8209 provides a total system gain equal to
Total Gain of (A1 + A2) (V/V) = 7 (V/V) × 2 (V/V) = 14 V/V
at the output of A2 (the OUT pin).
The ratios of RA, RB, RC, and RF are trimmed to a high level of
precision, allowing a typical CMRR value that exceeds 80 dB. This
performance is accomplished by laser trimming the resistor ratio
matching to better than 0.01%.
–IN
RA
+IN
VS
RA
–
RF
RB
RG
RC
RC
A2
RFILTER
+
RB
A1
+
A1
OUT
A2
–
RF1
RF
RM
RF2
A precision trimmed, 100 kΩ resistor is placed in series with the
output of Amplifier A1. The user has access to this resistor via
an external pin (A1). A low-pass filter can be easily implemented
Rev. 0 | Page 10 of 16
08461-025
350mV
Gain (A1) = 1/14 (V/V) × 97 (V/V) = 7 V/V
GND
Figure 23. Simplified Schematic
AD8209
APPLICATIONS INFORMATION
HIGH-SIDE CURRENT SENSING
WITH A LOW-SIDE SWITCH
HIGH-RAIL CURRENT SENSING
In load control configurations for high-side current sensing with a
low-side switch, the PWM-controlled switch is ground referenced.
An inductive load (solenoid) connects to a power supply/battery.
A resistive shunt is placed between the switch and the load (see
Figure 24). An advantage of placing the shunt on the high side
is that the entire current, including the recirculation current, is
monitored because the shunt remains in the loop when the switch
is off. In addition, shorts to ground can be detected with the shunt
on the high side, enhancing the diagnostics of the control loop. In
this circuit configuration, when the switch is closed, the commonmode voltage moves down to near the negative rail. When the
switch is opened, the voltage reversal across the inductive load
causes the common-mode voltage to be held one diode drop
above the battery by the clamp diode.
In the high-rail current-sensing configuration, the shunt resistor is
referenced to the battery. High voltage is present at the inputs of
the current-sense amplifier. When the shunt is battery referenced,
the AD8209 produces a linear ground-referenced analog output.
Additionally, the AD8214 can be used to provide an overcurrent
detection signal in as little as 100 ns (see Figure 26). This feature is
useful in high current systems where fast shutdown in overcurrent
conditions is essential.
OVERCURRENT
DETECTION (<100ns)
5
6
7
8
OUT GND NC –IN
AD8214
NC VREG +IN
4
3
VS
2
1
5V
CLAMP
DIODE
CLAMP
DIODE
INDUCTIVE
LOAD
OUTPUT
SHUNT
+IN
+VS
NC
+
BATTERY
–IN
GND
–
SHUNT
AD8209
A1
A2
GND
A1
1
8
2
7
3
AD8209
6
5
4
–
+IN
VS
BATTERY
INDUCTIVE
LOAD
5V
NC
OUT
SWITCH
CF
A2
08461-028
–IN
+
OUT
SWITCH
Figure 26. Battery-Referenced Shunt Resistor
08461-026
CF
NC = NO CONNECT
Figure 24. Low-Side Switch
In cases where a high-side switch is used for PWM control of the
load current in an application, the AD8209 can be used as shown
in Figure 25. The recirculation current through the freewheeling
diode (clamp diode) is monitored through the shunt resistor. In
this configuration, the common-mode voltage in the application
drops below GND when the FET is switched off. The AD8209
operates down to −2 V, providing an accurate current measurement.
LOW-SIDE CURRENT SENSING
In systems where low-side current sensing is preferable, the
AD8209 provides a simple, high accuracy, integrated solution. In
this configuration, the AD8209 rejects ground noise and offers high
input to output linearity, regardless of the differential input voltage.
INDUCTIVE
LOAD
5V
CLAMP
DIODE
SWITCH
OUTPUT
+IN
5V
+VS
NC
OUT
BATTERY
SWITCH
+VS
NC
OUT
+
BATTERY
–
–IN
SHUNT
GND
A1
A2
AD8209
CF
NC = NO CONNECT
–IN
CLAMP
DIODE
GND
A1
A2
Figure 27. Ground-Referenced Shunt Resistor
CF
NC = NO CONNECT
08461-027
INDUCTIVE
LOAD
Figure 25. High-Side Switch
Rev. 0 | Page 11 of 16
08461-029
+IN
AD8209
SHUNT
OUTPUT
AD8209
4 mA to 20 mA Current Loop Receiver
The AD8209 can also be used in low current-sensing applications, such as the 4 mA to 20 mA current loop receiver shown
in Figure 28. In such applications, the relatively large shunt
resistor may degrade the common-mode rejection. Adding a
resistor of equal value on the low impedance side of the input
corrects this error.
used should be equal to 100 kΩ minus the parallel sum of REXT
and 100 kΩ. For example, with REXT = 100 kΩ (yielding a composite
gain of 7 V/V), the optional offset nulling resistor is 50 kΩ.
Gains Greater than 14
Connecting a resistor from the output of the buffer amplifier to
its noninverting input, as shown in Figure 30, increases the gain.
The gain is now multiplied by the factor
5V
REXT/(REXT − 100 kΩ)
10Ω
1%
For example, it is doubled for REXT = 200 kΩ. Overall gains as
high as 50 are achievable in this way. Note that the accuracy of
the gain becomes critically dependent on the resistor value at
high gains. In addition, the effective input offset voltage at Pin 1
and Pin 8 (which is about six times the actual offset of A1) limits
the use of the part in high gain, dc-coupled applications.
OUTPUT
+IN
+VS
NC
OUT
+
–
BATTERY
10Ω
1%
AD8209
–IN
GND
A1
A2
5V
OUTPUT
08461-030
CF
NC = NO CONNECT
+IN
+VS
OUT
NC
GAIN =
+
Figure 28. 4 mA to 20 mA Current Loop Receiver
VDIFF
AD8209
REXT
–
REXT = 100kΩ
GAIN ADJUSTMENT
–IN
The default gain of the preamplifier and buffer are 7 V/V and
2 V/V, respectively, resulting in a composite gain of 14 V/V. With
the addition of external resistor(s) or trimmer(s), the gain can
be lowered, raised, or finely calibrated.
REXT/(100 kΩ + REXT)
5V
08461-032
–
GAIN TRIM
Figure 31 shows a method for incremental gain trimming by
using a trim potentiometer and an external resistor, REXT.
The following approximation is useful for small gain ranges:
+VS
NC
ΔG ≈ (10 MΩ ÷ REXT)%
AD8209
14REXT
REXT + 100kΩ
5V
–
REXT = 100kΩ
GND
A1
For example, using this equation, the adjustment range is ±2%
for REXT = 5 MΩ and ±10% for REXT = 1 MΩ.
OUT
GAIN =
–IN
A2
Figure 30. Adjusting for Gains Greater than 14
OUTPUT
+
A1
NC = NO CONNECT
Because the preamplifier has an output resistance of 100 kΩ, an
external resistor connected from Pin 3 and Pin 4 to GND decreases
the gain by the following factor (see Figure 29):
VDIFF
GND
GAIN
GAIN – 14
+
VCM
Gains Less than 14
+IN
14REXT
REXT – 100kΩ
GAIN
14 – GAIN
OUTPUT
A2
+IN
+VS
NC
OUT
+
REXT
NC = NO CONNECT
+
VDIFF
AD8209
–
–IN
GND
A1
A2
Figure 29. Adjusting for Gains Less than 14
The overall bandwidth is unaffected by changes in gain by using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to the buffer. In
many cases, this can be ignored, but if desired, the offset voltage can
be nulled by inserting a resistor in series with Pin 4. The resistor
Rev. 0 | Page 12 of 16
+
VCM
REXT
GAIN TRIM
20kΩ MIN
–
NC = NO CONNECT
Figure 31. Incremental Gain Trimming
08461-033
–
08461-031
VCM
AD8209
Internal Signal Overload Considerations
When configuring the gain for values other than 14, the maximum
input voltage with respect to the supply voltage and ground must
be considered because either the preamplifier or the output buffer
reaches its full-scale output (VS − 0.1 V) with large differential
input voltages. The input of the AD8209 is limited to (VS − 0.1) ÷
7 for overall gains of ≤7 because the preamplifier, with its fixed
gain of 7 V/V, reaches its full-scale output before the output
buffer. For gains greater than 7, the swing at the buffer output
reaches its full scale first and then limits the AD8209 input to
(VS − 0.1) ÷ G, where G is the overall gain.
If the gain is raised using a resistor, as shown in Figure 30, the
corner frequency is lowered by the same factor as the gain is raised.
Therefore, using a resistor of 200 kΩ (for which the gain would
be doubled), results in a corner frequency scaled to 0.796 Hz μF
(0.039 μF for a 20 Hz corner frequency).
5V
OUTPUT
+IN
+
VDIFF
+VS
OUT
NC
C
AD8209
–
fC(Hz) = 1/C(µF)
LOW-PASS FILTERING
–IN
When implementing a filter, the PAR should be considered so
that the output of the AD8209 preamplifier (A1) does not clip
before A2; otherwise, the nonlinearity would be averaged and
appear as an error at the output. To avoid this error, both amplifiers
should clip at the same time. This condition is achieved when the
PAR is no greater than the gain of the second amplifier (2 for
the default configuration). For example, if a PAR of 5 is expected,
the gain of A2 should be increased to 5.
Low-pass filters can be implemented in several ways by using
the features provided by the AD8209. In the simplest case, a
single-pole filter (20 dB/decade) is formed when the output
of A1 is connected to the input of A2 via the internal 100 kΩ
resistor by tying Pin 3 to Pin 4 and adding a capacitor from this
node to ground, as shown in Figure 32. If a resistor is added
across the capacitor to lower the gain, the corner frequency
increases; therefore, gain should be calculated using the parallel
sum of the resistor and 100 kΩ.
+
VCM
A1
A2
255kΩ
–
08461-035
C
NC = NO CONNECT
Figure 33. Two-Pole, Low-Pass Filter
A two-pole filter with a roll-off of 40 dB/decade can be
implemented using the connections shown in Figure 33. This
configuration is a Sallen-Key form based on a ×2 amplifier. It is
useful to remember that a two-pole filter with a corner frequency
of f2 and a single-pole filter with a corner frequency of f1 have
the same attenuation, that is, 40 log (f2/f1), as shown in Figure 34.
Using the standard resistor value shown in Figure 33 and capacitors
of equal values, the corner frequency is conveniently scaled to
1 Hz μF (0.05 μF for a 20 Hz corner frequency). A maximal flat
response occurs when the resistor is lowered to 196 kΩ, scaling
the corner frequency to 1.145 Hz μF. The output offset is raised
by approximately 5 mV (equivalent to 250 μV at the input pins).
FREQUENCY
ATTENUATION
In many transducer applications, it is necessary to filter the signal
to remove spurious high frequency components, including noise,
or to extract the mean value of a fluctuating signal with a peakto-average ratio (PAR) greater than unity. For example, a full-wave
rectified sinusoid has a PAR of 1.57, a raised cosine has a PAR
of 2, and a half-wave sinusoid has a PAR of 3.14. Signals with
large spikes may have PARs of 10 or more.
GND
40dB/DECADE
20dB/DECADE
5V
40log (f2/f1)
OUTPUT
+
VDIFF
+VS
NC
OUT
A 1-POLE FILTER, CORNER f1, AND
A 2-POLE FILTER, CORNER f2, HAVE
THE SAME ATTENUATION –40log (f2/f1)
AT FREQUENCY f22/f1
1
fC = 2πC10 5
AD8209
–
08461-036
+IN
C IN FARADS
–IN
GND
A1
f1
A2
f2
f22/f1
Figure 34. Comparative Responses of Single-Pole and Two-Pole Low-Pass Filters
+
CF
–
NC = NO CONNECT
08461-034
VCM
Figure 32. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Resistor
Rev. 0 | Page 13 of 16
AD8209
diode regulates the common-mode potential applied to the device.
For example, a battery spike of 20 V may result in an applied
common-mode potential of 21.5 V to the input of the devices.
HIGH LINE CURRENT SENSING
WITH LPF AND GAIN ADJUSTMENT
The circuit shown in Figure 35 is similar to Figure 24, but
includes gain adjustment and low-pass filtering.
To produce a full-scale output of 4 V, a gain of 40 V/V is used,
adjustable by ±5% to absorb the tolerance in the shunt. There is
sufficient headroom to allow 10% overrange (to 4.4 V). The
roughly triangular voltage across the sense resistor is averaged
by a single-pole, low-pass filter that is set with a corner frequency
of 3.6 Hz, which provides about 30 dB of attenuation at 100 Hz.
A higher rate of attenuation can be obtained by using a two-pole
filter with a corner frequency of 20 Hz, as shown in Figure 36.
Although this circuit uses two separate capacitors, the total capacitance is less than half of what is needed for the single-pole filter.
5V
INDUCTIVE
LOAD
OUTPUT
4V/AMP
+IN
+VS
OUT
NC
+
BATTERY
133kΩ
–
SHUNT
AD8209
20kΩ
–IN
GND
A1
A2
SWITCH
VOS/IB
NULL
NC = NO CONNECT
5% CALIBRATION RANGE
fC(Hz) = 0.767Hz/C(µF)
(0.22µF FOR fC = 3.6Hz)
5V
08461-037
C
CLAMP
DIODE
Figure 35. High Line Current-Sensor Interface;
Gain = 40 V/V, Single-Pole, Low-Pass Filter
INDUCTIVE
LOAD
OUTPUT
+IN
+VS
NC
OUT
432kΩ
+
A power device that is either on or off controls the current in
the load. The average current is proportional to the duty cycle
of the input pulse and is sensed by a small-value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value is higher by an amount that depends on the
inductance of the load and the control frequency. The commonmode voltage, on the other hand, extends from roughly 1 V above
ground for the on condition to about 1.5 V above the battery
voltage in the off condition. The conduction of the clamping
BATTERY
–
SHUNT
C
AD8209
50kΩ
–IN
GND
A1
A2
SWITCH
93kΩ
C
fC(Hz) =1/C(µF)
(0.05µF FOR fC = 20Hz)
NC = NO CONNECT
Rev. 0 | Page 14 of 16
Figure 36. Two-Pole Low-Pass Filter
08461-038
CLAMP
DIODE
AD8209
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
0.80
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-AA
100709-B
0.15
0.05
COPLANARITY
0.10
Figure 37. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8209WBRMZ1
AD8209WBRMZ-R71
AD8209WBRMZ-RL1
1
Temperature Package
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
8-Lead Mini Small Outline Package (MSOP)
Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
Package Option
RM-8
RM-8
RM-8
Branding
Y26
Y26
Y26
AD8209
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08461-0-10/09(0)
Rev. 0 | Page 16 of 16