PD - 91644A
IRL1004S
IRL1004L
Logic-Level Gate Drive
Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
Description
l
HEXFET® Power MOSFET
l
D
VDSS = 40V
RDS(on) = 0.0065Ω
G
Fifth Generation HEXFET® power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer with
an extremely efficient and reliable device for use in a wide
variety of applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL1004L) is available for lowprofile application.
ID = 130A
S
D2Pak
IRL1004S
TO-262
IRL1004L
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TA = 25°C
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
130
92
520
3.8
200
1.3
± 16
700
78
20
5.0
-55 to + 175
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case)
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)*
Typ.
Max.
Units
–––
–––
0.75
40
°C/W
1
12/29/99
IRL1004S/1004L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
40
–––
–––
–––
1.0
63
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
V(BR)DSS
IGSS
Typ. Max. Units
Conditions
––– –––
V
V GS = 0V, ID = 250µA
0.04 ––– V/°C Reference to 25°C, I D = 1mA
––– 0.0065
VGS = 10V, ID = 78A
Ω
––– 0.009
VGS = 4.5V, ID = 65A
–––
V
VDS = V GS, ID = 250µA
––– –––
S
VDS = 25V, ID = 78A
––– 25
VDS = 40V, VGS = 0V
µA
––– 250
VDS = 32V, VGS = 0V, TJ = 150°C
––– 100
VGS = 16V
nA
––– -100
VGS = -16V
––– 100
ID = 78A
––– 32
nC
VDS = 32V
––– 43
VGS = 4.5V, See Fig. 6 and 13
16 –––
VDD = 20V,
210 –––
ID = 78A,
25 –––
ns
RG = 2.5Ω,
14 –––
RD = 0.18Ω, See Fig. 10
Between lead,
7.5
nH
–––
and center of die contact
5330 –––
VGS = 0V
1480 –––
pF
VDS = 25V
320 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 130
showing the
A
G
integral reverse
––– ––– 520
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 78A, VGS = 0V
––– 78 120
ns
TJ = 25°C, IF = 78A
––– 180 270
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. (See fig. 11)
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handing of the
package refer to Design Tip # 93-4
Starting TJ = 25°C, L = 0.23mH
RG = 25Ω, I AS = 78A. (See Figure 12)
ISD ≤ 78A, di/dt ≤ 370A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Uses IRL1004 data and test conditions
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRL1004S/1004L
10000
1000
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 2.7V
1000
100
100
10
1
2.7V
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
10
2.5
R DS(on) , Drain-to-Source On Resistance
(Normalized)
TJ = 25 ° C
TJ = 175 ° C
10
1
V DS = 50V
20µs PULSE WIDTH
3.0
4.0
5.0
6.0
7.0
8.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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1
10
100
Fig 2. Typical Output Characteristics
1000
0.1
2.0
20µs PULSE WIDTH
TJ = 175 ° C
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
2.7V
1
0.1
100
VDS , Drain-to-Source Voltage (V)
I D , Drain-to-Source Current (A)
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 2.7V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
9.0
ID = 130A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRL1004S/1004L
10000
VGS , Gate-to-Source Voltage (V)
8000
C, Capacitance (pF)
12
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Ciss
6000
Coss
4000
2000
Crss
ID = 78 A
10
8
6
4
2
0
FOR TEST CIRCUIT
SEE FIGURE 13
0
1
10
100
0
VDS , Drain-to-Source Voltage (V)
60
90
120
150
180
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
TJ = 175 ° C
100
1000
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
30
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10
10us
100us
100
TJ = 25 ° C
1
1ms
10ms
10
0.1
0.0
V GS = 0 V
0.5
1.0
1.5
2.0
2.5
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS = 32V
VDS = 20V
3.0
TC = 25 °C
TJ = 175 °C
Single Pulse
1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL1004S/1004L
140
RD
VDS
LIMITED BY PACKAGE
VGS
120
D.U.T.
I D , Drain Current (A)
RG
+
-VDD
100
10V
80
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
60
Fig 10a. Switching Time Test Circuit
40
VDS
20
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
P DM
0.05
t1
0.02
0.01
t2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL1004S/1004L
L
D.U.T.
RG
VDD
tp
BOTTOM
ID
32A
55A
78A
1200
IAS
4.5 V
TOP
1500
+
-
EAS , Single Pulse Avalanche Energy (mJ)
1800
VDS
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
900
600
300
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
VDD
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
VDS
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
4.5 V
QGS
QGD
D.U.T.
+
V
- DS
VGS
VG
3mA
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRL1004S/1004L
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D=
Period
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-channel HEXFET® Power MOSFETs
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7
IRL1004S/1004L
D2Pak Package Outline
1 0.54 (.415 )
1 0.29 (.405 )
1.4 0 (.055 )
M AX.
-A-
1.3 2 (.05 2)
1.2 2 (.04 8)
2
1.7 8 (.07 0)
1.2 7 (.05 0)
1
10 .1 6 (.4 00 )
R E F.
-B-
4 .6 9 (.18 5)
4 .2 0 (.16 5)
6.47 (.2 55 )
6.18 (.2 43 )
1 5.49 (.6 10)
1 4.73 (.5 80)
3
2.7 9 (.110 )
2.2 9 (.090 )
2.61 (.1 03 )
2.32 (.0 91 )
5.28 (.2 08 )
4.78 (.1 88 )
3X
1.40 (.0 55)
1.14 (.0 45)
3X
5 .08 (.20 0)
0.55 (.0 22)
0.46 (.0 18)
0.9 3 (.0 37 )
0.6 9 (.0 27 )
0.25 (.0 10 )
M
8.8 9 (.3 50 )
R E F.
1.3 9 (.0 55 )
1.1 4 (.0 45 )
B A M
M IN IM U M R EC O M M E ND E D F O O TP R IN T
1 1.43 (.4 50 )
NO TE S:
1 D IM EN S IO N S A FTER SO LD E R D IP .
2 D IM EN S IO N IN G & TO LE R AN C IN G P ER AN S I Y1 4.5M , 19 82 .
3 C O N TRO L LIN G D IM EN S IO N : IN C H.
4 H E ATSINK & L EA D D IM E N SIO N S DO N O T IN C LU D E B U R RS .
LE AD AS SIG N M E N TS
1 - G ATE
2 - D RA IN
3 - SO U R C E
8 .89 (.35 0)
17 .78 (.70 0)
3.81 (.1 5 0)
2.0 8 (.08 2)
2X
2.5 4 (.100 )
2X
D2Pak Part Marking Information
IN TE R N A TIO N A L
R E C T IF IE R
LO G O
A S S E M B LY
LO T C O D E
8
A
PART NUM BER
F530S
9 24 6
9B
1M
DATE CODE
(Y YW W )
YY = Y E A R
W W = W EEK
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IRL1004S/1004L
TO-262 Package Outline
TO-262 Part Marking Information
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9
IRL1004S/1004L
D2Pak Tape & Reel Information
TR R
1 .6 0 (.0 6 3 )
1 .5 0 (.0 5 9 )
4 .1 0 (.1 6 1 )
3 .9 0 (.1 5 3 )
F EE D D IR E C T IO N 1 .8 5 (.0 7 3 )
1 .6 5 (.0 6 5 )
1 .6 0 (.0 6 3 )
1 .5 0 (.0 5 9 )
1 1 .6 0 (.4 5 7 )
1 1 .4 0 (.4 4 9 )
0 .3 6 8 (.0 1 4 5 )
0 .3 4 2 (.0 1 3 5 )
1 5 .4 2 (.6 0 9 )
1 5 .2 2 (.6 0 1 )
2 4 .3 0 (.9 5 7 )
2 3 .9 0 (.9 4 1 )
TRL
1 0 .9 0 (.4 2 9 )
1 0 .7 0 (.4 2 1 )
1 .7 5 (.0 6 9 )
1 .2 5 (.0 4 9 )
4 .7 2 (.1 3 6 )
4 .5 2 (.1 7 8 )
1 6 .1 0 (.6 3 4 )
1 5 .9 0 (.6 2 6 )
F E E D D IR E C T IO N
1 3.5 0 (.5 32 )
1 2.8 0 (.5 04 )
2 7 .4 0 (1 .0 79 )
2 3 .9 0 (.9 4 1)
4
3 3 0 .0 0
(1 4 .1 7 3)
M A X.
N OT ES :
1. C O M F O R M S T O E IA -4 1 8 .
2. C O N T R O L L IN G D IM E N S IO N : M IL L IM E T E R .
3. D IM E N S IO N M E A S U R E D @ H U B .
4. IN C L U D E S F LA N G E D IS T O R T IO N @ O U T E R E D G E .
6 0 .0 0 (2 .3 6 2)
M IN .
2 6 .4 0 (1 .0 3 9 )
2 4 .4 0 (.9 6 1 )
3
3 0 .4 0 (1 .1 97 )
M AX .
4
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252 7105
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
Data and specifications subject to change without notice. 12/99
10
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