MCNIX MX23L8111TC-12 8m-bit mask rom(8/16 bit output) Datasheet

MX23L8111
8M-BIT MASK ROM(8/16 BIT OUTPUT)
FEATURES
ORDER INFORMATION
• Bit organization
- 1M x 8 (byte mode)
- 512K x 16 (word mode)
• Fast access time
- Random access: 100ns (max.)
- Page access: 30ns (max.)
• Current
- Operating: 20mA
- Standby: 20uA
• Supply voltage
- 100ns @3.0V ~ 3.6V
- 120ns @2.7V ~ 3.6V
• Package
- 44 pin SOP (500mil)
- 42 pin PDIP (600mil)
- 48 pin TSOP (type 1)
- 44 pin TSOP (type 2)
Part No.
Access
Page
Time
Access Time
Package
MX23L8111MC-10 100ns
30ns
44 pin SOP
MX23L8111MC-12 120ns
60ns
44 pin SOP
MX23L8111PC-10
100ns
30ns
42 pin PDIP
MX23L8111PC-12
120ns
60ns
42 pin PDIP
MX23L8111TC-10
100ns
50ns
48 pin TSOP
MX23L8111TC-12
120ns
60ns
48 pin TSOP
MX23L8111RC-10
100ns
50ns
48 pin RTSOP
MX23L8111RC-12
120ns
60ns
48 pin RTSOP
MX23L8111YC-10
100ns
50ns
44 pin TSOP
MX23L8111YC-12
120ns
60ns
44 pin TSOP
Note: 48-TSOP and 48-RTSOP support word mode only, not
for byte mode.
PIN CONFIGURATION
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
42PDIP
NC
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
48 TSOP (for word mode only)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MX23L8111
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
MX23L8111
44 SOP/44TSOP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NC
A16
A15
A14
A13
A12
A11
A10
A9
A8
NC
VSS
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
NC
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX23L8111
(Normal Type)
VSS
VSS
D15
D7
D14
D6
D13
D5
D12
D4
VCC
VCC
NC
D11
D3
D10
D2
D9
D1
D8
D0
OE
VSS
VSS
48 Reverse TSOP (for word mode only)
VSS
VSS
D15
D7
D14
D6
D13
D5
D12
D4
VCC
VCC
NC
D11
D3
D10
D2
D9
D1
D8
D0
OE
VSS
VSS
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48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX23L8111
(Reverse Type)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
A16
A15
A14
A13
A12
A11
A10
A9
A8
NC
VSS
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
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MX23L8111
PIN DESCRIPTION
Symbol
A0~A18
D0~D14
D15/A-1
MODE SELECTION
CE
OE
Byte
VCC
VSS
Pin Function
Address Inputs
Data Outputs
D15(Word Mode)/LSB Address (Byte
Mode)
Chip Enable Input
Output Enable Input
Word/Byte Mode Selection
Power Supply Pin
Ground Pin
NC
No Connection
CE OE Byte D15/A-1 D0~D7 D8~D15 Mode
Power
H
X
X
X
High Z
High Z
-
Stand-by
L
H
X
X
High Z
High Z
-
Active
L
L
H
L
L
L
Output D0~D7 D8~D15 Word
Input
D0~D7
High Z
Byte
Active
Active
BLOCK DIAGRAM
A0/(A-1)
A2
A3
Address
Buffer
Memory
Array
Page
Decoder
Page
Buffer
Double
Word
D0
Output
Buffer
D15/(D7)
A18
CE
BYTE
OE
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any Pin Relative to VSS
Ambient Operating Temperature
Storage Temperature
Symbol
VIN
Topr
Tstg
Ratings
-1.3V to VCC+2.0V (Note)
0° C to 70° C
-65° C to 125° C
Note: Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -1.3V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns.
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MX23L8111
DC CHARACTERISTICS (Ta = 0° C ~ 70° C, VCC = 3.3V±10%)
Item
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current (TTL)
Standby Current (CMOS)
Input Capacitance
Output Capacitance
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
ICC1
ISTB1
ISTB2
CIN
COUT
MIN.
24V
2.2V
-0.3V
-
MAX.
0.4V
VCC+0.3V
0.8V
5uA
5uA
20mA
1mA
20uA
10pF
10pF
Conditions
IOH = -0.4mA
IOL = 1.6mA
0V, VCC
0V, VCC
f=10MHz, all output open
CE=VIH
CE> VCC - 0.2V
Ta = 25° C, f = 1MHZ
Ta = 25° C, f = 1MHZ
AC CHARACTERISTICS (Ta = 0° C ~ 70° C, VCC = 3.3V±10%)
Item
Symbol
Read Cycle Time
Address Access Time
Chip Enable Access Time
Page Mode Access Time
Output Enable Time
Output Hold After Address
Output High Z Delay
tRC
tAA
tACE
tPA
tOE
tOH
tHZ
23L8111-10
MIN.
MAX.
100ns
100ns
100ns
30ns*
30ns*
0ns
20ns
23L8111-12
MIN.
MAX.
120ns
120ns
120ns
60ns
60ns
0ns
20ns
Note: Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by
design over the full voltage and temperature operating range - not tested.
* For 100ns speed grade, tPA and tOE spec are 30ns for PDIP and SOP package types, but 50ns for TSOP package
type.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Level
Output Timing Level
Output Load
IOH (load)=-0.4mA
0.4V~2.4V
10ns
1.4V
1.4V
See Figure
DOUT
IOL (load)=1.6mA
C<100pF
Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
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MX23L8111
TIMING DIAGRAM
RANDOM READ
ADD
ADD
ADD
ADD
tRC
tACE
CE
tOE
OE
tOH
tAA
VALID
DATA
VALID
tHZ
VALID
PAGE READ
VALID ADD
A3-A18
(A-1),A0,A1,A2
2'nd ADD
1'st ADD
tAA
DATA
3'rd ADD
tPA
VALID
VALID
VALID
Note: CE, OE are enable.
Page size is 8 words in 16-bit mode, 16 bytes in 8-bit mode.
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MX23L8111
PACKAGE INFORMATION
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MX23L8111
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MX23L8111
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MX23L8111
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MX23L8111
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MX23L8111
REVISION HISTORY
Revision
1.8
1.9
2.0
2.1
2.2
2.3
Description
Add new 44pin TSOP(type2)
Output hold after address (tOH) spec is revised as 0ns(min.)
120ns speed grade's voltage range is revised as 2.7V~3.6V
Add Package Information
Modify page access:50ns(max.)-->30ns(max.)
Modify Package Information
Modify 42-PDIP Package Information
P/N:PM0412
Page
P3
P1
P5~9
P1,3
P5~9
P5
Date
JUL/17/1998
JAN/22/1999
NOV/23/2001
MAY/24/2002
NOV/21/2002
JUN/19/2003
REV. 2.3, JUN. 19, 2003
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MX23L8111
MACRONIX INTERNATIONAL CO., LTD.
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TEL:+1-408-262-8887
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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