STMicroelectronics M59DR032E-ZBE 32 mbit (2mb x 16, dual bank, page ) 1.8v supply flash memory Datasheet

M59DR032EA
M59DR032EB
32 Mbit (2Mb x 16, Dual Bank, Page )
1.8V Supply Flash Memory
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– VDD = VDDQ = 1.65V to 2.2V for Program,
Erase and Read
■
– VPP = 12V for fast Program (optional)
ASYNCHRONOUS PAGE MODE READ
BGA
– Page Width: 4 Words
– Page Access: 35ns
– Random Access: 85ns, 100ns and 120ns
■
PROGRAMMING TIME
– 10µs by Word typical
TFBGA48 (ZB)
7 x 12mm
– Double Word Program Option
■
MEMORY BLOCKS
– Dual Bank Memory Array: 4 Mbit, 28 Mbit
– Parameter Blocks (Top or Bottom location)
■
BGA
DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
■
BLOCK LOCKING
TFBGA48 (ZF)
7 x 7mm
– All blocks locked at Power up
– Any combination of blocks can be locked
– WP for Block Lock-Down
■
COMMON FLASH INTERFACE (CFI)
– 64 bit Unique Device Identifier
– 64 bit User Programmable OTP Cells
■
ERASE SUSPEND and RESUME MODES
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code, M59DR032EA: 00A0h
– Bottom Device Code, M59DR032EB: 00A1h
April 2003
1/43
M59DR032EA, M59DR032EB
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Bank Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset/Power-Down Input (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VDD and VDDQ Supply Voltage (1.65V to 2.2V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VPP Programming Voltage (11.4V to 12.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dual Bank Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Quadruple Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Enter Bypass Mode Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Exit Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Double Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Quadruple Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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M59DR032EA, M59DR032EB
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Read Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 15
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. Testing Input/Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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M59DR032EA, M59DR032EB
Figure 11. Reset/Power-Down AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Reset/Power-Down AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Data Polling DQ7 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. Data Toggle DQ6, DQ2 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. Data Polling and Toggle Bits AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Outline . . . . . . . . . . . . . . 32
Table 22. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . 32
Figure 17. TFBGA48 7x7mm - 8x6 ball array, 0.75 mm pitch, Package Outline . . . . . . . . . . . . . . . 33
Table 23. TFBGA48 7x7mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . . . . 33
Figure 18. TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 34
Figure 19. TFBGA48 Daisy Chain - PCB Connection Proposal (Top view through package). . . . . 34
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 25. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 26. Bank A, Top Boot Block Addresses M59DR032EA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 27. Bank B, Top Boot Block Addresses M59DR032EA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 28. Bank B, Bottom Boot Block Addresses M59DR032EB . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 29. Bank A, Bottom Boot Block Addresses M59DR032EB . . . . . . . . . . . . . . . . . . . . . . . . . . 38
APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 31. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 33. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 34. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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M59DR032EA, M59DR032EB
SUMMARY DESCRIPTION
The M59DR032E is a 32 Mbit (2Mbit x16) non-volatile Flash memory that may be erased electrically
at block level and programmed in-system on a
Word-by-Word basis using a 1.65V to 2.2V V DD
supply for the circuitry and a 1.65V to 2.2V V DDQ
supply for the Input/Output pins. An optional 12V
VPP power supply is provided to speed up customer programming.
The device features an asymmetrical block architecture. M59DR032E has an array of 71 blocks
and is divided into two banks, Banks A and B, providing Dual Bank operations. While programming
or erasing in Bank A, read operations are possible
in Bank B or vice versa. Only one bank at a time is
allowed to be in program or erase mode. The bank
architecture is summarized in Table 2, and the
Block Addresses are shown in Appendix A. The
Parameter Blocks are located at the top of the
memory address space for the M59DR032EA,
and at the bottom for the M59DR032EB.
Each block can be erased separately. Erase can
be suspended, in order to perform either read or
program in any other block, and then resumed.
Each block can be programmed and erased over
100,000 cycles.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the timings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC standards.
The M59DR032E features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling instant code and data protection. All blocks have two
levels of protection. They can be individually
locked and locked-down preventing any accidental programming or erasure. All blocks are locked
at Power Up and Reset.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system’s design. The Protection Register is divided into two 64 bit segments. The first segment
contains a unique device number written by ST,
while the second one is one-time-programmable
by the user. The user programmable segment can
be permanently protected. The Security Block, parameter block 0, can be permanently protected by
the user. Figure 4, shows the Security Block and
Protection Register Memory Map.
The device is available in TFBGA48 (7 x 12mm
and 7 x 7mm, 0.75mm pitch) packages and it is
supplied with all the bits erased (set to ‘1’).
Figure 2. Logic Diagram
VDD VDDQ VPP
21
16
A0-A20
DQ0-DQ15
W
E
G
M59DR032EA
M59DR032EB
RP
WP
VSS
AI06188
Table 1. Signal Names
A0-A20
Address Inputs
DQ0-DQ15
Data Input/Outputs, Command Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Power-Down
WP
Write Protect
VDD
Supply Voltage
VDDQ
Supply Voltage for Input/Output
Buffers
VPP
Optional Supply Voltage for
Fast Program & Erase
VSS
Ground
NC
Not Connected Internally
5/43
M59DR032EA, M59DR032EB
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A13
A11
A8
VPP
WP
A19
A7
A4
B
A14
A10
W
RP
A18
A17
A5
A2
C
A15
A12
A9
NC
A20
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI06184
Table 2. Bank Organization
6/43
Bank Size
Parameter Blocks
Main Blocks
Bank A
4 Mbit
8 blocks of 4 KWord
7 blocks of 32 KWord
Bank B
28 Mbit
-
56 blocks of 32 KWord
M59DR032EA, M59DR032EB
Figure 4. Security Block and Protection Register Memory Map
PROTECTION REGISTER
88h
SECURITY BLOCK
User Programmable OTP
85h
84h
Parameter Block # 0
Unique device number
81h
80h
Protection Register Lock
2
1
0
AI06185
7/43
M59DR032EA, M59DR032EB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
During a write operation the address inputs are
latched on the falling edge of Chip Enable E or
Write Enable W, whichever occurs last.
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address during a Bus Read operation or input a command or
the data to be programmed during a Write Bus operation.
Both input data and commands are latched on the
rising edge of Write Enable W. The data output is
the Memory Array, the Common Flash Interface,
the Electronic Signature Manufacturer or Device
codes, the Block Protection status, the Configuration Register status or the Status Register Data
depending on the address.
The data bus is high impedance when the chip is
deselected, Output Enable G is at VIH, or RP is at
VIL.
Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is
at VIH the device is deselected and the power consumption is reduced to the standby level.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read operation. When Output Enable is at V IH the outputs
are high impedance.
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at V IL, the
locked-down blocks cannot be locked or unlocked.
When Write Protect is at VIH, the Lock-Down is
disabled and the locked-down blocks can be
locked or unlocked. (refer to Table 10, Lock Status).
8/43
Reset/Power-Down Input (RP). The Reset/Power-Down input provides hardware reset of the
memory, and/or Power-Down functions, depending on the Configuration Register status. A Reset
or Power-Down of the memory is achieved by pulling RP to VIL for at least tPLPH.
The Reset/Power-Down function is set in the Configuration Register (see Set Configuration Register command). If it is set to ‘0’ the Reset function is
enabled, if it is set to ‘1’ the Power-Down function
is enabled. After a Reset or Power-Up the power
save function is disabled and all blocks are locked.
The memory Command Interface is reset on Power Up to Read Array. Either Chip Enable or Write
Enable must be tied to VIH during Power Up to allow maximum security and the possibility to write a
command on the first rising edge of Write Enable.
After a Reset, when the device is in Read, Erase
Suspend Read or Standby, valid data will be output tPHQ7V1 after the rising edge of RP. If the device is in Erase or Program, the operation will be
aborted and the reset recovery will take a maximum of t PLQ7V. The memory will recover from
Power-Down tPHQ7V2 after the rising edge of RP.
See Tables 17, 18 and Figure 11.
VDD and VDDQ Supply Voltage (1.65V to 2.2V).
VDD provides the power supply to the internal core
of the memory device. It is the main power supply
for all operations (read, program and erase).
VDDQ provides the power supply to the I/O pins.
VDD and V DDQ must be at the same voltage.
VPP Programming Voltage (11.4V to 12.6V). VPP
provides a high voltage power supply for fast factory programming. VPP is required to use the Double Word and Quadruple Word Program
commands.
VSS Ground. VSS ground is the reference for the
core supply. It must be connected to the system
ground.
Note: Each device in a system should have
VDD, VDDQ and V PP decoupled with a 0.1µF capacitor close to the pin. See Figure 6, AC Measurement Load Circuit. The PCB trace widths
should be sufficient to carry the required VPP
program and erase currents.
M59DR032EA, M59DR032EB
BUS OPERATIONS
The following operations can be performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write, Output Disable, Standby
and Reset/Power-Down, see Table 3.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Signature, the Status Register, the CFI, the Block
Protection Status or the Configuration Register
status. Read operation of the memory array is performed in asynchronous page mode, that provides
fast access time. Data is internally read and stored
in a page buffer. The page has a size of 4 words
and is addressed by A0-A1 address inputs. Read
operations of the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performed as single asynchronous read
cycles (Random Read). Both Chip Enable E and
Output Enable G must be at VIL in order to read the
output of the memory.
Write. Write operations are used to give commands to the memory or to latch Input Data to be
programmed. A write operation is initiated when
Chip Enable E and Write Enable W are at V IL with
Output Enable G at V IH. Addresses are latched on
the falling edge of W or E whichever occurs last.
Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Noise
pulses of less than 5ns typical on E, W and G signals do not start a write cycle.
Output Disable. The data outputs are high impedance when the Output Enable G is at VIH with
Write Enable W at VIH.
Standby. The memory is in standby when Chip
Enable E is at VIH and the P/E.C. is idle. The power consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
Automatic Standby. In Read mode, after 150ns
of bus inactivity and when CMOS levels are driving
the addresses, the chip automatically enters a
pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs
still drive the bus.
Power-Down. The memory is in Power-Down
when the Configuration Register is set for PowerDown and RP is at VIL. The power consumption is
reduced to the Power-Down level, and Outputs are
in high impedance, independent of the Chip Enable E, Output Enable G or Write Enable W inputs.
Dual Bank Operations. The Dual Bank allows
data to be read from one bank of memory while a
program or erase operation is in progress in the
other bank of the memory. Read and Write cycles
can be initiated for simultaneous operations in different banks without any delay. Status Register
during Program or Erase must be monitored using
an address within the bank being modified.
Table 3. Bus Operations
Operation
E
G
W
RP
WP
DQ15-DQ0
Read
VIL
VIL
VIH
VIH
VIH
Data Output
Write
VIL
VIH
VIL
VIH
VIH
Data Input
Output Disable
VIL
VIH
VIH
VIH
VIH
Hi-Z
Standby
VIH
X
X
VIH
VIH
Hi-Z
X
X
X
VIL
VIH
Hi-Z
Reset / Power-Down
Note: X = Don’t care.
9/43
M59DR032EA, M59DR032EB
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution
of the Program and Erase commands. Two bus
write cycles are required to unlock the Command
Interface. They are followed by a setup or confirm
cycle. The increased number of write cycles is to
ensure maximum data security.
The Program/Erase Controller provides a Status
Register whose output may be read at any time to
monitor the progress or the result of the operation.
The Command Interface is reset to Read mode
when power is first applied or exiting from Reset.
Command sequences must be followed exactly.
Any invalid combination of commands will reset
the device to Read mode
Read/Reset Command. The Read/Reset command returns the device to Read mode. One Bus
Write cycle is required to issue the Read/Reset
command and return the device to Read mode.
Subsequent Read operations will read the addressed location and output the data. The write cycle can be preceded by the unlock cycles but it is
not mandatory.
Read CFI Query Command. The Read CFI
Query command is used to read data from the
Common Flash Interface (CFI) and the Electronic
Signature (Manufacturer or the Device Code, see
Table 5). The Read CFI Query Command consists
of one Bus Write cycle. Once the command is issued the device enters Read CFI mode. Subsequent Bus Read operations read the Common
Flash Interface or Electronic Signature. Once the
device has entered Read CFI mode, only the
Read/Reset command should be used and no other. Issuing the Read/Reset command returns the
device to Read mode.
See Appendix B, Common Flash Interface, Tables
31, 32, and 33 for details on the information contained in the Common Flash Interface memory area.
Auto Select Command. The Auto Select command uses the two unlock cycles followed by one
write cycle to any bank address to setup the command. Subsequent reads at any address will output the Block Protection status, Protection
Register and Protection Register Lock or the Configuration Register status depending on the levels
of A0 and A1 (see Tables 6, 7 and 8). Once the
Auto Select command has been issued only the
Read/Reset command should be used and no other. Issuing the Read/Reset command returns the
device to Read mode.
10/43
Set Configuration Register Command. The
M59DR032E contains a Configuration Register,
see Table 7, Configuration Register.
It is used to define the status of the Reset/PowerDown functions. The value for the Configuration
Register is always presented on A0-A15, the other
address bits are ignored. Address input A10 defines the status of the Reset/Power-Down functions. If it is set to ‘0’ the Reset function is enabled,
if it is set to ‘1’ the Power-Down function is enabled. At Power Up the Configuration Register bit
is set to ‘0’.
The Set Configuration Register command is used
to write a new value to the Configuration Register.
The command uses the two unlock cycles followed
by one write cycle to setup the command and a
further write cycle to write the data and confirm the
command.
Program Command. The Program command
uses the two unlock cycles followed by a write cycle to set up the command and a further write cycle
to latch the Address and Data and start the Program Erase Controller. Read operations within the
same bank output the Status Register after programming has started.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole bank from ’0’ to ’1’. If the Program
command is used to try to set a bit from ‘0’ to ‘1’
Status Register Error bit DQ5 will be set to ‘1’, only
if VPP is in the range of 11.4V to 12.6V.
Double Word Program Command. This feature
is offered to improve the programming throughput
by writing a page of two adjacent Words in parallel.
The V PP supply voltage is required to be from
11.4V to 12.6V for the Double Word Program command.
The command uses the two unlock cycles followed
by a write cycle to set up the command. A further
two cycles are required to latch the address and
data of the two Words and start the Program Erase
Controller.
The addresses must be the same except for the
A0. The Double Word Program command can be
executed in Bypass mode to skip the two unlock
cycles.
Note that the Double Word Program command
cannot change a bit set to ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Double Word Program command is used to try to
set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5
will be set to ‘1’.
Quadruple Word Program Command. The
Quadruple Word Program command improves the
M59DR032EA, M59DR032EB
programming throughput by writing a page of four
adjacent Words in parallel. The four Words must
differ only for the addresses A0 and A1. The VPP
supply voltage is required to be from 11.4V to
12.6V for the Quadruple Word Program command.
The command uses the two unlock cycles followed
by a write cycle to set up the command. A further
four cycles are required to latch the address and
data of the four Words and start the Program
Erase Controller.
The Quadruple Word Program command can be
executed in Bypass mode to skip the two unlock
cycles.
Note that the Quadruple Word Program command
cannot change a bit set to ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Quadruple Word Program command is used to try
to set a bit from ‘0’ to ‘1’ Status Register Error bit
DQ5 will be set to ‘1’.
Enter Bypass Mode Command. The
Bypass
mode is used to reduce the overall programming
time when large memory arrays need to be programmed.
The Enter Bypass Mode command uses the two
unlock cycles followed by one write cycle to set up
the command. Once in Bypass mode, it is imperative that only the following commands be issued:
Exit Bypass, Program, Double Word Program or
Quadruple Word Program.
Exit Bypass Mode Command. The Exit Bypass
Mode command uses two write cycles to be set up
and confirmed. The unlock cycles are not required.
After the Exit Bypass Mode command, the device
resets to Read mode.
Program in Bypass Mode Command. The
Program in Bypass Mode command can be issued when the device is in Bypass mode (issue an
Enter Bypass Mode command). It uses the same
sequence of cycles as the Program command with
the exception of the unlock cycles.
Double Word Program in Bypass Mode Command. The Double Word Program in Bypass
Mode command can be issued when the device is
in Bypass mode (issue an Enter Bypass Mode
command). It uses the same sequence of cycles
as the Double Word Program command with the
exception of the unlock cycles.
Quadruple Word Program in Bypass Mode
Command. The Quadruple Word Program in Bypass Mode command can be issued when the device is in Bypass mode (issue an Enter Bypass
Mode command). It uses the same sequence of
cycles as the Quadruple Word Program command
with the exception of the unlock cycles.
Block Lock Command. The Block Lock command is used to lock a block and prevent Program
or Erase operations from changing the data in it.
All blocks are locked at Power-Up or Reset.
Three Bus Write cycles are required to issue the
Block Lock command.
■ The first two bus cycles unlock the Command
Interface.
■ The third bus cycle sets up the Block Lock
command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Table 10 shows
the Lock Status after issuing a Block Lock command.
The Block Lock bits are volatile, once set they remain set until a hardware Reset or Power-Down/
Power-Up. They are cleared by a Block Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.
Block Unlock Command. The Block Unlock
command is used to unlock a block, allowing the
block to be programmed or erased.
Three Bus Write cycles are required to issue the
Block Unlock command.
■ The first two bus cycles unlock the Command
Interface.
■ The third bus cycle sets up the Block UnLock
command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Table 10 shows
the lock status after issuing a Block Unlock command. Refer to the section, Block Locking, for a
detailed explanation.
Block Lock-Down Command. A locked or unlocked block can be locked-down by issuing the
Block Lock-Down command. A locked-down block
cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When
WP is high, V IH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command.
Three Bus Write cycles are required to issue the
Block Lock-Down command.
■ The first two bus cycles unlock the Command
Interface.
■ The third bus cycle sets up the Block LockDown command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Locked-Down
blocks revert to the locked (and not locked-down)
state when the device is reset on power-down. Table 10 shows the Lock Status after issuing a Block
Lock-Down command. Refer to the section, Block
Locking, for a detailed explanation.
11/43
M59DR032EA, M59DR032EB
Block Erase Command. The Block Erase command can be used to erase a block. It sets all the
bits within the selected block to ’1’. All previous
data in the block is lost. If the block is protected
then the Erase operation will abort, the data in the
block will not be changed and the device will return
to Read Array mode. It is not necessary to pre-program the block as the Program/Erase Controller
does it automatically before erasing.
Six Bus Write cycles are required to issue the
command.
■ The first two write cycles unlock the Command
Interface.
■ The third write cycles sets up the command
■ the fourth and fifth write cycles repeat the unlock
sequence
■ the sixth write cycle latches the block address
and confirms the command.
Additional Block Erase confirm cycles can be issued to erase other blocks without further unlock
cycles. All blocks must belong to the same bank; if
a new block belonging to the other bank is given,
the operation is aborted.
The additional Block Erase confirm cycles must be
given within the DQ3 erase timeout period. Each
time a new confirm cycle is issued the timeout period restarts. The status of the internal timer can
be monitored through the level of DQ3, see Status
Register section for more details.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.
After the command has been issued the Read/Reset command will be accepted during the DQ3 timeout period, after that only the Erase Suspend
command will be accepted.
On successful completion of the Block Erase command, the device returns to Read Array mode.
Bank Erase Command. The Bank Erase command can be used to erase a bank. It sets all the
bits within the selected bank to ’1’. All previous
data in the bank is lost. The Bank Erase command
will ignore any protected blocks within the bank. If
all blocks in the bank are protected then the Bank
Erase operation will abort and the data in the bank
will not be changed. It is not necessary to pre-program the bank as the Program/Erase Controller
does it automatically before erasing.
As for the Block Erase command six Bus Write cycles are required to issue the command.
■ The first two write cycles unlock the Command
Interface.
■ The third write cycles sets up the command
■ the fourth and fifth write cycles repeat the unlock
sequence
12/43
the sixth write cycle latches the block address
and confirms the command.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.
For optimum performance, Bank Erase commands should be limited to a maximum of 100 Program/Erase cycles per Block. After 100 Program/
Erase cycles the internal algorithm will still operate
properly but some degradation in performance
may occur.
Dual operations are not supported during Bank
Erase operations and the command cannot be
suspended.
On successful completion of the Bank Erase command, the device returns to Read Array mode.
Erase Suspend Command. The Erase Suspend
command is used to pause a Block Erase operation. In a Dual Bank memory it can be used to read
data within the bank where an Erase operation is
in progress. It is also possible to program data in
blocks not being erased.
One bus write cycle is required to issue the Erase
Suspend command. The Program/Erase Controller suspends the Erase operation within 20µs of
the Erase Suspend command being issued and
bits 7, 6 and/ or 2 of the Status Register are set to
‘1’. The device is then automatically set to Read
mode. The command can be addressed to any
bank.
During Erase Suspend the memory will accept the
Erase Resume, Program, Read CFI Query, Auto
Select, Block Lock, Block Unlock and Block LockDown commands.
Erase Resume Command. The Erase Resume
command can be used to restart the Program/
Erase Controller after an Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command must
be issued to an address within the bank being
erased. The unlock cycles are not required.
Protection Register Program Command. The
Protection Register Program command is used to
Program the Protection Register (One-Time-Programmable (OTP) segment and Protection Register Lock). The OTP segment is programmed 16
bits at a time. When shipped all bits in the segment
are set to ‘1’. The user can only program the bits
to ‘0’.
Four write cycles are required to issue the Protection Register Program command.
■ The first two bus cycles unlock the Command
Interface.
■ The third bus cycle sets up the Protection
Register Program command.
■
M59DR032EA, M59DR032EB
The fourth latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The OTP segment can be protected by programming bit 1 of the Protection Register Lock. The
segment can be protected by programming bit 1 of
the Protection Register Lock. Bit 1 of the Protection Register Lock also protects bit 2 of the Protec-
tion Register Lock. Programming bit 2 of the
Protection Register Lock will result in a permanent
protection of Parameter Block #0 (see Figure 4,
Security Block and Protection Register Memory
Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection
Register and/or the Security Block is not reversible.
■
Commands
No of Cycles
Table 4. Commands
1+
Read/Reset
Bus Operations
1st
2nd
3rd
Add Data Add Data Add
X
F0h
4th
5th
6th
7th
Dat
Add Data Add Data Add Data Add Data
a
Read Memory Array until a new write cycle is initiated.
AAh 2AAh 55h
CFI Query
1+
98h
Auto Select
3+ 555h
AAh 2AAh 55h
555h 90h
Set Configuration
Register
4 555h
AAh 2AAh 55h
555h 60h CRD
03h
Program
4 555h
AAh 2AAh 55h
555h A0h
PD
Double Word Program
5 555h
AAh 2AAh 55h
555h 40h PA1
PD1 PA2
PD2
Quadruple Word
Program
5 555h
AAh 2AAh 55h
555h 50h PA1
PD1 PA2
PD2
Enter Bypass Mode
3 555h
AAh 2AAh 55h
555h 20h
Exit Bypass Mode
2
X
90h
X
00h
Program in Bypass
Mode
2
X
A0h
PA
PD
Double Word Program
in Bypass Mode
3
X
40h
PA1
PD1
PA2 PD2
Quadruple Word
Program in Bypass
Mode
3
X
50h
PA1
PD1
PA2 PD2 PA3
PD3
Block Lock
4 555h
AAh 2AAh 55h
555h 60h
BA
01h
Block Unlock
4 555h
AAh 2AAh 55h
555h 60h
BA
D0h
Block Lock-Down
4 555h
AAh 2AAh 55h
555h 60h
BA
2Fh
Block Erase
6+ 555h
AAh 2AAh 55h
555h 80h 555h AAh 2AAh 55h
BA
30h
Bank Erase
6 555h
AAh 2AAh 55h
555h 80h 555h AAh 2AAh 55h
BA
10h
Erase Suspend
1
X
B0h
Read until Toggle stops, then read all the data needed from any Blocks not
being erased then Resume Erase.
Erase Resume
1
BA
30h
Read Data Polling or Toggle Bits until Erase completes or Erase is
suspended another time
Protection Register
Program
4 555h
55h
555h F0h
Read Memory Array until a new write cycle is
initiated.
3+ 555h
Read CFI and Electronic Signature until a Read/Reset command is issued.
AAh 2AAh 55h
Read Protection Register, Block Protection or
Configuration Register Status until a Read/Reset
command is issued.
PA
Read Data Polling or Toggle Bit until
Program completes.
PA3
PD3 PA4 PD4
Read Data Polling or Toggle Bit until Program completes.
PA
C0h
PA
PA4
PD4
PD
Note: X = Don’t Care, BA = Block Address, PA = Program address, PD = Program Data, CRD = Configuration Register Data. For Coded
cycles address inputs A12-A20 are don’t care.
13/43
M59DR032EA, M59DR032EB
Table 5. Read Electronic Signature
Code
Device
E
G
W
A0
A1
A7-A2
A8-A20
DQ15-DQ0
VIL
VIL
VIH
VIL
VIL
0
X
0020h
M59DR032EA
VIL
VIL
VIH
VIH
VIL
0
X
00A0h
M59DR032EB
VIL
VIL
VIH
VIH
VIL
0
X
00A1h
Manufacturer Code
Device Code
Note: X = Don’t care.
Table 6. Read Block Protection
E
G
W
A0
A1
A20-A12
A7-A2
Other
Addresses
DQ0
DQ1
DQ15-DQ2
Locked Block
VIL
VIL
VIH
VIL
VIH
Block Address
0
X
1
0
0000h
Unlocked Block
VIL
VIL
VIH
VIL
VIH
Block Address
0
X
0
0
0000h
Locked-Down
Block
VIL
VIL
VIH
VIL
VIH
Block Address
0
X
X
1
0000h
Block Status
Note: X = Don’t care.
Table 7. Configuration Register
E
G
W
A0
A1
A7-A2
Other Addresses
DQ10
DQ9-DQ0
DQ15-DQ11
Reset
VIL
VIL
VIH
VIH
VIH
0
X
0
Don’t Care
Reset/Power-Down
VIL
VIL
VIH
VIH
VIH
0
X
1
Don’t Care
RP Function
Note: X = Don’t care.
14/43
M59DR032EA, M59DR032EB
Table 8. Read Protection Register
Word
E
G
W
A20-A8
A7-0
DQ15-8
DQ7-3
DQ2
DQ1
DQ0
Lock
VIL
VIL
VIH
X
80h
XXh
00000b
Security
prot.data
OTP
prot.data
0
Unique ID 0
VIL
VIL
VIH
X
81h
ID data
ID data
ID data
ID data
ID data
Unique ID 1
VIL
VIL
VIH
X
82h
ID data
ID data
ID data
ID data
ID data
Unique ID 2
VIL
VIL
VIH
X
83h
ID data
ID data
ID data
ID data
ID data
Unique ID 3
VIL
VIL
VIH
X
84h
ID data
ID data
ID data
ID data
ID data
OTP 0
VIL
VIL
VIH
X
85h
OTP data
OTP data
OTP data
OTP data
OTP data
OTP 1
VIL
VIL
VIH
X
86h
OTP data
OTP data
OTP data
OTP data
OTP data
OTP 2
VIL
VIL
VIH
X
87h
OTP data
OTP data
OTP data
OTP data
OTP data
OTP 3
VIL
VIL
VIH
X
88h
OTP data
OTP data
OTP data
OTP data
OTP data
Note: X= Don’t care.
Table 9. Program, Erase Times and Program, Erase Endurance Cycles
M59DR032E
Parameter
Typ
Typical after
100k W/E Cycles
Unit
Max
2.5
0.3
1
s
4
0.8
3
s
Bank Erase (Preprogrammed, Bank A)
3
6
s
Bank Erase (Preprogrammed, Bank B)
20
30
s
Chip Program (1)
20
25
s
Chip Program (Double Word, VPP = 12V) (1)
8
s
Min
Parameter Block (4 KWord) Erase (Preprogrammed)
Main Block (32 KWord) Erase (Preprogrammed)
Word Program (2)
100
10
µs
Double Word Program (VPP = 12V)
100
8
µs
Quadruple Word Program (VPP = 12V)
100
8
µs
Program/Erase Cycles (per Block)
100,000
cycles
Note: 1. Excludes the time needed to execute the sequence for program command.
2. Same timing value if V PP = 12V
15/43
M59DR032EA, M59DR032EB
BLOCK LOCKING
The M59DR032E features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has two levels of protection.
■ Lock/Unlock - this first level allows softwareonly control of block locking.
■
Lock-Down - this second level requires
hardware interaction before locking can be
changed.
The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 10, defines all of the possible protection states (WP,
DQ1, DQ0).
Reading a Block’s Lock Status
The lock status of every block can be read in the
Auto Select mode of the device. Subsequent
reads at the address specified in Table 6, will output the protection status of that block. The lock
status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by
the Lock command and cleared by the Unlock
command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
The following sections explain the operation of the
locking system.
Locked State
The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase operations attempted on a locked block will reset the
device to Read Array mode. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.
Unlocked State
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
16/43
software commands. A locked block can be unlocked by issuing the Unlock command.
Lock-Down State
Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status cannot be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the
device is reset or powered-down.
The Lock-Down function is dependent on the WP
input pin. When WP=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When
WP=1 (V IH) the Lock-Down function is disabled
(1,1,1) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WP
remains High. When WP is low, blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WP was High. Device reset or power-down
resets all blocks, including those in Lock-Down, to
the Locked state.
Locking Operations During Erase Suspend
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After completing any desired lock, read, or program operations,
resume the erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
M59DR032EA, M59DR032EB
Table 10. Lock Status
Current
Protection Status(1)
(WP, DQ1, DQ0)
Next Protection Status(1)
(WP, DQ1, DQ0)
Current State
Program/Erase
Allowed
After
Block Lock
Command
After
Block Unlock
Command
After Block
Lock-Down
Command
After
WP transition
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
1,0,1(2)
no
1,0,1
1,0,0
1,1,1
0,0,1
1,1,0
yes
1,1,1
1,1,0
1,1,1
0,1,1
1,1,1
no
1,1,1
1,1,0
1,1,1
0,1,1
0,0,0
yes
0,0,1
0,0,0
0,1,1
1,0,0
0,0,1(2)
no
0,0,1
0,0,0
0,1,1
1,0,1
0,1,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Auto Select command with A1 = VIH and A0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
17/43
M59DR032EA, M59DR032EB
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operations.
Bus Read operations from any address within the
bank, always read the Status Register during Program and Erase operations.
The various bits convey information about the status and any errors of the operation.
The bits in the Status Register are summarized in
Table 12, Status Register Bits. Refer to Tables 11
and 12 in conjunction with the following text descriptions.
Data Polling Bit (DQ7). When Program operations are in progress, the Data Polling bit outputs
the complement of the bit being programmed on
DQ7. For a Double Word Program operation, it is
the complement of DQ7 for the last Word written to
the Command Interface.
During an Erase operation, it outputs a ’0’. After
completion of the operation, DQ7 will output the bit
last programmed or a ’1’ after erasing.
Data Polling is valid and only effective during P/
E.C. operation, that is after the fourth W pulse for
programming or after the sixth W pulse for erase.
It must be performed at the address being programmed or at an address within the block being
erased. See Figure 21 for the Data Polling flowchart and Figure 12 for the Data Polling waveforms.
DQ7 will also flag an Erase Suspend by switching
from ’0’ to ’1’ at the start of the Erase Suspend. In
order to monitor DQ7 in the Erase Suspend mode
an address within a block being erased must be
provided. DQ7 will output ’1’ if the read is attempted on a block being erased and the data value on
other blocks. During a program operation in Erase
Suspend, DQ7 will have the same behavior as in
the normal program.
Toggle Bit (DQ6). When Program or Erase operations are in progress, successive attempts to
read DQ6 will output complementary data. DQ6
will toggle following the toggling of either G or E.
The operation is completed when two successive
reads give the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing.
The Toggle Bit DQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase.
DQ6 will be set to ’1’ if a read operation is attempted on an Erase Suspend block. When erase is
suspended DQ6 will toggle during programming
operations in a block different from the block in
Erase Suspend.
18/43
See Figure 15 for Toggle Bit flowchart and Figure
13 for Toggle Bit waveforms.
Toggle Bit (DQ2). Toggle Bit DQ2, together with
DQ6, can be used to determine the device status
during erase operations.
During Erase Suspend a read from a block being
erased will cause DQ2 to toggle. A read from a
block not being erased will output data. DQ2 will
be set to '1' during program operation and to ‘0’ in
erase operation. If a read operation is addressed
to a block where an erase error has occurred, DQ2
will toggle.
Error Bit (DQ5). The Error Bit can be used to
identify if an error occurs during a program or
erase operation.
The Error Bit is set to ‘1’ when a program or erase
operation has failed. When it is set to ‘0’ the program or erase operation was successful.
If any Program command is used to try to set a bit
from ‘0’ to ‘1’ Status Register Error bit DQ5 will be
set to ‘1’, only if VPP is in the range of 11.4V to
12.6V.
The Error Bit is reset by a Read/Reset command.
Erase Timer Bit (DQ3). The Erase Timer bit is
used to indicate the timeout period for an erase
operation.
When the last block Erase command has been entered to the Command Interface and it is waiting
for the erase operation to start, the Erase Timer Bit
is set to ‘0’. When the erase timeout period is finished, DQ3 returns to ‘1’, (80µs to 120µs).
DQ0, DQ1 and DQ4 are reserved for future use
and should be masked.
Table 11. Polling and Toggle Bits
Mode
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
N/A
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
1
Program
M59DR032EA, M59DR032EB
Table 12. Status Register Bits
DQ
7
Name
Data
Polling
Logic Level
’1’
Erase complete or erase block
in Erase Suspend.
’0’
Erase in progress
DQ
Program complete or data of
non erase block during Erase
Suspend.
DQ
Program in progress(2)
’-1-0-1-0-1-0-1-’
DQ
6
Toggle Bit
’-1-1-1-1-1-1-1-’
5
4
3
Erase or Program in progress
Program complete
Erase complete or Erase
Suspend on currently addressed
block
Note
Indicates the P/E.C. status, check
during Program or Erase, and on
completion before checking bits DQ5
for Program or Erase success.
Successive reads output
complementary data on DQ6 while
Programming or Erase operations are
in progress. DQ6 remains at constant
level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
’1’
Program or Erase Error
’0’
Program or Erase in progress
’1’
Erase Timeout Period Expired
P/E.C. Erase operation has started.
Only possible command entry is Erase
Suspend
’0’
Erase Timeout Period in
progress
An additional block to be erased in
parallel can be entered to the P/E.C
provided that it belongs to the same
bank
Error Bit
This bit is set to ’1’ in the case of
Programming or Erase failure.
Reserved
Erase Time
Bit
’-1-0-1-0-1-0-1-’
2
Definition
Toggle Bit
1
DQ
1
Reserved
0
Reserved
Erase Suspend read in the
Erase Suspended Block.
Erase Error due to the currently
addressed block (when DQ5 =
’1’).
Program in progress or Erase
complete.
Indicates the erase status and allows
to identify the erased block.
Erase Suspend read on non
Erase Suspend block.
Note: 1. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations.
2. In case of double word program DQ7 refers to the last word input.
19/43
M59DR032EA, M59DR032EB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 13. Absolute Maximum Ratings
Symbol
Value
Unit
Ambient Operating Temperature (1)
–40 to 85
°C
TBIAS
Temperature Under Bias
–40 to 125
°C
TSTG
Storage Temperature
–55 to 155
°C
VIO (2)
Input or Output Voltage
–0.5 to VDDQ+0.5
V
Supply Voltage
–0.5 to 2.7
V
Program Voltage
–0.5 to 13
V
TA
VDD, VDDQ
VPP
Parameter
Note: 1. Depends on range.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
20/43
M59DR032EA, M59DR032EB
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 14, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when relying on the quoted parameters.
Table 14. Operating and AC Measurement Conditions
M59DR032EA, M59DR032EB
85
100
120
Parameter
Units
Min
Max
Min
Max
Min
Max
VDD Supply Voltage
1.8
2.2
1.65
2.2
1.65
2.2
V
VDDQ Supply Voltage
1.8
2.2
1.65
2.2
1.65
2.2
V
VPP Supply Voltage
11.4
12.6
11.4
12.6
11.4
12.6
V
Ambient Operating Temperature
– 40
85
– 40
85
– 40
85
°C
Load Capacitance (CL)
30
Input Rise and Fall Times
30
30
4
Input Pulse Voltages
Input and Output Timing Ref. Voltages
4
pF
4
ns
0 to VDDQ
0 to VDDQ
0 to VDDQ
V
VDDQ/2
VDDQ/2
VDDQ/2
V
Figure 5. Testing Input/Output Waveforms
Figure 6. AC Testing Load Circuit
VDDQ / 2
VDDQ
VDDQ/2
1N914
0V
AI06186
3.3kΩ
DEVICE
UNDER
TEST
OUT
CL
CL includes JIG capacitance
AI06187
Table 15. Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: Sampled only, not 100% tested.
21/43
M59DR032EA, M59DR032EB
Table 16. DC Characteristics
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
0V ≤ VIN ≤ VDD
±1
µA
0V ≤ VOUT ≤ VDD
±5
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
Supply Current
(Read Mode)
E = VIL, G = VIH, f = 6MHz
3
6
mA
ICC2
Supply Current
(Power-Down)
RP = VSS ± 0.2V
2
10
µA
ICC3
Supply Current (Standby)
E = VDD ± 0.2V
10
50
µA
ICC4 (1)
Supply Current
(Program or Erase)
Word Program, Block Erase
in progress
10
20
mA
ICC5 (1)
Supply Current
(Dual Bank)
Program/Erase in progress
in one Bank, Read in the
other Bank
13
26
mA
VPP = 12V ± 0.6V
2
5
mA
VPP ≤ VDD
0.2
5
µA
VPP = 12V ± 0.6V
100
400
µA
IPP1
VPP Supply Current
(Program or Erase)
IPP2
VPP Supply Current
(Standby or Read)
VIL
Input Low Voltage
–0.5
0.4
V
VIH
Input High Voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output Low Voltage
IOL = 100µA
0.1
V
VOH
Output High Voltage
CMOS
IOH = –100µA
VPP (2,3)
VPP Supply Voltage
(Program or Erase)
VDDQ –0.1
Double Word Program
Note: 1. Sampled only, not 100% tested.
2. VPP may be connected to 12V power supply for a total of less than 100 hrs.
3. For standard program/erase operation VPP is don’t care.
22/43
V
–0.4
VDD + 0.4
V
11.4
12.6
V
Note: Write Enable (W) = High.
DQ0-DQ15
G
E
A0-A20
tAVQV
tGLQV
tGLQX
tELQX
tELQV
VALID
tAVAV
VALID
tGHQZ
tGHQX
tEHQX
tEHQZ
tAXQX
AI06190
M59DR032EA, M59DR032EB
Figure 7. Random Read AC Waveforms
23/43
24/43
DQ0-DQ15
G
E
A0-A1
A2-A20
tAVQV
tELQV
VALID
VALID
tGLQV
VALID
tAVQV1
VALID
VALID
VALID
VALID
tEHQX
VALID
tGHQX
VALID
tEHQZ
tGHQZ
AI06191
M59DR032EA, M59DR032EB
Figure 8. Page Read AC Waveforms
M59DR032EA, M59DR032EB
Table 17. Read AC Characteristics
M59DR032E
Symbol
Alt
Parameter
Test Condition
85
Min
100
Max
Min
120
Max
Min
Unit
Max
tAVAV
tRC
Address Valid to Next
Address Valid
E = VIL, G = VIL
tAVQV
tACC
Address Valid to Output
Valid (Random)
E = VIL, G = VIL
85
100
120
ns
tAVQV1
tPAGE
Address Valid to Output
Valid (Page)
E = VIL, G = VIL
30
35
45
ns
tELQX (1)
tLZ
Chip Enable Low to
Output Transition
G = VIL
tELQV (2)
tCE
Chip Enable Low to
Output Valid
G = VIL
tGLQX (1)
tOLZ
Output Enable Low to
Output Transition
E = VIL
tGLQV (2)
tOE
Output Enable Low to
Output Valid
E = VIL
tEHQX
tOH
Chip Enable High to
Output Transition
G = VIL
tEHQZ (1)
tHZ
Chip Enable High to
Output Hi-Z
G = VIL
tGHQX
tOH
Output Enable High to
Output Transition
E = VIL
tGHQZ (1)
tDF
Output Enable High to
Output Hi-Z
E = VIL
tAXQX
tOH
Address Transition to
Output Transition
E = VIL, G = VIL
100
85
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
35
0
ns
ns
35
25
20
ns
ns
35
25
20
ns
120
25
25
ns
0
100
85
0
120
ns
ns
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV .
25/43
M59DR032EA, M59DR032EB
Figure 9. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A20
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ15
tWHDX
VALID
VDD
tVDHEL
AI06192
Note: Addresses are latched on the falling edge of W, Data is latched on the rising edge of W
Table 18. Write AC Characteristics, Write Enable Controlled
M59DR032E
Symbol
Alt
Parameter
85
Min
100
Max
Min
120
Max
Min
Unit
Max
tAVAV
tWC
Address Valid to Next Address Valid
85
100
120
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
0
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
50
50
50
ns
tDVWH
tDS
Input Valid to Write Enable High
40
50
50
ns
tWHDX
tDH
Write Enable High to Input Transition
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
30
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
0
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
50
50
50
ns
Output Enable High to Write Enable Low
0
0
0
ns
tGHWL
tVDHEL
tVCS
VDD High to Chip Enable Low
50
50
50
µs
tWHGL
tOEH
Write Enable High to Output Enable Low
30
30
30
ns
tPLQ7V
26/43
RP Low to Reset Complete During
Program/Erase
15
15
15
µs
M59DR032EA, M59DR032EB
Figure 10. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A20
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ15
tEHDX
VALID
VDD
tVDHWL
AI06193
Note: Addresses are latched on the falling edge of E, Data is latched on the rising edge of E.
Table 19. Write AC Characteristics, Chip Enable Controlled
M59DR032E
Symbol
Alt
Parameter
85
Min
100
Max
Min
120
Max
Min
Unit
Max
tAVAV
tWC
Address Valid to Next Address Valid
85
100
120
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
0
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
50
50
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
40
50
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
0
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
30
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
0
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
50
50
50
ns
Output Enable High Chip Enable Low
0
0
0
ns
tGHEL
tVDHWL
tVCS
VDD High to Write Enable Low
50
50
50
µs
tEHGL
tOEH
Chip Enable High to Output Enable Low
30
30
30
ns
tPLQ7V
RP Low to Reset Complete During
Program/Erase
15
15
15
µs
27/43
M59DR032EA, M59DR032EB
Figure 11. Reset/Power-Down AC Waveform
READ
PROGRAM / ERASE
W
DQ7
DQ7
VALID
VALID
RP
tPLPH
tPLQ7V
tPHQ7V
AI06194
Table 20. Reset/Power-Down AC Characteristics
M59DR032E
Symbol
Alt
Parameter
Test Condition
85
Min
100
Max
Min
120
Max
Min
Unit
Max
tPHQ7V1
RP High to Data Valid
(Read Mode)
150
150
150
ns
tPHQ7V2
RP High to Data Valid
(Power-Down enabled)
50
50
50
µs
During Program
10
10
10
µs
During Erase
20
20
20
µs
tPLQ7V
tPLPH
28/43
RP Low to Reset Complete
tRP
RP Pulse Width
50
50
50
ns
DQ0-DQ6/
DQ8-DQ15
DQ7
W
G
E
A0-A20
LAST WRITE
CYCLE OF
PROGRAM
OR ERASE
INSTRUCTION
DATA POLLING
READ CYCLES
tWHQ7V
tEHQ7V
tELQV
tAVQV
tQ7VQV
IGNORE
DQ7
DATA POLLING (LAST) CYCLE
tGLQV
ADDRESS (WITHIN BLOCKS)
VALID
VALID
AI06195
MEMORY
ARRAY
READ CYCLE
M59DR032EA, M59DR032EB
Figure 12. Data Polling DQ7 AC Waveforms
29/43
30/43
DATA
TOGGLE
READ CYCLE
Note: All other timings are as a normal Read cycle.
LAST WRITE
CYCLE OF
PROGRAM
OF ERASE
INSTRUCTION
DQ0-DQ1,DQ3-DQ5,
DQ7-DQ15
DQ6,DQ2
W
G
E
A0-A20
DATA TOGGLE
READ CYCLE
IGNORE
STOP TOGGLE
tWHQV
tEHQV
tAVQV
MEMORY ARRAY
READ CYCLE
VALID
VALID
tGLQV
tELQV
VALID
AI06196
M59DR032EA, M59DR032EB
Figure 13. Data Toggle DQ6, DQ2 AC Waveforms
M59DR032EA, M59DR032EB
Table 21. Data Polling and Toggle Bits AC Characteristics
M59DR032E
Symbol
tWHQ7V
Parameter
Unit
Write Enable High to DQ7 Valid (Program, W Controlled)
Write Enable High to DQ7 Valid (Block Erase, W Controlled)
Chip Enable High to DQ7 Valid (Program, E Controlled)
Min
Max
8
100
µs
0.8
4
s
8
100
µs
0.8
4
s
0
ns
8
100
µs
0.8
4
s
8
100
µs
0.8
4
s
tEHQ7V
Chip Enable High to DQ7 Valid (Block Erase, E Controlled)
tQ7VQV
Q7 Valid to Output Valid (Data Polling)
Write Enable High to Output Valid (Program)
tWHQV
Write Enable High to Output Valid (Block Erase)
tEHQV
Chip Enable High to Output Valid (Program)
Chip Enable High to Output Valid (Block Erase)
Note: All other timings are defined in Read AC Characteristics
Figure 14. Data Polling Flowchart
Figure 15. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
DQ6
=
TOGGLES
YES
NO
NO
YES
NO
DQ5
=1
DQ5
=1
YES
YES
READ DQ7
READ DQ6
DQ7
=
DATA
NO
YES
DQ6
=
TOGGLES
NO
NO
YES
FAIL
PASS
FAIL
PASS
AI06197
AI06198
31/43
M59DR032EA, M59DR032EB
PACKAGE MECHANICAL
Figure 16. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Outline
D
D1
FD
SD
FE
SE
E1
E
ddd
BALL "A1"
A
e
A2
b
A1
BGA-Z03
Note: Drawing is not to scale.
Table 22. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
A1
Typ
Min
1.350
0.300
0.200
A2
0.350
0.300
0.550
Max
0.0531
0.0118
0.0079
1.000
b
0.0138
0.0394
0.0118
0.0217
D
7.000
6.900
7.100
0.2756
0.2717
0.2795
D1
5.250
–
–
0.2067
–
–
ddd
32/43
Max
0.100
0.0039
E
12.000
11.900
12.100
0.4724
0.4685
0.4764
E1
3.750
–
–
0.1476
–
–
e
0.750
–
–
0.0295
–
–
SD
0.375
–
–
0.0148
–
–
SE
0.375
–
–
0.0148
–
–
FE
4.125
–
–
0.1624
–
–
FD
0.875
–
–
0.0344
–
–
M59DR032EA, M59DR032EB
Figure 17. TFBGA48 7x7mm - 8x6 ball array, 0.75 mm pitch, Package Outline
D
FD
D1
SD
FE
SE
E
E1
e
ddd
BALL "A1"
e
b
A
A2
A1
BGA-Z09
Note: Drawing is not to scale.
Table 23. TFBGA48 7x7mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
Max
0.0472
0.200
0.0079
A2
0.800
0.0315
b
0.400
0.350
0.450
0.0157
0.0138
0.0177
D
7.000
6.900
7.100
0.2756
0.2717
0.2795
D1
5.250
–
–
0.2067
–
–
ddd
0.100
0.0039
E
7.000
6.900
7.100
0.2756
0.2717
0.2795
E1
3.750
–
–
0.1476
–
–
e
0.750
–
–
0.0295
–
–
FD
0.875
–
–
0.0344
–
–
FE
1.625
–
–
0.0640
–
–
SD
0.375
–
–
0.0148
–
–
SE
0.375
–
–
0.0148
–
–
33/43
M59DR032EA, M59DR032EB
Figure 18. TFBGA48 Daisy Chain - Package Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
AI03079
Figure 19. TFBGA48 Daisy Chain - PCB Connection Proposal (Top view through package)
1
A
2
3
4
5
6
7
8
START
POINT
B
C
D
E
F
END
POINT
AI03080
34/43
M59DR032EA, M59DR032EB
PART NUMBERING
Table 24. Ordering Information Scheme
Example:
M59DR032EA
10 ZB
6
T
Device Type
M59
Architecture
D = Dual Bank, Page Mode
Operating Voltage
R = 1.8V
Device Function
032EA = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Top Boot
032EB = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Bottom Boot
Random Speed
85 = 85ns
10 = 100ns
12 = 120ns
Package
ZB = TFBGA48: 7 x 12mm, 0.75mm pitch
ZF = TFBGA48: 7 x 7mm, 0.75mm pitch
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Option
blank = Standard Packing
T = Tape & Reel packing
E = Lead-Free Package, Standard Packing
F = Lead-Free Package, Tape & Reel Packing
35/43
M59DR032EA, M59DR032EB
Table 25. Daisy Chain Ordering Scheme
Example:
M59DR032E
-ZB T
Device Type
M59DR032E
Daisy Chain
ZB = TFBGA48: 7x12mm, 0.75mm pitch
ZF = TFBGA48: 7 x 7mm, 0.75mm pitch
Option
blank = Standard Packing
T = Tape & Reel packing
E = Lead-Free Package, Standard Packing
F = Lead-Free Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST
Sales Office nearest to you.
36/43
M59DR032EA, M59DR032EB
APPENDIX A. BLOCK ADDRESSES
Table 26. Bank A, Top Boot Block Addresses
M59DR032EA
38
32
130000h-137FFFh
37
32
128000h-12FFFFh
36
32
120000h-127FFFh
#
Size
(KWord)
Address Range
14
4
1FF000h-1FFFFFh
35
32
118000h-11FFFFh
13
4
1FE000h-1FEFFFh
34
32
110000h-117FFFh
12
4
1FD000h-1FDFFFh
33
32
108000h-10FFFFh
32
100000h-107FFFh
11
4
1FC000h-1FCFFFh
32
10
4
1FB000h-1FBFFFh
31
32
0F8000h-0FFFFFh
9
4
1FA000h-1FAFFFh
30
32
0F0000h-0F7FFFh
8
4
1F9000h-1F9FFFh
29
32
0E8000h-0EFFFFh
32
0E0000h-0E7FFFh
7
4
1F8000h-1F8FFFh
28
6
32
1F0000h-1F7FFFh
27
32
0D8000h-0DFFFFh
5
32
1E8000h-1EFFFFh
26
32
0D0000h-0D7FFFh
4
32
1E0000h-1E7FFFh
25
32
0C8000h-0CFFFFh
32
0C0000h-0C7FFFh
3
32
1D8000h-1DFFFFh
24
2
32
1D0000h-1D7FFFh
23
32
0B8000h-0BFFFFh
1
32
1C8000h-1CFFFFh
22
32
0B0000h-0B7FFFh
0
32
1C0000h-1C7FFFh
21
32
0A8000h-0AFFFFh
20
32
0A0000h-0A7FFFh
19
32
098000h-09FFFFh
Table 27. Bank B, Top Boot Block Addresses
M59DR032EA
#
Size
(KWord)
18
32
090000h-097FFFh
Address Range
17
32
088000h-08FFFFh
32
080000h-087FFFh
55
32
1B8000h-1BFFFFh
16
54
32
1B0000h-1B7FFFh
15
32
078000h-07FFFFh
53
32
1A8000h-1AFFFFh
14
32
070000h-077FFFh
52
32
1A0000h-1A7FFFh
13
32
068000h-06FFFFh
32
060000h-067FFFh
51
32
198000h-19FFFFh
12
50
32
190000h-197FFFh
11
32
058000h-05FFFFh
49
32
188000h-18FFFFh
10
32
050000h-057FFFh
48
32
180000h-187FFFh
9
32
048000h-04FFFFh
32
040000h-047FFFh
47
32
178000h-17FFFFh
8
46
32
170000h-177FFFh
7
32
038000h-03FFFFh
45
32
168000h-16FFFFh
6
32
030000h-037FFFh
44
32
160000h-167FFFh
5
32
028000h-02FFFFh
32
020000h-027FFFh
43
32
158000h-15FFFFh
4
42
32
150000h-157FFFh
3
32
018000h-01FFFFh
41
32
148000h-14FFFFh
2
32
010000h-017FFFh
40
32
140000h-147FFFh
1
32
008000h-00FFFFh
138000h-13FFFFh
0
32
000000h-007FFFh
39
32
37/43
M59DR032EA, M59DR032EB
Table 28. Bank B, Bottom Boot Block
Addresses M59DR032EB
18
32
0D0000h-0D7FFFh
17
32
0C8000h-0CFFFFh
#
Size
(KWord)
Address Range
16
32
0C0000h-0C7FFFh
55
32
1F8000h-1FFFFFh
15
32
0B8000h-0BFFFFh
54
32
1F0000h-1F7FFFh
14
32
0B0000h-0B7FFFh
53
32
1E8000h-1EFFFFh
13
32
0A8000h-0AFFFFh
52
32
1E0000h-1E7FFFh
12
32
0A0000h-0A7FFFh
51
32
1D8000h-1DFFFFh
11
32
098000h-09FFFFh
50
32
1D0000h-1D7FFFh
10
32
090000h-097FFFh
49
32
1C8000h-1CFFFFh
9
32
088000h-08FFFFh
48
32
1C0000h-1C7FFFh
8
32
080000h-087FFFh
47
32
1B8000h-1BFFFFh
7
32
078000h-07FFFFh
46
32
1B0000h-1B7FFFh
6
32
070000h-077FFFh
45
32
1A8000h-1AFFFFh
5
32
068000h-06FFFFh
44
32
1A0000h-1A7FFFh
4
32
060000h-067FFFh
43
32
198000h-19FFFFh
3
32
058000h-05FFFFh
42
32
190000h-197FFFh
2
32
050000h-057FFFh
41
32
188000h-18FFFFh
1
32
048000h-04FFFFh
40
32
180000h-187FFFh
0
32
040000h-047FFFh
39
32
178000h-17FFFFh
38
32
170000h-177FFFh
37
32
168000h-16FFFFh
36
32
160000h-167FFFh
#
Size
(KWord)
Address Range
35
32
158000h-15FFFFh
14
32
038000h-03FFFFh
34
32
150000h-157FFFh
13
32
030000h-037FFFh
33
32
148000h-14FFFFh
12
32
028000h-02FFFFh
32
32
140000h-147FFFh
11
32
020000h-027FFFh
31
32
138000h-13FFFFh
10
32
018000h-01FFFFh
30
32
130000h-137FFFh
9
32
010000h-017FFFh
29
32
128000h-12FFFFh
8
32
008000h-00FFFFh
28
32
120000h-127FFFh
7
4
007000h-007FFFh
27
32
118000h-11FFFFh
6
4
006000h-006FFFh
26
32
110000h-117FFFh
5
4
005000h-005FFFh
25
32
108000h-10FFFFh
4
4
004000h-004FFFh
24
32
100000h-107FFFh
3
4
003000h-003FFFh
23
32
0F8000h-0FFFFFh
2
4
002000h-002FFFh
22
32
0F0000h-0F7FFFh
1
4
001000h-001FFFh
21
32
0E8000h-0EFFFFh
0
4
000000h-000FFFh
20
32
0E0000h-0E7FFFh
19
32
0D8000h-0DFFFFh
38/43
Table 29. Bank A, Bottom Boot Block
Addresses M59DR032EB
M59DR032EA, M59DR032EB
APPENDIX B. COMMON FLASH INTERFACE
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when
necessary.
When the Read CFI Query Command is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 30, 31,
32 and 33 show the address used to retrieve each
data. The Query data is always presented on the
lowest order data outputs (DQ0-DQ7), the other
outputs (DQ8-DQ15) are set to 0.
The CFI data structure contains also a security
area starting at address 81h. This area can be accessed only in read mode and it is impossible to
change after it has been written by ST. Issue a
Read command to return to Read mode.
Table 30. Query Structure Overview
Offset
Sub-section Name
Description
00h
Reserved
Reserved for algorithm-specific information
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing & voltage information
27h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Table 31. CFI Query Identification String
Offset
Data
Description
00h
0020h
01h
00A1h - bottom
00A0h - top
02h-0Fh
reserved
10h
0051h
Query Unique ASCII String "QRY"
11h
0052h
Query Unique ASCII String "QRY"
12h
0059h
Query Unique ASCII String "QRY"
13h
0002h
14h
0000h
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
15h
offset = P = 0040h
16h
0000h
17h
0000h
18h
0000h
19h
value = A = 0000h
1Ah
0000h
Manufacturer Code
Device Code
Reserved
Address for Primary Algorithm extended Query table
Alternate Vendor Command Set and Control Interface ID Code second vendor
- specified algorithm supported (note: 0000h means none exists)
Address for Alternate Algorithm extended Query table
note: 0000h means none exists
39/43
M59DR032EA, M59DR032EB
Table 32. CFI Query System Interface Information
Offset
Data
1Bh
0017h
VDD Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
1Ch
0022h
VDD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
0000h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
Note: This value must be 0000h if no VPP pin is present
1Eh
00C0h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
Note: This value must be 0000h if no VPP pin is present
1Fh
0004h
Typical timeout per single byte/word program (multi-byte program count = 1), 2n µs
(if supported; 0000h = not supported)
20h
0003h
Typical timeout for maximum-size multi-byte program or page write, 2n µs
(if supported; 0000h = not supported)
21h
000Ah
Typical timeout per individual block erase, 2n ms
(if supported; 0000h = not supported)
22h
0000h
Typical timeout for full chip erase, 2n ms
(if supported; 0000h = not supported)
23h
0003h
Maximum timeout for byte/word program, 2n times typical (offset 1Fh)
(0000h = not supported)
24h
0004h
Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h)
(0000h = not supported)
25h
0002h
Maximum timeout per individual block erase, 2n times typical (offset 21h)
(0000h = not supported)
26h
0000h
Maximum timeout for chip erase, 2n times typical (offset 22h)
(0000h = not supported)
1Dh
40/43
Description
M59DR032EA, M59DR032EB
Table 33. Device Geometry Definition
Offset Word
Mode
Data
27h
0016h
28h
0001h
29h
0000h
2Ah
0000h
2Bh
0000h
2Ch
0002h
Description
Device Size = 2n in number of bytes
Flash Device Interface Code description: Asynchronous x16
Maximum number of bytes in multi-byte program or page = 2n
Number of Erase Block Regions within device
bit 7 to 0 = x = number of Erase Block Regions
Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk."
2. x specifies the number of regions within the device containing one or more
contiguous Erase Blocks of the same size. For example, a 128KB device
(1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is
considered to have 5 Erase Block Regions. Even though two regions both
contain 16KB blocks, the fact that they are not contiguous means they are
separate Erase Block Regions.
3. By definition, symmetrically block devices have only one blocking region.
M59DR032EA
M59DR032EA Erase Block Region Information
2Dh
003Eh
2Eh
0000h
2Fh
0000h
30h
0001h
31h
0007h
32h
0000h
33h
0020h
34h
0000h
M59DR032EB
M59DR032EB
2Dh
0007h
2Eh
0000h
2Fh
0020h
30h
0000h
31h
003Eh
32h
0000h
33h
0000h
34h
0001h
bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes
in size. The value z = 0 is used for 128 byte block size.
e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K
bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase
Block Region:
e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]
y = 0 means no blocking (# blocks = y+1 = "1 block")
Note: y = 0 value must be used with number of block regions of one as indicated
by (x) = 0
41/43
M59DR032EA, M59DR032EB
REVISION HISTORY
Table 34. Document Revision History
Date
Version
05-Feb-2002
-01
First Issue
-02
Document classified as Preliminary Data. Top and Bottom Device Codes modified,
Program commands text clarified, Table 4, Commands modified, Table 9, Program and
Erase Times modified, Status Register Error bit DQ5 text clarified, Table 21, Data
Polling and Toggle Bits AC Characteristics modified.
2.1
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(revision version 02 equals 2.0).
Locked block condition at Reset specified in the Summary Description. Read CFI
Query Command, Auto Select Command, Enter Bypass Mode Command, Block Erase
Command, Bank Erase Command and Erase Suspend Command specified. Auto
Select command modified in Table 4, Commands. States of lines A8-A20 modified in
Table 5, Read Electronic Signature. States of lines A8-A20 modified in Table 8, Read
Protection Register. Note corresponding to DQ3 at ‘0’ specified in Table 12, Status
Register Bits.
04-Dec-2002
2.2
Figures 18 and 19 added (TFBGA48 Daisy Chain - Package Connections (Top view
through package) and TFBGA48 Daisy Chain - PCB Connection Proposal (Top view
through package), respectively).
85ns Speed Class added.
22-Apr-2003
3.0
Document promoted from Preliminary Data to full Datasheet status.
TFBGA48, 7 x 7mm, 0.75mm pitch package added. 85ns Speed Class characterized.
Performance of Bank Erase Command specified.
04-Apr-2002
05-Sep-2002
42/43
Revision Details
M59DR032EA, M59DR032EB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
© 2003 STMicroelectronics - All Rights Reserved
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43/43