MC100LVELT22 3.3VDual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the LVELT22 makes it ideal for applications which require the translation of a clock and a data signal. Features • • • • • MARKING DIAGRAMS* 8 8 1 KVT22 ALYW G SOIC−8 D SUFFIX CASE 751 1 8 8 1 KR22 ALYWG G TSSOP−8 DT SUFFIX CASE 948R 1 4I M G G • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation LVPECL Operating Range: VCC = 3.0 V to 3.8 V with GND = 0 V When Unused TTL Input is left Open, Q Output will Default High Pb−Free Packages are Available http://onsemi.com DFN8 MN SUFFIX CASE 506AA A L Y W M G 1 4 = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 5 1 Publication Order Number: MC100LVELT22/D MC100LVELT22 Q0 1 8 Table 1. PIN DESCRIPTION VCC PIN Q0 2 LVPECL 7 D0 LVTTL/ LVCMOS Q1 3 6 D1 Q1 4 5 GND FUNCTION Qn, Qn D0, D1 VCC GND LVPECL Differential Outputs LVTTL/LVCMOS Inputs Positive Supply Ground EP Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. Figure 1. 8−Lead Pinout (Top View) and Logic Diagram EP Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model > 4 kV > 200 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 164 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Positive Power Supply GND = 0 V VI Input Voltage GND = 0 V Iout Output Current Continuous Surge TA Condition 2 VI VCC Rating Unit 7 V 7 V 50 100 mA mA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SO−8 SO−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) std bd SO−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) std bd TSSOP−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 MC100LVELT22 Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 2) −40°C Symbol Characteristic Min Typ 25°C Max Min 85°C Typ Max 28 Min Typ Max Unit 29 mA ICC Power Supply Current 28 VOH Output HIGH Voltage (Note 3) 2275 2420 2275 2420 2275 2420 mV VOL Output LOW Voltage (Note 3) 1490 1680 1490 1680 1490 1680 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Output parameters vary 1:1 with VCC. VCC can vary ±0.15 V. 3. Outputs are terminated through a 50 ohm resistor to VCC−2 volts. Table 5. LVTTL/LVCMOS INPUT DC CHARACTERISTICS VCC = 3.3 V; TA = −40°C to 85°C (Note 4) Symbol Characteristic Min Typ Max Unit Condition IIH Input HIGH Current 20 mA VIN = 2.7 V IIHH Input HIGH Current 100 mA VIN = VCC IIL Input LOW Current −0.2 mA VIN = 0.5 V −1.2 V VIK VIH Input HIGH Voltage VIL Input LOW Voltage 2.0 IIN = −18 mA V 0.8 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. VCC can vary ±0.15 V. Table 6. AC CHARACTERISTICS VCC = 3.3 V; GND = 0.0 V (Note 5) −40°C Symbol Characteristic fmax Maximum Toggle Frequency t PLH Propagation Delay (Note 6) t skew Skew tJITTER t /t r f Min Typ 25°C Max Min Max Min Typ Max 350 200 Output−to−Output Part−to−Part 350 600 30 100 400 200 Random Clock Jitter (RMS) Output Rise/Fall Time (20−80%) Typ 85°C MHz 350 600 30 100 400 200 350 600 ps 30 100 400 ps 1.6 200 550 200 Unit ps 500 200 500 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. VCC can vary ±0.15 V. 6. Specifications for standard TTL input signal. http://onsemi.com 3 MC100LVELT22 Zo = 50 W Q D Receiver Device Driver Device Zo = 50 W Q D 50 W 50 W VTT VTT = VCC − 3.0 V Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVELT22D Package Shipping † SOIC−8 98 Units / Rail MC100LVELT22DG SOIC−8 (Pb−Free) 98 Units / Rail MC100LVELT22DR2 SOIC−8 2500 / Tape & Reel MC100LVELT22DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100LVELT22DT TSSOP−8 100 Units / Rail MC100LVELT22DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100LVELT22DTR2 TSSOP−8 2500 / Tape & Reel MC100LVELT22DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100LVELT22MNR4 DFN8 1000 / Tape & Reel MC00LVELT22MNR4G DFN8 (Pb−Free) 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 4 MC100LVELT22 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC100LVELT22 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U K REF 0.10 (0.004) S 2X L/2 8 1 PIN 1 IDENT S T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S 5 0.25 (0.010) B −U− L 0.15 (0.006) T U M M 4 A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E http://onsemi.com 6 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC100LVELT22 PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B PIN ONE REFERENCE 2X 0.10 C 2X ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ 0.10 C TOP VIEW 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 A 0.10 C 8X DIM A A1 A3 b D D2 E E2 e K L E (A3) SIDE VIEW A1 C D2 e e/2 4 1 8X L E2 K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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