preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 1/12 FEATURES APPLICATIONS ♦ Compact, 5-channel encoder sensor with differential scanning and analog sine/cosine outputs: 2048 CPR with index, 1 CPR absolute, size ∅ 39 mm ♦ Phased-array design for excellent signal matching ♦ Reduced cross talk due to moderate track pitch ♦ Ultra low dark currents for operation up to high temperature ♦ Low noise amplifiers with high transimpedance ♦ Short-circuit-proof, low impedance voltage outputs for enhanced EMI tolerance ♦ Space saving optoQFN and optoBGA packages (RoHS compliant) ♦ Low power consumption from single 4.5 to 5.5 V supply ♦ Operational temperature range of -40 to +110 ◦ C ♦ Suitable code disc: PD2S 39-2048 (glass 1 mm) OD ∅ 39 mm, ID ∅ 18.0 mm, optical radius 17.5 mm ♦ Incremental sine encoders with commutation information ♦ Motor feedback ♦ AC servo and BLDC motor systems PACKAGES 15-pin optoBGA 6.2 mm x 5.2 mm x 1.7 mm 32-pin optoQFN 5 mm x 5 mm x 0.9 mm BLOCK DIAGRAM )%% )*+, 1! iC-PD3948 *+,+*+!%+ - )&./01+ $ "'(! - "'(! "# - $ !'(! - !'(! "% - $ "%&' - !% "%&' "% "'(! - "%&' !'(! "% $ !%&' !% - !% $ " - - !%&' $ # )* % $ $ !%&' )*'% $ "# " $ - " ! $ !# $ Copyright © 2008, 2014 iC-Haus !# ! !# - ! $ http://www.ichaus.com iC-PD 3948 preliminary PHASED ARRAY SINE ENCODER Rev C1, Page 2/12 DESCRIPTION iC-PD3948 is an optical sensor IC with integrated photodiodes whose signal currents are converted into output voltages by low-noise transimpedance amplifiers. Due to a high transimpedance gain of typically 4 MΩ (*1 MΩ/2 MΩ), output signal voltages of several hundred millivolts are obtained at illumination levels of just 1 to 3 mW/cm2 (*6 to 18 mW/cm2 ). In most cases complicated noise suppression measures are thus rendered unnecessary. As the pin names would suggest, iC-PD3948 is typically applied as a sine encoder for motor feedback systems. To this end, iC-PD3948 provides sine and cosine signals with both a high resolution of 2048 CPR (plus an additional index signal) and a low resolution of 1 CPR (at C/D). All code disc signal tracks are evaluated differential; the high resolution sine signals are read by photodiodes in a phased array. The layout of the signal amplifiers is such that there is good paired channel matching, reducing the time and effort required for calibration to an absolute minimum. The spectral sensitivity ranges from visible to near infrared light, with the maximum sensitivity close to a wavelength of 680 nm. An output voltage of 1 V is typical in low light conditions, for instance when iCPD is illuminated at only 2 mW/cm2 (*12 mW/cm2 ) by a 740 nm LED. A relatively low LED current is enough to operate the sensor, proving beneficial to the life expectancy of the LED at high operating temperatures. HD Phased Arrays are designed for fidelity and robustness. Ultra-low signal distortion is obtained at increased tolerances for alignment and random code defects (e.g. due to dust). For information on chip releases, refer to chapter Design Review. *) Data refers to chip release iC-PD3948 Y. iC-PD 3948 preliminary PHASED ARRAY SINE ENCODER Rev C1, Page 3/12 PACKAGING INFORMATION PAD LAYOUT Chip release . (2.88 mm x 3.37 mm) PAD FUNCTIONS No. Name Function Refer to the description of pin functions. PAD LAYOUT Chip release Y, Y1 (2.88 mm x 3.37 mm), HD Phased Array PAD FUNCTIONS No. Name Function Refer to the description of pin functions. preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 4/12 PIN CONFIGURATION oBGA LSH2C (6.2 mm x 5.2 mm) 1 2 PIN FUNCTIONS No. Name Function 3 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 4 C <A-CODE> B <P-CODE> A D VCC VREF GND PSIN NSIN VRDC VRSC PCOS NCOS NC PC Z NZ ND PD +4.5...5.5 V Supply Voltage Reference Voltage Output Ground Sine Track + Sine Track D/C Track Reference S/C Track Reference Cosine Track + Cosine Track C Track C Track + Z Index Signal Z Index Track D Track D Track + Note: All signal and reference outputs are analog voltage outputs. IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes); For dimensional specifications refer to the relevant package data sheet, available separately. PIN FUNCTIONS No. Name Function PIN CONFIGURATION oQFN32-5x5 (5 mm x 5 mm) 32 31 30 29 28 27 26 25 <P-CODE> <A-CODE> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9..16 17 18 19 20 21 22 23 24 25..32 VCC VREF PSIN NSIN PCOS NCOS Z NZ n.c.1) ND PD NC PC VRDC VRSC n.c.1) GND n.c.1) BP +4.5...5.5 V Supply Voltage Reference Voltage Output Sine Track + Sine Track Cosine Track + Cosine Track Z Index Signal Z Index Track D Track D Track + C Track C Track + D/C Track Reference S/C Track Reference Ground Backside paddle2) Note: All signal and reference outputs are analog voltage outputs. IC top marking: <P-CODE> = product code, <A-CODE> = assembly (subject to changes); 1) Pin numbers marked n.c. are not connected. 2) Connecting the backside paddle is recommended by a single link to GND. A current flow across the paddle is not permissible. preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 5/12 PACKAGE DIMENSIONS RECOMMENDED PCB-FOOTPRINT 15 R0. 3.60 0.30 0.70 0.50 4.90 SIDE 0.90 ±0.10 BOTTOM TOP 5 1.90 3.60 5 3.24 G4 3.60 0.50 0.23 0.40 0.30 4.90 3.60 All dimensions given in mm. Tolerances of form and position according to JEDEC MO-220. Positional tolerance of sensor pattern: ±70μm / ±1° (with respect to center of backside pad). G4: radius of chip center (refer to the relevant encoder disc and code description). Maximum molding excess +20μm / -75μm versus surface of glass/reticle. drb_pdxx-oqfn32-2_pack_1, 10:1 preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 6/12 ABSOLUTE MAXIMUM RATINGS These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item No. Symbol Parameter Conditions Unit Min. Max. G001 VCC Voltage at VCC -0.3 6 V G002 I(VCC) Current in VCC -20 20 mA G003 V() Pin Voltage, all signal outputs -0.3 VCC + 0.3 V G004 I() Pin Current, all signal outputs -20 20 mA G005 Vd() ESD Susceptibility, all pins G006 Tj Junction Temperature G007 Ts Chip Storage Temperature HBM, 100 pF discharged through 1.5 kΩ 2 kV -40 150 ◦C -40 150 ◦C THERMAL DATA Operating conditions: VCC = 4.5...5.5 V Item No. T01 Symbol Parameter Conditions Unit Min. Ta Typ. Max. Operating Ambient Temperature Range package oBGA LSH2C package oQFN32-5x5 (extended temperature range of -40 to 125 ◦ C available on request) -40 -40 110 110 ◦C -40 110 ◦C 245 230 ◦C 245 230 ◦C T02 Ts Storage Temperature Range package oBGA LSH2C, package oQFN32-5x5 T03 Tpk Soldering Peak Temperature package oBGA LSH2C tpk < 20 s, convection reflow tpk < 20 s, vapor phase soldering ◦C ◦C TOL (time on label) 8 h; Please refer to customer information file No. 7 for details. T04 Tpk Soldering Peak Temperature package oQFN32-5x5 tpk < 20 s, convection reflow tpk < 20 s, vapor phase soldering MSL 5 A (max. floor live 24 h at 30 ◦ C and 60 % RH); Please refer to customer information file No. 7 for details. All voltages are referenced to ground unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative. ◦C preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 7/12 ELECTRICAL CHARACTERISTICS Operating conditions: VCC = 4.5...5.5 V, Tj = -40..125 ◦ C, unless otherwise stated Item No. Symbol Parameter Conditions Unit Min. Typ. Max. Total Device 001 VCC Permissible Supply Voltage 002 I(VCC) Supply Current no load, photocurrents within op. range 4.5 003 Vc()hi Clamp-Voltage hi at all pins I() = 4 mA 004 Vc()lo Clamp-Voltage lo at all pins I() = -4 mA -1.2 Se(λar) = 0.25 x S(λpk) 400 12 5.5 V 16 mA 11 V -0.3 V 950 nm Photosensors 101 λar Spectral Application Range 102 103 λpk Peak Sensitivity Wavelength Aph() Radiant Sensitive Area 680 nm chip release iC-PD3948. S/C track (DPSIN, DNSIN, DPCOS, DNCOS) C/D track (DPC, DNC, DPD, DND) Z track (DPZ, DNZ) 0.075 0.033 0.042 mm2 mm2 mm2 chip release iC-PD3948 Y S/C track (DPSIN, DNSIN, DPCOS, DNCOS) C/D track (DPC, DNC, DPD, DND) Z track (DPZ, DNZ) 0.076 0.031 0.039 mm2 mm2 mm2 0.5 0.3 A/W A/W 104 S(λ) Spectral Sensitivity λLED = 740 nm λLED = 850 nm 106 E()mx Irradiance For Maximum Signal Level λLED = 740 nm, Vout() not saturated; chip release iC-PD3948. S/C track 1.2 2.0 3.2 C/D track 2.4 4.0 6.4 Z track 1.9 3.0 4.8 chip release iC-PD3948 Y S/C track 6.0 12 18 C/D track 8.0 15 24 Z track 12 21 36 chip release iC-PD3948., all tracks 0 280 nA chip release iC-PD3948 Y S/C track and Z track C/D track 0 0 1120 560 nA nA Photocurrent Amplifiers 201 Iph() Permissible Photocurrent Operating Range 202 η()r Photo Sensitivity λLED = 740 nm; (light-to-voltage conversion ratio) chip release iC-PD3948., all tracks chip release iC-PD3948 Y S/C track, Z track C/D track 203 Z() Equivalent Transimpedance Gain Z = Vout() / Iph(); chip release iC-PD3948., all tracks chip release iC-PD3948 Y S/C track, Z track C/D track 204 TCz Temperature Coefficient of Transimpedance Gain 209 ∆Z()pn Transimpedance Gain Matching Of Paired Amplifiers 210 ∆Vout()pn Signal Matching no illumination, any output to any output 211 ∆Vout()pn Signal Matching no illumination, P vs. N path per diff. channel mW/ cm2 mW/ cm2 mW/ cm2 0.8 1.2 2.0 V/µW 0.1 0.2 0.16 0.32 0.3 0.6 V/µW V/µW 2.69 4.0 5.46 MΩ 0.67 1.34 1.0 2.0 1.36 2.72 MΩ MΩ %/◦ C -0.12 P.. channel vs. corresponding N.. channel mW/ cm2 mW/ cm2 mW/ cm2 -0.2 0.2 % -35 35 mV -2.5 2.5 mV preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 8/12 ELECTRICAL CHARACTERISTICS Operating conditions: VCC = 4.5...5.5 V, Tj = -40..125 ◦ C, unless otherwise stated Item No. 212 Symbol Parameter Conditions fc()hi Cut-off Frequency (-3 dB) chip release iC-PD3948. chip release iC-PD3948 Y 213 VNoise() RMS Output Noise illuminated to 500 mV signal level above dark level, 500 kHz band width Unit Min. Typ. Max. 120 240 180 360 280 560 0.5 kHz kHz mV Signal Outputs 301 Vout()mx Permissible Maximum Output Voltage illumination to E()mxr, linear gain 302 Vout()d Dark Signal Level no illumination, load 20 kΩ vs. +2 V; 303 Vout()acmx Maximum Signal Level Vout()acmx = Vout()mx - Vout()d 304 Isc()hi Short-Circuit Current hi load current to ground 305 Isc()lo Short-Circuit Current lo 306 Ri() Internal Output Resistance 2.45 2.72 3.02 V 560 770 1000 mV 1.48 1.96 2.35 V 100 420 800 µA load current to IC 250 480 700 µA f = 1 kHz 70 110 180 Ω Signal References VRSC, VRDC 401 Vout() Reference Voltage 560 770 1000 mV 402 Isc()hi Short-Circuit Current hi current to ground 100 420 800 µA 403 Isc()lo Short-Circuit Current lo current to IC 250 480 700 µA 404 Ri() Internal Output Resistance 70 110 180 Ω 770 1000 mV +10 mV Reference Voltages VREF 501 Vout() Reference Voltage I(VREF) = -100 µA...+300 µA 560 502 503 dVout() Load Balancing I(VREF) = -100 µA...+300 µA -10 Isc()hi Short-Circuit Current hi current to ground; chip release iC-PD3948. chip release iC-PD3948 Y 200 600 420 1100 800 1600 µA µA current to IC 0.5 4.5 10 mA 504 Isc()lo Short-Circuit Current lo preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 9/12 APPLICATION CIRCUITS +5V C5 100nF R6 2.2k VP R5 2.2k X4 X6 X3 X5 iC-TL85 D3 47 Disc iC-PD3948 C1 1μF I2C SDA SDA VN C7 100nF VDD C2 100nF D2 24xx R9 VDDS SCL SCL R1 1k iC-MSB ERR PS PSIN + - NS + NSIN PC PCOS - X1 + X2 - ACO VCC ERR Reverse Polarity Protection NC NCOS PZ SIGNAL LEVEL PZ NZ NZ CONTROL VREF GNDS GND VN PZ DPZ NZ TVS-Diode-Array VRSC DPC VRDC C6 100nF DNC PSIN R8 2.2k VP SCL NSIN DPSIN DPCOS DNCOS DNSIN PCOS 24xx VNSDA C4 100nF R7 2.2k VDDS SCL I2C SDA PC NC PD DND ND DNZ X4 X6 X3 ERR Reverse Polarity Protection NCOS DPD C3 1μF VDD iC-MSB PS PC + - NS + X5 - X1 + X2 - NC PC PD NC ND PZ GND ACO SIGNAL LEVEL NZ CONTROL GNDS GND TVS-Diode-Array Figure 1: Application example of a motor feedback encoder utilizing two iC-MSB devices. Sine square plus cosine square LED power controlling by iC-MSB maintains the differential 1 Vpp signal of the S/C channel featuring 2048 CPR. The C/D channel with 1 CPR is initially also calibrated to 1 Vpp differential, but experiences variation due to LED power controlling. This variation can be neglected at speeds below 1,500 rpm, as iC-PD3948 does not run into cut-off frequency. preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 10/12 +5V C3 100nF R6 2.2k VP SCL 24xx SDA VN C2 100nF R5 2.2k VDDS SCL C1 1μF VDD R1 1k D2 I2C SDA ERR Reverse Polarity Protection ERR iC-MSB X4 R9 - X3 + X5 iC-TL85 D3 47 Disc iC-PD3948 NSIN PC PCOS + X2 - VCC PSIN NS X1 ACO C7 100nF PS + X6 NC NCOS PZ SIGNAL LEVEL PZ NZ NZ CONTROL GNDS VREF GND VN PZ DPZ NZ VRSC DPC VRDC C6 100nF C5 100nF C4 1μF TVS-Diode-Array DNC PSIN VDDS SCL NSIN I2C SDA DPSIN DPCOS DNCOS DNSIN PC NC PD DND ND DNZ ERR Reverse Polarity Protection PCOS NCOS DPD VDD iC-MSA X4 X6 X3 X5 PS + - NS + PC - X1 + X2 - NC PZ GND AUTOMATIC GAIN NZ CONTROL GNDS GND Figure 2: Application example motor feedback encoder utilizing iC-MSB and iC-MSA. Sine square plus cosine square LED power controlling by iC-MSB maintains the differential 1 Vpp signal of the S/C channel featuring 2048 CPR. The C/D channel with 1 CPR ensures its 1 Vpp differential signal by automatic gain control. In this setup, operation at high rpm speed and beyond iC-MSB’s cut-off frequency is possible. PC NC PD ND preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 11/12 DESIGN REVIEW: Notes On Chip Functions iC-PD3948. No. Function, Parameter/Code Description and Application Hints 1 None at time of printing (datasheet release B5, 2011). The current datasheet (C1) introduces minor changes to Elec. Char. which are applicable to iC-PD3948. as well, but not functional relevant to applications. Refer to Revision History for details. 2 IC top marking Change of optoBGA package marking during 2014: <A-CODE> (assembly code) replaced by <P-CODE> (product code), <D-CODE> (date code) replaced by <A-CODE> (assembly code) Table 4: Notes on chip functions regarding iC-PD3948 chip release 0. iC-PD3948 Y, Y1 No. Function, Parameter/Code Description and Application Hints 1 HD Phased Array Chip release utilizes a high density phased array layout. 2 Transimpedance Gain Improvement of disturbance immunity by lower gain: for S/C and index channel from 4 MΩ to 1 MΩ, for C/D channel from 4 MΩ to 2 MΩ. Table 5: Notes on chip functions regarding iC-PD3948 chip release Y and Y1. REVISION HISTORY Rel Rel.Date Chapter B5 11-03-14 ... Modification Page Rel Rel.Date C1 14-07-31 Chapter Modification Page FEATURES Explanation of CPR and size Change of transimpedance (for chip release iC-PD3948 Y) 2 DESCRIPTION Description of HD Phased Array supplemented (for chip release iC-PD3948 Y) 2 PACKAGING INFORMATION Pad layout supplemented (for chip release iC-PD3948 Y) oQFN and oBGA package drawings updated for top marking oQFN package drawing updated for tolerances 3...5 THERMAL DATA Missing operating conditions and extended temperature added 6 ELECTRICAL CHARACTERISTICS Item 101, conditions: reference is λpk Item 104: wavelength 850 nm supplemented, item 105 excluded Item 106: adaption of limits (for chip release iC-PD3948.) Items 103, 106, 201, 202, 203, 212: supplements (for chip release iC-PD3948 Y) Items 302, 401, 501, 503: min. limit Items 501, 502: conditions 7, 8 APPLICATION CIRCUITS Fig. 1 corrected, description supplemented Fig. 2 replaced, description supplemented (iC-MSA in place of iC-TW3) 9,10 DESIGN REVIEW Chapter added 10 REVISION HISTORY Chapter added 11 iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by email. Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus products are not designed for and must not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (Safety-Critical Applications) without iC-Haus’ specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems. iC-Haus products are not designed nor intended for use in military or aerospace applications or environments or in automotive applications unless specifically designated for such use by iC-Haus. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. preliminary iC-PD 3948 PHASED ARRAY SINE ENCODER Rev C1, Page 12/12 ORDERING INFORMATION Type Package iC-PD3948 32-pin optoQFN, 5 mm x 5 mm, thickness 0.9 mm RoHS compliant iC-PD3948 oQFN32-5x5 15-pin optoBGA, 6.2 mm x 5.2 mm thickness 1.7 mm RoHS compliant iC-PD3948 oBGA LSH2C PCB (60 mm x 40 mm), with LED and code disc assembled with optoBGA iC-PD3948 EVAL LSH2M Evaluation Kit Code Disc Options 2048 CPR (S/C) with index, 1 CPR (C/D) absolute, OD ∅ 39 mm, ID ∅ 18.0 mm, optical radius 17.5 mm (glass 1 mm) Order Designation PD2S 39-2048 For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (0) 61 35 - 92 92 - 0 Fax: +49 (0) 61 35 - 92 92 - 192 Web: http://www.ichaus.com E-Mail: [email protected] Appointed local distributors: http://www.ichaus.com/sales_partners