TI1 OPA350UA High-speed, single-supply, rail-to-rail operational amplifier Datasheet

OPA350
OPA2350
OPA4350
SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
High-Speed, Single-Supply, Rail-to-Rail
OPERATIONAL AMPLIFIERS
MicroAmplifiertSeries
FEATURES
DESCRIPTION
D
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The OPA350 series rail-to-rail CMOS operational
amplifiers are optimized for low voltage, single-supply
operation. Rail-to-rail input/output, low noise (5nV/√Hz),
and high speed operation (38MHz, 22V/µs) make them
ideal for driving sampling Analog-to-Digital (A/D)
converters. They are also well suited for cell phone PA
control loops and video processing (75Ω drive capability)
as well as audio and general purpose applications. Single,
dual, and quad versions have identical specifications for
maximum design flexibility.
RAIL-TO-RAIL INPUT
RAIL-TO-RAIL OUTPUT (within 10mV)
WIDE BANDWIDTH: 38MHz
HIGH SLEW RATE: 22V/µs
LOW NOISE: 5nV/√Hz
LOW THD+NOISE: 0.0006%
UNITY-GAIN STABLE
MicroSIZE PACKAGES
SINGLE, DUAL, AND QUAD
The OPA350 series operates on a single supply as low as
2.5V with an input common-mode voltage range that
extends 300mV below ground and 300mV above the
positive supply. Output voltage swing is to within 10mV of
the supply rails with a 10kΩ load. Dual and quad designs
feature completely independent circuitry for lowest
crosstalk and freedom from interaction.
APPLICATIONS
D
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CELL PHONE PA CONTROL LOOPS
DRIVING A/D CONVERTERS
VIDEO PROCESSING
DATA ACQUISITION
PROCESS CONTROL
AUDIO PROCESSING
COMMUNICATIONS
ACTIVE FILTERS
TEST EQUIPMENT
The single (OPA350) and dual (OPA2350) come in the
miniature MSOP-8 surface mount, SO-8 surface mount,
and DIP-8 packages. The quad (OPA4350) packages are
the space-saving SSOP-16 surface mount and SO-14
surface mount. All are specified from −40°C to +85°C and
operate from −55°C to +150°C.
SPICE model available at www.ti.com
OPA350
NC
1
8
NC
−In
2
7
V+
+In
3
6
Output
V−
4
5
NC
OPA4350
OPA4350
Out A
1
14
Out D
−In A
2
13
− In D
+In A
3
12
+In D
V+
4
11
V−
A
D
DIP−8, SO−8, MSOP−8
OPA2350
+In B
Out A
1
−In A 2
+In A
3
−
4
8
A
B
5
7
Out B
6
−In B
5
+In B
10
B
V+
+In C
C
−In B
6
9
− In C
Out B
7
8
Out C
Out A
1
16
Out D
− In A
2
15
−In D
+In A
3
14
+In D
A
D
+V
4
13
−V
+In B
5
12
+In C
− In B
6
11
−In C
Out B
7
10
Out C
NC
8
9
NC
B
C
SO−14
SSOP−16
DIP−8, SO−8, MSOP−8
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2000−2005, Texas Instruments Incorporated
! ! www.ti.com
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SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC DISCHARGE SENSITIVITY
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Signal Input Terminals(2), Voltage . . . . . (V−) − 0.3V to (V+) + 0.3V
Current . . . . . . . . . . . . . . . . . . . . . . 10mA
Open Short-Circuit Current(3) . . . . . . . . . . . . . . . . . . . . Continuous
Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +150°C
Storage Temperature Range . . . . . . . . . . . . . . . . . −55°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
(2) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.3V beyond the supply
rails should be current limited to 10mA or less.
(3) Short-circuit to ground, one amplifier per package.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
MSOP-8
DGK
−40°C to +85°C
C50
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA350EA/250
Tape and Reel, 250
OPA350EA/2K5
Tape and Reel, 2500
SINGLE
OPA350EA
OPA350UA
SO-8
D
−40°C to +85°C
OPA350UA
OPA350PA
DIP-8
P
−40°C to +85°C
OPA350PA
OPA2350EA
MSOP-8
DGK
−40°C to +85°C
D50
OPA2350UA
SO-8
D
−40°C to +85°C
OPA2350UA
OPA2350PA
DIP-8
P
−40°C to +85°C
OPA2350PA
OPA4350EA
SSOP-16
DBQ
−40°C to +85°C
OPA4350EA
OPA4350UA
SO-14
D
−40°C to +85°C
OPA4350UA
OPA350UA
Rails
OPA350UA/2K5
Tape and Reel, 2500
OPA350PA
Rails
DUAL
OPA2350EA/250
Tape and Reel, 250
OPA2350EA/2K5
Tape and Reel, 2500
OPA2350UA
Rails
OPA2350UA/2K5
Tape and Reel, 2500
OPA2350PA
Rails
QUAD
OPA4350EA/250
Tape and Reel, 250
OPA4350EA/2K5
Tape and Reel, 2500
OPA4350UA
Rails
OPA4350UA/2K5
Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
2
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SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS: VS = 2.7V to 5.5V
Boldface limits apply over the temperature range, TA = −40°C to +85°C. VS = 5V.
All specifications at TA = +25°C, RL = 1kΩ connected to VS/2 and VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
OPA350, OPA2350, OPA4350
MIN
TYP(1)
MAX
VS = 5V
±150
UNIT
OFFSET VOLTAGE
Input Offset Voltage
VOS
TA = −40°C to +85°C
vs Temperature
vs Power-Supply Rejection Ratio
PSRR
TA = −40°C to +85°C
Channel Separation (dual, quad)
TA = −40°C to +85°C
VS = 2.7V to 5.5V, VCM = 0V
VS = 2.7V to 5.5V, VCM = 0V
±4
dc
0.15
40
±500
µV
±1
mV
µV/°C
150
µV/V
175
µV/V
µV/V
INPUT BIAS CURRENT
Input Bias Current
±0.5
IB
vs Temperature
Input Offset Current
±10
pA
See Typical Characteristics
±0.5
IOS
±10
pA
NOISE
Input Voltage Noise, f = 100Hz to 400kHz
Input Voltage Noise Density, f = 10kHz
en
Input Current Noise Density, f = 100kHz
Current Noise Density, f = 10kHz
in
4
µVrms
7
nV/√Hz
5
nV/√Hz
4
fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
VCM
CMRR
TA = −40°C to +85°C
INPUT IMPEDANCE
TA = −40°C to +85°C
VS = 2.7V, −0.1V < VCM < 2.8V
VS = 5.5V, −0.1V < VCM < 5.6V
−0.1
VS = 5.5V, −0.1V < VCM < 5.6V
74
(V+) + 0.1
V
66
84
dB
74
90
dB
Differential
Common-Mode
dB
1013 || 2.5
1013 || 6.5
Ω || pF
122
dB
Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain
AOL
TA = −40°C to +85°C
TA = −40°C to +85°C
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
100
100
dB
120
dB
dB
G=1
38
MHz
G=1
22
V/µs
G = ±1, 2V Step
0.22
µs
G = ±1, 2V Step
0.5
µs
0.1
µs
0.0006
%
Overload Recovery Time
Differential Phase Error
RL = 1kW, 200mV < VO < (V+) −200mV
CL = 100pF
100
SR
0.01%
Differential Gain Error
100
GBW
Settling Time: 0.1%
Total Harmonic Distortion + Noise
RL = 10kΩ, 50mV < VO < (V+) −50mV
RL = 10kW, 50mV < VO < (V+) −50mV
RL = 1kΩ, 200mV < VO < (V+) −200mV
THD+N
VIN • G = VS
RL = 600Ω, VO = 2.5VPP(2), G = 1, f = 1kHz
G = 2, RL = 600Ω, VO = 1.4V(3)
G = 2, RL = 600Ω, VO = 1.4V(3)
0.17
%
0.17
deg
(1) VS = +5V.
(2) VOUT = 0.25V to 2.75V.
(3) NTSC signal generator used. See Figure 6 for test circuit.
(4) Output voltage swings are measured between the output and power supply rails.
(5) See typical characteristic curve, Output Voltage Swing vs Output Current.
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SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS: VS = 2.7V to 5.5V (continued)
Boldface limits apply over the temperature range, TA = −40°C to +85°C. VS = 5V.
All specifications at TA = +25°C, RL = 1kΩ connected to VS/2 and VOUT = VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
OPA350, OPA2350, OPA4350
MIN
TYP(1)
MAX
UNIT
10
50
mV
50
mV
200
mV
200
mV
OUTPUT
Voltage Output Swing from Rail(4)
VOUT
TA = −40°C to +85°C
TA = −40°C to +85°C
Output Current
Short-Circuit Current
Capacitive Load Drive
RL = 10kΩ, AOL ≥ 100dB
RL = 10kW, AOL 100dB
RL = 1kΩ, AOL ≥ 100dB
25
RL = 1kW, AOL 100dB
IOUT
ISC
CLOAD
±40(5)
mA
±80
mA
See Typical Characteristics
POWER SUPPLY
Operating Voltage Range
VS
TA = −40°C to +85°C
2.7
Minimum Operating Voltage
Quiescent Current (per amplifier)
5.5
V
7.5
mA
8.5
mA
2.5
IQ
TA = −40°C to +85°C
TEMPERATURE RANGE
IO = 0
IO = 0
5.2
V
Specified Range
−40
+85
°C
Operating Range
−55
+150
°C
Storage Range
−55
+150
°C
Thermal Resistance
qJA
MSOP-8 Surface Mount
150
°C/W
SO-8 Surface Mount
150
°C/W
DIP-8
100
°C/W
SO-14 Surface Mount
100
°C/W
SSOP-16 Surface Mount
100
°C/W
(1) VS = +5V.
(2) VOUT = 0.25V to 2.75V.
(3) NTSC signal generator used. See Figure 6 for test circuit.
(4) Output voltage swings are measured between the output and power supply rails.
(5) See typical characteristic curve, Output Voltage Swing vs Output Current.
4
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SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
All specifications at TA = +25°C, VS = +5V, and RL = 1kΩ connected to VS/2, unless otherwise noted.
POWER SUPPLY AND COMMON−MODE
REJECTION RATIO vs FREQUENCY
OPEN-LOOP GAIN/PHASE vs FREQUENCY
160
100
0
90
φ
80
−90
60
G
PSRR, CMRR (dB)
100
−135
40
PSRR
80
−45
120
Phase (_)
Voltage Gain (dB)
140
20
70
CMRR
(VS = +5V
VCM = −0.1V to 5.1V)
60
50
40
30
20
0
0.1
1
10
100
1k
10k 100k
Frequency (Hz)
−180
10M 100M
1M
10
0
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
INPUT VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
CHANNEL SEPARATION vs FREQUENCY
140
10k
100k
1k
Current Noise
100
1k
Voltage Noise
100
10
10
1
Current Noise (fA√Hz)
Voltage Noise (nV√Hz)
10k
Channel Separation (dB)
130
120
110
100
90
80
70
1
10
100
1k
10k
100k
1M
Dual and quad devices.
60
0.1
10M
10
100
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
0.01
G = 10, 3VPP (VO = 1V to 4V)
Harmonic Distortion (%)
THD+N (%)
RL = 600Ω
G = 100, 3VPP (VO = 1V to 4V)
G = 1, 3VPP (VO = 1V to 4V)
Input goes through transition region
0.001
G = 1, 2.5VPP (VO = 0.25V to 2.75V)
Input does NOT go through transition region
100
1k
Frequency (Hz)
100k
1M
10M
10k
0.1
(−60dBc)
G=1
VO = 2.5VPP
RL = 600Ω
0.01
(−80dBc)
0.001
(−100dBc)
3rd−Harmonic
2nd−Harmonic
0.0001
10
10k
HARMONIC DISTORTION + NOISE vs FREQUENCY
1
(−40dBc)
1
0.1
1k
Frequency (Hz)
Frequency (Hz)
100k
0.0001
(−120dBc) 1k
10k
100k
1M
Frequency (Hz)
5
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SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +5V, and RL = 1kΩ connected to VS/2, unless otherwise noted.
OPEN−LOOP GAIN vs TEMPERATURE
DIFFERENTIAL GAIN/PHASE vs RESISTIVE LOAD
130
0.5
Open−Loop Gain (dB)
0.4
Differential Gain (%)
Differential Phase (_)
G=2
VO = 1.4V
NTSC Signal Generator
See Figure 6 for test circuit.
Phase
0.3
0.2
Gain
125
RL = 1kΩ
RL = 10kΩ
120
RL = 600Ω
115
0.1
110
0
0
100 200 300 400
500 600
−75
700 800 900 1000
−50
−25
Resistive Load ( Ω )
50
75
100
125
40
35
90
CMRR, VS = 2.7V
(VCM = −0.1V to +2.8V)
PSRR
70
Slew Rate (V/µs)
30
100
PSRR (dB)
90
CMRR (dB)
25
SLEW RATE vs TEMPERATURE
COMMON−MODE AND POWER−SUPPLY REJECTION RATIO
vs TEMPERATURE
100
110
CMRR, VS = 5.5V
(VCM = −0.1V to +5.6V)
80
0
Temperature (_ C)
Negative Slew Rate
25
Positive Slew Rate
20
15
10
80
5
60
−75
−50
−25
0
25
50
75
100
0
70
125
−75
−50
−25
100
6
−ISC
80
5.5
70
IQ
60
4.5
50
4.0
40
30
0
25
50
Temperature (_C)
75
100
125
Quiescent Current (mA)
90
−25
100
125
5.5
Short−Circuit Current (mA)
Quiescent Current (mA)
6.5
−50
75
Per Amplifier
+ISC
3.5
−75
50
6.0
7.0
5.0
25
QUIESCENT CURRENT vs SUPPLY VOLTAGE
QUIESCENT CURRENT AND
SHORT−CIRCUIT CURRENT vs TEMPERATURE
6.0
0
Temperature (_C)
Temperature (_C)
5.0
4.5
4.0
3.5
3.0
2.0
2.5
3.0
3.5
4.0
Supply Voltage (V)
4.5
5.0
5.5
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SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +5V, and RL = 1kΩ connected to VS/2, unless otherwise noted.
INPUT BIAS CURRENT
vs INPUT COMMON−MODE VOLTAGE
INPUT BIAS CURRENT vs TEMPERATURE
1.5
100
1.0
Input Bias Current (pA)
Input Bias Current (pA)
1k
10
1
−50
−25
0
25
50
Temperature (_ C)
75
100
0.0
−0.5
−0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.1
−75
0.5
125
Common−Mode Voltage (V)
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
6
10
5
Output Voltage (VPP)
Output Impedance (Ω)
CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY
100
1
0.1
G = 100
0.01
G = 10
0.001
G=1
10
Maximum output
voltage without
slew rate−induced
distortion.
4
VS = 2.7V
3
2
1
0
100k
0.0001
1
VS = 5.5V
100
1k
10k
100k
1M
10M
100M
1M
Frequency (Hz)
100M
OPEN−LOOP GAIN vs OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
140
V+
−55_C
+125_ C
(V+)−2
Open−Loop Gain (dB)
(V+)−1
+25_C
Depending on circuit configuration
(including closed−loop gain) performance
may be degraded in shaded region.
(V−)+2
−55_C
+25_C
+125_C
(V−)+1
I OUT = 2.5mA
IOUT = 250µA
130
Output Voltage (V)
10M
Frequency (Hz)
120
110
IOUT = 4.2mA
100
90
80
70
60
(V−)
0
±10
±20
Output Current (mA)
±30
±40
0
20
40
60
80
100 120
140 160 180 200
Output Voltage Swing from Rails (mV)
7
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SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VS = +5V, and RL = 1kΩ connected to VS/2, unless otherwise noted.
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
18
20
Typical distribution of
packaged units.
16
Typical production
distribution of
packaged units.
18
14
16
Percent of Amplifiers (%)
Percent of Amplifiers (%)
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
12
10
8
6
4
14
12
10
8
6
4
2
2
0
−500
−450
−400
−350
−300
−250
−200
−150
−100
−50
0
50
100
150
200
250
300
350
400
450
500
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Offset Voltage Drift (µV/_C)
Offset Voltage (µV)
SETTLING TIME vs CLOSED−LOOP GAIN
SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE
10
80
70
G=1
50
Settling Time (µs)
Overshoot (%)
60
G = −1
40
30
G = ±10
20
0.01%
1
10
0.1%
0.1
0
10
100
1k
10k
100k
−1
1M
Load Capacitance (pF)
LARGE−SIGNAL STEP RESPONSE
CL = 100pF
1V/div
50mV/div
SMALL−SIGNAL STEP RESPONSE
CL = 100pF
100ns/div
8
−10
Closed−Loop Gain (V/V)
200ns/div
−100
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SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
APPLICATIONS INFORMATION
OPA350 series op amps are fabricated on a
state-of-the-art 0.6 micron CMOS process. They are
unity-gain stable and suitable for a wide range of
general-purpose applications. Rail-to-rail input/output
make them ideal for driving sampling A/D converters.
They are also well-suited for controlling the output
power in cell phones. These applications often require
high speed and low noise. In addition, the OPA350
series offers a low-cost solution for general-purpose
and consumer video applications (75Ω drive capability).
Excellent ac performance makes the OPA350 series
well-suited for audio applications. Their bandwidth,
slew rate, low noise (5nV/√Hz), low THD (0.0006%),
and small package options are ideal for these
applications. The class AB output stage is capable of
driving 600Ω loads connected to any point between V+
and ground.
Rail-to-rail input and output swing significantly
increases dynamic range, especially in low voltage
supply applications. Figure 1 shows the input and
output waveforms for the OPA350 in unity-gain
configuration. Operation is from a single +5V supply
with a 1kΩ load connected to VS/2. The input is a 5VPP
sinusoid. Output voltage swing is approximately
4.95VPP.
Power supply pins should be bypassed with 0.01µF
ceramic capacitors.
VS = +5, G = +1, RL = 1kΩ
5V
1.25V/div
VIN
0
5V
VOUT
0
Figure 1. Rail-to-Rail Input and Output
OPERATING VOLTAGE
OPA350 series op amps are fully specified from +2.7V
to +5.5V. However, supply voltage may range from
+2.5V to +5.5V. Parameters are tested over the
specified supply range—a unique feature of the
OPA350 series. In addition, many specifications apply
from −40°C to +85°C. Most behavior remains virtually
unchanged throughout the full operating voltage range.
Parameters that vary significantly with operating
voltage or temperature are shown in the typical
characteristics.
RAIL-TO-RAIL INPUT
The tested input common-mode voltage range of the
OPA350 series extends 100mV beyond the supply rails.
This is achieved with a complementary input stage—an
N-channel input differential pair in parallel with a
P-channel differential pair, as shown in Figure 2. The
N-channel pair is active for input voltages close to the
positive rail, typically (V+) – 1.8V to 100mV above the
positive supply, while the P-channel pair is on for inputs
from 100mV below the negative supply to
approximately (V+) – 1.8V. There is a small transition
region, typically (V+) – 2V to (V+) – 1.6V, in which both
pairs are on. This 400mV transition region can vary
±400mV with process variation. Thus, the transition
region (both input stages on) can range from (V+) –
2.4V to (V+) – 2.0V on the low end, up to (V+) – 1.6V
to (V+) – 1.2V on the high end.
OPA350 series op amps are laser-trimmed to reduce
offset voltage difference between the N-channel and
P-channel input stages, resulting in improved
common-mode rejection and a smooth transition
between the N-channel pair and the P-channel pair.
However, within the 400mV transition region PSRR,
CMRR, offset voltage, offset drift, and THD may be
degraded compared to operation outside this region.
A double-folded cascode adds the signal from the two
input pairs and presents a differential signal to the class
AB output stage. Normally, input bias current is
approximately 500fA. However, large inputs (greater
than 300mV beyond the supply rails) can turn on the
OPA350’s input protection diodes, causing excessive
current to flow in or out of the input pins. Momentary
voltages greater than 300mV beyond the power supply
can be tolerated if the current on the input pins is limited
to 10mA. This is easily accomplished with an input
resistor, as shown in Figure 3. Many input signals are
inherently current-limited to less than 10mA; therefore,
a limiting resistor is not required.
9
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SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
V+
Reference
Current
VIN+
VIN−
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V−
(Ground)
Figure 2. Simplified Schematic
within a few tens of millivolts from the supply rails and
maintain high open-loop gain. See the typical
characteristics Output Voltage Swing vs Output Current
and Open-Loop Gain vs Output Voltage.
CAPACITIVE LOAD AND STABILITY
V+
IOVERLOAD
10mA max
OPAx350
VOUT
VIN
5kΩ
Figure 3. Input Current Protection for Voltages
Exceeding the Supply Voltage
RAIL-TO-RAIL OUTPUT
A class AB output stage with common-source
transistors is used to achieve rail-to-rail output. For light
resistive loads (>10kΩ), the output voltage swing is
typically ten millivolts from the supply rails. With heavier
resistive loads (600Ω to 10kΩ), the output can swing to
10
OPA350 series op amps can drive a wide range of
capacitive loads. However, all op amps under certain
conditions may become unstable. Op amp
configuration, gain, and load value are just a few of the
factors to consider when determining stability. An op
amp in unity-gain configuration is the most susceptible
to the effects of capacitive load. The capacitive load
reacts with the op amp’s output impedance, along with
any additional load resistance, to create a pole in the
small-signal response that degrades the phase margin.
In unity gain, OPA350 series op amps perform well with
very large capacitive loads. Increasing gain enhances
the amplifier’s ability to drive more capacitance. The
typical characteristic Small-Signal Overshoot vs
Capacitive Load shows performance with a 1kΩ
resistive load. Increasing load resistance improves
capacitive load drive capability.
"#$
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&"#$
www.ti.com
SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
FEEDBACK CAPACITOR IMPROVES
RESPONSE
For optimum settling time and stability with
high-impedance feedback networks, it may be
necessary to add a feedback capacitor across the
feedback resistor, RF, as shown in Figure 4. This
capacitor compensates for the zero created by the
feedback network impedance and the OPA350’s input
capacitance (and any parasitic layout capacitance).
The effect becomes more significant with higher
impedance networks.
series provides an effective means of buffering the
A/D’s input capacitance and resulting charge injection
while providing signal gain.
Figure 5 shows the OPA350 driving an ADS7861. The
ADS7861 is a dual, 500kHz, 12-bit sampling converter
in the tiny SSOP-24 package. When used with the
miniature package options of the OPA350 series, the
combination is ideal for space-limited applications. For
further information, consult the ADS7861 data sheet
(SBAS110A).
OUTPUT IMPEDANCE
CF
R IN
RF
VIN
V+
CIN
RIN • CIN = RF • CF
VOUT
O PA350
CL
CIN
Where CIN is equal to the OPA350’s input
capacitance (approximately 9pF) plus any
parasitic layout capacitance.
Figure 4. Feedback Capacitor Improves Dynamic
Performance
It is suggested that a variable capacitor be used for the
feedback capacitor since input capacitance may vary
between op amps and layout capacitance is difficult to
determine. For the circuit shown in Figure 4, the value
of the variable feedback capacitor should be chosen so
that the input resistance times the input capacitance of
the OPA350 (typically 9pF) plus the estimated parasitic
layout capacitance equals the feedback capacitor times
the feedback resistor:
R IN @ C IN + RF @ CF
where CIN is equal to the OPA350’s input capacitance
(sum of differential and common-mode) plus the layout
capacitance. The capacitor can be varied until optimum
performance is obtained.
DRIVING A/D CONVERTERS
OPA350 series op amps are optimized for driving
medium speed (up to 500kHz) sampling A/D
converters. However, they also offer excellent
performance for higher speed converters. The OPA350
The low frequency open-loop output impedance of the
OPA350’s
common-source
output
stage
is
approximately 1kΩ. When the op amp is connected with
feedback, this value is reduced significantly by the loop
gain of the op amp. For example, with 122dB of
open-loop gain, the output impedance is reduced in
unity-gain to less than 0.001Ω. For each decade rise in
the closed-loop gain, the loop gain is reduced by the
same amount which results in a ten-fold increase in
effective output impedance (see the typical
characteristic, Output Impedance vs Frequency).
At higher frequencies, the output impedance will rise as
the open-loop gain of the op amp drops. However, at
these frequencies the output also becomes capacitive
due to parasitic capacitance. This prevents the output
impedance from becoming too high, which can cause
stability problems when driving capacitive loads. As
mentioned previously, the OPA350 has excellent
capacitive load drive capability for an op amp with its
bandwidth.
VIDEO LINE DRIVER
Figure 6 shows a circuit for a single supply, G = 2
composite video line driver. The synchronized outputs
of a composite video line driver extend below ground.
As shown, the input to the op amp should be ac-coupled
and shifted positively to provide adequate signal swing
to account for these negative signals in a single-supply
configuration.
The input is terminated with a 75Ω resistor and
ac-coupled with a 47µF capacitor to a voltage divider
that provides the dc bias point to the input. In Figure 6,
this point is approximately (V−) + 1.7V. Setting the
optimal bias point requires some understanding of the
nature of composite video signals. For best
performance, one should be careful to avoid the
distortion caused by the transition region of the
OPA350’s complementary input stage. Refer to the
discussion of rail-to-rail input.
11
"#$
%"#$
&"#$
www.ti.com
SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
CB1
2
4
1
1/ 4
3
VIN B1
+5V
2kΩ
2kΩ
O P A 43 5 0
0.1µF
0.1µF
CB0
24
2kΩ
2kΩ
2
3
6
7
1/ 4
5
VIN B0
4
O P A 43 5 0
5
6
CA1
7
2kΩ
2kΩ
8
9
9
8
1/ 4
10
VIN A1
13
+VD
O P A 43 5 0
10
11
CA0
+VA
CH B1+
SERIAL DATA A
CH B1−
SERIAL DATA B
CH B0+
BUSY
CH B0−
CLOCK
CH A1+
CS
CH A1−
ADS7861
RD
CH A0+
CONVST
CH A0−
A0
REFIN
M0
REFOUT
M1
DGND
1
AGND
12
2kΩ
2kΩ
12
14
1/ 4
VIN A0
13
O P A 43 5 0
11
VIN = 0V to 2.45V for 0V to 4.9V output.
Choose CB1, CB0, CA1, CA0 to filter high frequency noise.
Figure 5. OPA4350 Driving Sampling A/D Converter
12
23
22
21
20
19
18
17
16
15
14
Serial
Interface
"#$
%"#$
&"#$
www.ti.com
SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
RF
1kΩ
RG
1kΩ
+5V
C1
220µF
C4
0.1µF
0.1µF
2
+
10µF
7
C5
1000µF
6
C2
47µF
Video
In
ROUT
Cable
VOUT
OPA350
RL
3
R1
75Ω
4
R2
5kΩ
R3
5kΩ
R4
5kΩ
+5V (pin 7)
C3
10µF
Figure 6. Single-Supply Video Line Driver
+5V
50kΩ
(2.5V)
8
RG
REF1004−2.5
4
R1
100kΩ
R2
25kΩ
+5V
1/ 2
R3
25kΩ
R4
100kΩ
O P A 2 35 0
1/ 2
VO
O P A 23 5 0
G=5+
200kΩ
RG
RL
10kΩ
Figure 7. Two Op-Amp Instrumentation Amplifier With
Improved High Frequency Common-Mode Rejection
13
"#$
%"#$
&"#$
www.ti.com
SBOS099C − SEPTEMBER 2000 − REVISED JANUARY 2005
R1
10.5kΩ
C1
4.7nF
+2.5V
+2.5V
R1
2.74kΩ
R2
19.6kΩ
RL
20kΩ
VIN
C2
1nF
−2.5V
Figure 8. 10kHz Low-Pass Filter
14
C1
1830pF
VOUT
OPA350
C2
270pF
VOUT
OPA350
RL
20kΩ
VIN
R2
49.9kΩ
−2.5V
Figure 9. 10kHz High-Pass Filter
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
OPA2350EA/250
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
D50
OPA2350EA/250G4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
D50
OPA2350EA/2K5
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
D50
OPA2350EA/2K5G4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
D50
OPA2350PA
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
OPA2350PA
OPA2350PAG4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
OPA2350PA
OPA2350UA
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2350UA
OPA2350UA/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2350UA
OPA2350UA/2K5G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2350UA
OPA2350UAG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
2350UA
OPA350EA/250
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
C50
OPA350EA/250G4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
C50
OPA350EA/2K5
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
C50
OPA350EA/2K5G4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
C50
OPA350PA
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
OPA350PA
OPA350PAG4
ACTIVE
PDIP
P
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
OPA350PA
OPA350UA
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
350UA
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
OPA350UA/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
350UA
OPA350UA/2K5G4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
350UA
OPA350UAG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
350UA
OPA4350EA/250
ACTIVE
SSOP
DBQ
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA
4350EA
OPA4350EA/250G4
ACTIVE
SSOP
DBQ
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA
4350EA
OPA4350EA/2K5
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
4350EA
OPA4350EA/2K5G4
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
4350EA
OPA4350UA
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA4350UA
OPA4350UA/2K5
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA4350UA
OPA4350UA/2K5G4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA4350UA
OPA4350UAG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA4350UA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2350EA/250
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2350EA/2K5
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA350EA/250
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA350UA/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA4350EA/250
SSOP
DBQ
16
250
180.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA4350EA/2K5
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA4350UA/2K5
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2350EA/250
VSSOP
DGK
8
250
210.0
185.0
35.0
OPA2350EA/2K5
VSSOP
DGK
8
2500
367.0
367.0
35.0
OPA350EA/250
VSSOP
DGK
8
250
210.0
185.0
35.0
OPA350UA/2K5
SOIC
D
8
2500
367.0
367.0
35.0
OPA4350EA/250
SSOP
DBQ
16
250
210.0
185.0
35.0
OPA4350EA/2K5
SSOP
DBQ
16
2500
367.0
367.0
35.0
OPA4350UA/2K5
SOIC
D
14
2500
367.0
367.0
38.0
Pack Materials-Page 2
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