Cypress CY8C24794-24LFXIT Psocâ® programmable system-on-chip Datasheet

CY8C24094, CY8C24794
CY8C24894, CY8C24994
PSoC® Programmable System-on-Chip
1. Features
■
XRES Pin to Support In-System Serial Programming (ISSP)
and External Reset Control in CY8C24894
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3V to 5.25V Operating Voltage
❐ Industrial Temperature Range: -40°C to +85°C
❐ USB Temperature Range: -10°C to +85°C
■
Advanced Peripherals (PSoC® Blocks)
❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPI/O Pins
❐ Complex Peripherals by Combining Blocks
❐ Capacitive Sensing Application Capability
Logic Block Diagram
Full Speed USB (12 Mbps)
❐ Four Uni-Directional Endpoints
❐ One Bi-Directional Control Endpoint
❐ USB 2.0 Compliant
❐ Dedicated 256 Byte Buffer
❐ No External Crystal Required
■
Flexible On-Chip Memory
❐ 16K Flash Program Storage 50,000 Erase and Write Cycles
❐ 1K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPI/O
❐ Up to 48 Analog Inputs on GPI/O
❐ Two 33 mA Analog Outputs on GPI/O
❐ Configurable Interrupt on all GPI/O
■
Precision, Programmable Clocking
❐ Internal ±4% 24 and 48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
❐ 0.25% Accuracy for USB with no External Components
Additional System Resources
2
❐ I C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User Configurable Low Voltage Detection
■
P o rt 5
P o rt 7
System Bus
■
P o rt 4
P o rt 3
G lo b a l D ig ita l In t e r c o n n e c t
P o rt 2
P o rt 1
P o rt 0
A n a lo g
D r iv e r s
G lo b a l A n a lo g In te r c o n n e c t
PSoC C O R E
SR AM
1K
SR O M
F la s h 1 6 K
S le e p a n d
W a tc h d o g
C P U C o re (M 8 C )
In te rru p t
C o n tr o lle r
C lo c k S o u r c e s
( I n c lu d e s IM O a n d I L O )
D IG IT A L
S Y S TEM
A N A LO G
SYSTEM
A n a lo g
R e f.
D ig ita l
B lo c k
A rra y
D ig ita l
C lo c k s
2
M AC s
D e c im a to r
Type 2
A n a lo g
B lo c k
A rra y
I2 C
PO R and LVD
S y s te m R e s e ts
In te rn a l
V o lta g e
R e f.
U S B
A n a lo g
In p u t
M u x in g
SY S TE M R E S O U R C E S
Cypress Semiconductor Corporation
Document Number: 38-12018 Rev. *U
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 30, 2010
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2. Contents
Features ...............................................................................1
Logic Block Diagram ..........................................................1
Contents ..............................................................................2
PSoC Functional Overview ................................................3
The PSoC Core .............................................................3
The Digital System ........................................................3
The Analog System .......................................................4
Additional System Resources .......................................5
PSoC Device Characteristics ........................................5
Getting Started ....................................................................5
Application Notes ..........................................................5
Development Kits ..........................................................5
Training .........................................................................5
CyPros Consultants .......................................................5
Solutions Library ............................................................5
Technical Support .........................................................5
Development Tools ............................................................6
PSoC Designer Software Subsystems ..........................6
In-Circuit Emulator .........................................................6
Designing with PSoC Designer .........................................7
Select Components .......................................................7
Configure Components .................................................7
Organize and Connect ..................................................7
Generate, Verify, and Debug .........................................7
Document Conventions .....................................................8
Acronyms Used .............................................................8
Units of Measure ...........................................................8
Numeric Naming ............................................................8
Pin Information ...................................................................9
56-Pin Part Pinout ........................................................9
56-Pin Part Pinout (with XRES) ..................................10
68-Pin Part Pinout .......................................................11
Document Number: 38-12018 Rev. *U
68-Pin Part Pinout (On-Chip Debug) ...........................12
100-Ball VFBGA Part Pinout .......................................13
100-Ball VFBGA Part Pinout (On-Chip Debug) ...........14
100-Pin Part Pinout (On-Chip Debug) .........................16
Register Reference ...........................................................18
Register Conventions ..................................................18
Register Mapping Tables ............................................18
Register Map Bank 0 Table: User Space ...................19
Register Map Bank 1 Table: Configuration Space .....20
Electrical Specifications ..................................................21
Absolute Maximum Ratings .........................................22
Operating Temperature ...............................................22
DC Electrical Characteristics .......................................23
AC Electrical Characteristics .......................................31
Packaging Dimensions ....................................................39
Thermal Impedance ....................................................43
Solder Reflow Peak Temperature ...............................43
Development Tool Selection ...........................................44
Software ......................................................................44
Development Kits ........................................................44
Evaluation Tools ..........................................................44
Device Programmers ...................................................45
Accessories (Emulation and Programming) ................45
Ordering Information ........................................................46
Ordering Code Definitions ...........................................47
Document History Page ...................................................48
Sales, Solutions, and Legal Information ........................50
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The PSoC family consists of many programmable
system-on-chips with On-Chip Controller devices. All PSoC
family devices are designed to replace traditional MCUs, system
ICs, and the numerous discrete components that surround them.
The PSoC CY8C24x94 devices are unique members of the
PSoC family because it includes a full featured, full speed (12
Mbps) USB port. Configurable analog, digital, and interconnect
circuitry enable a high level of integration in a host of industrial,
consumer, and communication applications.
3.2 The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource used alone or combined with
other blocks to form 8, 16, 24, and 32-bit peripherals, which are
called user modules.
Figure 3-1. Digital System Block Diagram
Port 7
This architecture enables the user to create customized
peripheral configurations that match the requirements of each
individual application. Additionally, a fast CPU, Flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts and packages.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 8%
over temperature and voltage. The 24 MHz IMO can also be
doubled to 48 MHz for use by the digital system. A low power 32
kHz ILO (internal low speed oscillator) is provided for the Sleep
timer and WDT. The clocks, together with programmable clock
dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC device. In
USB systems, the IMO self tunes to ± 0.25% accuracy for USB
communication.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin is also capable of generating a system interrupt
on high level, low level, and change from last read.
Document Number: 38-12018 Rev. *U
To System Bus
Port 0
To Analog
System
DIGITAL SYSTEM
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
Port 1
Port 2
Digital PSoC Block Array
3.1 The PSoC Core
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Port 3
Digital Clocks
From Core
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources including a full speed USB port. Configurable global busing enables all the device resources to be
combined into a complete custom system. The PSoC
CY8C24x94 devices can have up to seven I/O ports that connect
to the global digital and analog interconnects, providing access
to 4 digital blocks and 6 analog blocks.
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPI/O (General Purpose I/O).
Port 5
Port 4
Row Input
Configuration
3. PSoC Functional Overview
8
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include the following:
■
Full Speed USB (12 Mbps)
■
PWMs (8 to 32 bit)
■
PWMs with Dead band (8 to 24 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity
■
SPI master and slave
■
I2C slave and multi-master
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks are connected to any GPI/O through a series
of global buses that can route any signal to any pin. The buses
also enable signal multiplexing and performing logic operations.
This configurability frees the designs from the constraints of a
fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This enables you the
optimum choice of system resources for your application. Family
resources are shown in Table 3-1 on page 5.
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Figure 3-2. Analog System Block Diagram
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are as follows.
■
Filters (2 and 4 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
P 0 [6 ]
P 0 [5 ]
P 0 [4 ]
P 0 [3 ]
P 0 [2 ]
P 0 [1 ]
P 0 [0 ]
P 2 [3 ]
AGNDIn RefIn
Analog-to-digital converters (up to 2, with 6 to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
P 0 [7 ]
Analog
■
A ll IO
(E x c e p t P o r t 7 )
Mux Bus
3.3 The Analog System
P 2 [1 ]
P 2 [6 ]
P 2 [4 ]
P 2 [2 ]
P 2 [0 ]
A C I 0 [1 :0 ]
A C I 1 [1 :0 ]
A r r a y In p u t
C o n f ig u r a t io n
B lo c k
A rray
AC B00
A C B 01
Modulators
A SC 10
A SD 11
■
Correlators
ASD20
A SC 21
■
Peak Detectors
■
Many other topologies possible
A n a lo g R e f e r e n c e
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 3-2.
In t e r f a c e t o
D ig it a l S y s t e m
R e fH i
R e fL o
AGND
R e fe r e n c e
G e n e ra to rs
A G N D In
R e fIn
B andgap
M 8 C In t e r f a c e ( A d d r e s s B u s , D a t a B u s , E t c .)
3.3.1 The Analog Multiplexer System
The Analog Mux Bus can connect to every GPI/O pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. It is split into two
sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
Document Number: 38-12018 Rev. *U
■
Track pad, finger sensing.
■
Chip-wide mux that enables analog input from up to 48 I/O pins.
■
Crosspoint connection between any I/O pin combinations.
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4. Getting Started
3.4 Additional System Resources
System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow.
■
Full Speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (-10°C to +85°C).
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
■
Decimator provides a custom hardware filter for digital signal
processing applications including creation of Delta Sigma
ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, multi-master are supported.
■
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups. The device covered by this data
sheet is shown in the highlighted row of the table
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
Table 3-1. PSoC Device Characteristics
CY8C29x66
up to
64
4
16
12
4
4
12
2K
32K
CY8C27x43
up to
44
2
8
12
4
4
12
256
Bytes
16K
CY8C24x94
56
1
4
48
2
2
6
1K
16K
CY8C24x23A
up to
24
1
4
12
2
2
6
256
Bytes
4K
CY8C21x34
up to
28
1
4
28
0
2
4
512
Bytes
8K
CY8C21x23
16
1
4
8
0
2
4
256
Bytes
4K
CY8C20x34
up to
28
0
0
28
0
0
3
512
Bytes
8K
Document Number: 38-12018 Rev. *U
For in depth information, along with detailed programming information, see the Technical Reference Manual for this PSoC
device.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at http://www.cypress.com.
4.1 Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs and are available at
http://www.cypress.com.
4.2 Development Kits
PSoC Development Kits are available online from Cypress at
http://www.cypress.com and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
4.3 Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at http://www.cypress.com. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
4.4 CyPros Consultants
3.5 PSoC Device Characteristics
PSoC Part
Number
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to http://www.cypress.com and refer to
CYPros Consultants.
4.5 Solutions Library
Visit our growing library of solution focused designs at
http://www.cypress.com. Here you can find various application
designs that include firmware and hardware design files that
enable you to complete your designs quickly.
4.6 Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at http://www.cypress.com. If you cannot find
an answer to your question, call technical support at
1-800-541-4736.
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5. Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
5.1 PSoC Designer Software Subsystems
5.1.1 System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
5.1.2 Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE). Choose a base device to work with and then
select different onboard analog and digital components called
user modules that use the PSoC blocks. Examples of user
modules are ADCs, DACs, Amplifiers, and Filters. Configure the
user modules for your chosen application and connect them to
each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration enables changing configurations at run time.
5.1.4 Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
5.1.5 Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
5.1.6 Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
5.2 In-Circuit Emulator
5.1.3 Hybrid Designs
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 38-12018 Rev. *U
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6. Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
6.3 Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
6.1 Select Components
6.4 Generate, Verify, and Debug
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I2C-bus, for example), and the logic to control how they interact
with one another (called valuators).
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
6.2 Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 38-12018 Rev. *U
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
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7. Document Conventions
7.2 Units of Measure
7.1 Acronyms Used
A units of measure table is located in the Electrical Specifications
section. Table 10-1 on page 21 lists all the abbreviations used to
measure the PSoC devices.
The following table lists the acronyms that are used in this
document.
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
FSR
full scale range
GPI/O
general purpose I/O
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
I/O
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
PWM
pulse width modulator
SC
switched capacitor
SRAM
static random access memory
Document Number: 38-12018 Rev. *U
7.3 Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, ‘01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Page 8 of 50
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CY8C24094, CY8C24794
CY8C24894, CY8C24994
8. Pin Information
This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration.
The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin
(labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
8.1 56-Pin Part Pinout
Table 8-1. 56-Pin Part Pinout (QFN[3]) See LEGEND details and footnotes in Table 8-2 on page 10.
P5[4]
44
I/O
M
P2[6]
External Voltage Reference (VREF) input.
M
P5[6]
45
I/O
I, M
P0[0]
Analog column mux input.
33
I/O
M
P3[0]
46
I/O
I, M
P0[2]
Analog column mux input.
34
I/O
M
P3[2]
47
I/O
I, M
P0[4]
Analog column mux input VREF.
35
I/O
M
P3[4]
48
I/O
I, M
P0[6]
Analog column mux input.
36
I/O
M
P3[6]
49
Power
Vdd
Supply voltage.
37
I/O
M
P4[0]
50
Power
Vss
38
I/O
M
P4[2]
51
I/O
I, M
P0[7]
Analog column mux input,.
39
I/O
M
P4[4]
52
I/O
I/O, M
P0[5]
Analog column mux input and column output.
40
I/O
M
P4[6]
53
I/O
I/O, M
P0[3]
Analog column mux input and column output.
41
I/O
I, M
P2[0]
Direct switched capacitor block input.
54
I/O
I, M
P0[1]
Analog column mux input.
42
I/O
I, M
P2[2]
Direct switched capacitor block input.
55
I/O
M
P2[7]
43
I/O
M
P2[4]
External Analog Ground (AGND) input.
56
I/O
M
P2[5]
44
43
46
45
51
50
49
48
47
56
55
54
53
52
QFN
P7[0]
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2[2], A, I, M
P2[0], A, I, M
P4[6], M
P4[4], M
P4[2], M
P4[0], M
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
M, I2C SDA, P1[0]
M,P1[2]
EXTCLK, M,P1[4]
M, P1[6]
M,P1[3]
M, I2C SCL, P1[1]
Vss
D+
DVdd
P7[7]
21
22
23
24
(Top V ie w )
15
16
17
18
19
20
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
P2[4],M
M
I/O
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6],M
I/O
32
P0[7], A, I, M
Vss
31
P0[5], A, IO, M
CY8C24794 56-Pin PSoC Device[1]
P2[5],M
P2[7],M
P0[1], A, I, M
P0[3], A, IO, M
Type
Pin
Figure 8-1.
Description
No. Digital Analog Name
1
I/O
I, M
P2[3] Direct switched capacitor block input.
2
I/O
I, M
P2[1] Direct switched capacitor block input.
3
I/O
M
P4[7]
4
I/O
M
P4[5]
5
I/O
M
P4[3]
A, I, M , P2[3]
1
6
I/O
M
P4[1]
A, I, M , P2[1]
2
7
I/O
M
P3[7]
M , P4[7]
3
8
I/O
M
P3[5]
M , P4[5]
4
9
I/O
M
P3[3]
M , P4[3]
5
10
I/O
M
P3[1]
M , P4[1]
6
M , P3[7]
7
11
I/O
M
P5[7]
8
M , P3[5]
12
I/O
M
P5[5]
M , P3[3]
9
13
I/O
M
P5[3]
M , P3[1]
10
14
I/O
M
P5[1]
M , P5[7]
11
15
I/O
M
P1[7] I2C Serial Clock (SCL).
M , P5[5]
12
M , P5[3]
13
16
I/O
M
P1[5] I2C Serial Data (SDA).
M , P5[1]
14
17
I/O
M
P1[3]
18
I/O
M
P1[1] I2C Serial Clock (SCL), ISSP SCLK[2].
19
Power
Vss Ground connection.
20
USB
D+
21
USB
D22
Power
Vdd Supply voltage.
23
I/O
P7[7]
24
I/O
P7[0]
25
I/O
M
P1[0] I2C Serial Data (SDA), ISSP SDATA[2].
26
I/O
M
P1[2]
27
I/O
M
P1[4] Optional External Clock Input (EXTCLK).
28
I/O
M
P1[6]
29
I/O
M
P5[0]
Type
Pin
Name
No. Digital Analog
30
I/O
M
P5[2]
Description
Ground connection.
Note
1. This part cannot be programmed with Reset mode; use Power Cycle mode when programming.
Document Number: 38-12018 Rev. *U
Page 9 of 50
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.2 56-Pin Part Pinout (with XRES)
Table 8-2. 56-Pin Part Pinout (QFN[3])
I,
I,
I,
I,
A,
A,
A,
A,
M
M
I, M
IO, M
IO, M
I, M
48
47
46
45
44
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
QFN
(Top View)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2[2],
P2[0],
P4[6],
P4[4],
P4[2],
P4[0],
XRES
P3[4],
P3[2],
P3[0],
P5[6],
P5[4],
P5[2],
P5[0],
A, I, M
A, I, M
M
M
M
M
M
M
M
M
M
M
M
M, I2C SCL,
M, I2C SDA,
M,
M, I2C SCL,
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[0]
M, I2C SDA, P1[0]
M, P1[2]
EXTCLK, M, P1[4]
M, P1[6]
A, I, M,
A, I, M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
56
55
54
53
52
51
50
49
P2[5],
P2[7],
P0[1],
P0[3],
P0[5],
P0[7],
Vss
Vdd
P0[6],
P0[4],
P0[2],
P0[0],
P2[6],
P2[4],
M
M
A,
A,
A,
A,
M
M
M
M
Figure 8-2. CY8C24894 56-Pin PSoC Device
Type
Pin
Description
No. Digital Analog Name
1
I/O
I, M
P2[3] Direct switched capacitor block input.
2
I/O
I, M
P2[1] Direct switched capacitor block input.
3
I/O
M
P4[7]
4
I/O
M
P4[5]
5
I/O
M
P4[3]
6
I/O
M
P4[1]
7
I/O
M
P3[7]
8
I/O
M
P3[5]
9
I/O
M
P3[3]
10
I/O
M
P3[1]
11
I/O
M
P5[7]
12
I/O
M
P5[5]
13
I/O
M
P5[3]
14
I/O
M
P5[1]
15
I/O
M
P1[7] I2C Serial Clock (SCL).
16
I/O
M
P1[5] I2C Serial Data (SDA).
17
I/O
M
P1[3]
18
I/O
M
P1[1] I2C Serial Clock (SCL), ISSP SCLK[2].
19
Power
Vss Ground connection.
20
USB
D+
21
USB
D22
Power
Vdd Supply voltage.
23
I/O
P7[7]
24
I/O
P7[0]
25
I/O
M
P1[0] I2C Serial Data (SDA), ISSP SDATA[2].
26
I/O
M
P1[2]
27
I/O
M
P1[4] Optional External Clock Input (EXTCLK).
28
I/O
M
P1[6]
29
I/O
M
P5[0]
30
I/O
M
P5[2]
Type
Pin
No. Digital Analog Name
31
I/O
M
P5[4]
44
I/O
M
P2[6]
External Voltage Reference (VREF) input.
32
I/O
M
P5[6]
45
I/O
I, M
P0[0]
Analog column mux input.
33
I/O
M
P3[0]
46
I/O
I, M
P0[2]
Analog column mux input.
34
I/O
M
P3[2]
47
I/O
I, M
P0[4]
Analog column mux input VREF.
35
I/O
M
P3[4]
48
I/O
I, M
P0[6]
Analog column mux input.
49
Vdd
Supply voltage.
36
Input
37
I/O
M
XRES Active high external reset with internal
pull down.
P4[0]
38
I/O
M
P4[2]
51
I/O
I, M
P0[7]
Analog column mux input,.
39
I/O
M
P4[4]
52
I/O
I/O, M
P0[5]
Analog column mux input and column output.
40
I/O
M
P4[6]
53
I/O
I/O, M
P0[3]
Analog column mux input and column output.
41
I/O
I, M
P2[0]
Direct switched capacitor block input.
54
I/O
I, M
P0[1]
Analog column mux input.
42
I/O
I, M
P2[2]
Direct switched capacitor block input.
55
I/O
M
P2[7]
43
I/O
M
P2[4]
External Analog Ground (AGND) input.
56
I/O
M
P2[5]
50
Power
Description
Power
Vss
Ground connection.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Notes
2. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
3. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 38-12018 Rev. *U
Page 10 of 50
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.3 68-Pin Part Pinout
The following 68-pin QFN part table and drawing is for the CY8C24994 PSoC device.
Table 8-3. 68-Pin Part Pinout (QFN[3])
M
M
M
P4[0]
P4[2]
P4[4]
P2[6], M, Ext. VREF
P2[4], M, Ext. AGND
P2[2], M, AI
53
52
P0[2], M, AI
P0[0], M, AI
55
54
58
57
56
P0[7], M, AI
Vss
Vdd
P0[6], M, AI
P0[4], M, AI
P0[1], M, AI
P0[3], M, AIO
P0[5], M, AIO
63
62
61
60
59
64
P2[3], M, AI
P2[5], M
P2[7], M
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Vss
P0[7]
P0[5]
63
64
65
I/O
I/O
I/O
I/O,M
I,M
M
P0[3]
P0[1]
P2[7]
66
67
68
I/O
I/O
I/O
M
I,M
I,M
P2[5]
P2[3]
P2[1]
50
51
52
Optional External Clock Input (EXTCLK). 53
54
55
56
57
58
59
60
61
62
I2C Serial Data (SDA), ISSP SDATA[2].
No connection.
No connection.
Active high pin reset with internal pull
down.
66
65
Type
Digital Analog
I/O
M
I/O
I,M
I/O
I,M
I/O
M
I/O
M
I/O
I,M
I/O
I,M
I/O
I,M
I/O
I,M
Power
Power
I/O
I,M
I/O
I/O,M
Pin
No.
Name
31
32
33
34
38
37
36
35
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
EXTCLK, M, P1[4]
Supply voltage.
I2C SDA, M, P1[0]
M, P1[2]
I2C Serial Clock (SCL) ISSP SCLK[2].
Ground connection.
QFN
(Top View)
28
29
30
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
49
48
47
46
45
44
43
42
41
40
39
P7[3]
P7[2]
P7[1]
P7[0]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
51
50
24
25
26
27
M, P4[1]
NC
NC
Vss
M, P3[7]
M, P3[5]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P7[7]
P7[6]
P7[5]
P7[4]
M, P4[7]
M, P4[5]
M, P4[3]
20
21
22
23
I/O
I/O
I/O
P2[1], M, AI
47
48
49
68
67
Input
NC
NC
XRES
No connection.
No connection.
Ground connection.
18
19
44
45
46
Figure 8-3. CY8C24994 68-Pin PSoC Device
Description
M, P1[3]
P4[7]
P4[5]
P4[3]
P4[1]
NC
NC
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
Name
I2C SCL, M, P1[1]
Vss
D+
DVdd
Type
Pin
No. Digital Analog
1
I/O
M
2
I/O
M
3
I/O
M
4
I/O
M
5
6
7
Power
8
I/O
M
9
I/O
M
10 I/O
M
11
I/O
M
12 I/O
M
13 I/O
M
14 I/O
M
15 I/O
M
16 I/O
M
17 I/O
M
18 I/O
M
19 I/O
M
20 Power
21 USB
22 USB
23 Power
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31 I/O
32 I/O
M
33 I/O
M
34 I/O
M
35 I/O
M
36 I/O
M
37 I/O
M
38 I/O
M
39 I/O
M
40 I/O
M
41 I/O
M
42 I/O
M
43 I/O
M
Description
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
External Voltage Reference (VREF) input.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Ground connection.
Analog column mux input, integration input #1
Analog column mux input and column output, integration
input #2.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
Document Number: 38-12018 Rev. *U
Page 11 of 50
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.4 68-Pin Part Pinout (On-Chip Debug)
The following 68-pin QFN part table and drawing is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 8-4. 68-Pin Part Pinout (QFN[3])
Type
Pin
No. Digital Analog
50 I/O
M
I2C Serial Data (SDA), ISSP SDATA[2]. 51 I/O
I,M
52 I/O
I,M
Optional External Clock Input (EXTCLK). 53 I/O
M
54 I/O
M
55 I/O
I,M
56 I/O
I,M
57 I/O
I,M
58 I/O
I,M
59 Power
60 Power
61 I/O
I,M
62 I/O
I/O,M
I/O
I/O
I/O
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Vss
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
47 I/O
M
P4[0]
66 I/O
M
48 I/O
M
P4[2]
67 I/O
I,M
49 I/O
M
P4[4]
68 I/O
I,M
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.
P2[5]
P2[3]
P2[1]
Document Number: 38-12018 Rev. *U
63
64
65
Name
I/O,M
I,M
M
Input
P2[6], M, Ext. VREF
P2[4], M, Ext. AGND
P2[2], M, AI
I2C SDA, M, P1[0]
M, P1[2]
EXTCLK M, P1[4]
28
29
30
31
32
33
34
P7[3]
P7[2]
P7[1]
P7[0]
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
CCLK
HCLK
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
,
55
54
53
52
58
57
56
P0[7], M, AI
Vss
Vdd
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
64
63
62
61
60
59
P2[3], M, AI
P2[5], M
P2[7], M
P0[1], M, AI
P0[3], M, AIO
P0[5], M, AIO
QFN
(Top View)
P7[7]
P7[6]
P7[5]
P7[4]
Supply voltage.
OCD high speed clock output.
OCD CPU clock output.
Active high pin reset with internal pull
down.
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
23
24
25
26
27
I2C Serial Clock (SCL), ISSP SCLK[2].
Ground connection.
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
OCDE
OCDO
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
20
21
22
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
P2[1], M, AI
HCLK
CCLK
XRES
OCD even data I/O.
OCD odd data output.
Ground connection.
68
67
44
45
46
Figure 8-4. CY8C24094 68-Pin OCD PSoC Device
Description
18
19
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
Name
M, P1[3]
I2C SCL, M, P1[1]
Vss
D+
DVdd
Type
Pin
No. Digital Analog
1
I/O
M
2
I/O
M
3
I/O
M
4
I/O
M
5
6
7
Power
8
I/O
M
9
I/O
M
10 I/O
M
11
I/O
M
12 I/O
M
13 I/O
M
14 I/O
M
15 I/O
M
16 I/O
M
17 I/O
M
18 I/O
M
19 I/O
M
20 Power
21 USB
22 USB
23 Power
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31 I/O
32 I/O
M
33 I/O
M
34 I/O
M
35 I/O
M
36 I/O
M
37 I/O
M
38 I/O
M
39 I/O
M
40 I/O
M
41 I/O
M
42 I/O
M
43 I/O
M
Description
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
External Voltage Reference (VREF) input.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Ground connection.
Analog column mux input, integration input #1
Analog column mux input and column output,
integration input #2.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Page 12 of 50
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.5 100-Ball VFBGA Part Pinout
The 100-ball VFBGA part is for the CY8C24994 PSoC device.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
Power
Power
Vss
Vss
NC
NC
NC
Power
Vdd
NC
NC
Power
Vss
Power
Vss
Power
Vss
Power
Vss
I/O I,M
P2[1]
I/O I,M
P0[1]
I/O I,M
P0[7]
Power
Vdd
I/O I,M
P0[2]
I/O I,M
P2[2]
Power
Vss
Power
Vss
NC
I/O M
P4[1]
I/O M
P4[7]
I/O M
P2[7]
I/O I/O,M P0[5]
I/O I,M
P0[6]
I/O I,M
P0[0]
I/O I,M
P2[0]
I/O M
P4[2]
NC
NC
I/O M
P3[7]
I/O M
P4[5]
I/O M
P2[5]
I/O I/O,M P0[3]
I/O I,M
P0[4]
I/O M
P2[6]
I/O M
P4[6]
I/O M
P4[0]
NC
NC
NC
I/O M
P4[3]
I/O I,M
P2[3]
Power
Vss
Power
Vss
I/O M
P2[4]
I/O M
P4[4]
I/O M
P3[6]
NC
Description
Ground connection.
Ground connection.
No connection.
No connection.
No connection.
Supply voltage.
No connection.
No connection.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
Direct switched capacitor block input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Analog column mux input.
Direct switched capacitor block input.
Ground connection.
Ground connection.
No connection.
Pin
No.
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
Analog column mux input and column output. H5
Analog column mux input.
H6
Analog column mux input.
H7
Direct switched capacitor block input.
H8
H9
No connection.
H10
No connection.
J1
J2
J3
J4
Analog column mux input and column output. J5
Analog column mux input.
J6
External Voltage Reference (VREF) input.
J7
J8
J9
No connection.
J10
No connection.
K1
No connection.
K2
K3
Direct switched capacitor block input.
K4
Ground connection.
K5
Ground connection.
K6
External Analog Ground (AGND) input.
K7
K8
K9
No connection.
K10
Analog
Name
Digital
Analog
Pin
No.
Digital
Table 8-5. 100-Ball Part Pinout (VFBGA)
I/O M
I/O M
I/O M
Power
Power
I/O M
I/O M
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
M
I/O M
I/O M
I/O M
I/O M
I/O M
I/O M
I/O M
I/O M
I/O
Power
Power
USB
USB
Power
I/O
I/O
I/O M
Power
Power
Power
Power
Power
I/O
I/O
I/O
Power
Power
Name
NC
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
NC
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
DVdd
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
Description
No connection.
Ground connection.
Ground connection.
Active high pin reset with internal pull down.
No connection.
I2C Serial Clock (SCL).
I2C Serial Clock (SCL), ISSP SCLK[2].
I2C Serial Data (SDA), ISSP SDATA[2].
No connection.
I2C Serial Data (SDA).
Optional External Clock Input (EXTCLK).
Ground connection.
Ground connection.
Supply voltage.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
No connection.
No connection.
Supply voltage.
Ground connection.
Ground connection.
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection.
Document Number: 38-12018 Rev. *U
Page 13 of 50
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
Figure 8-5. CY8C24094 OCD (Not for Production)
1
2
3
4
5
6
7
8
9
10
A
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
B
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
C
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
D
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
NC
E
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
NC
F
NC
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
G
NC
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
H
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
J
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
K
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
8.6 100-Ball VFBGA Part Pinout (On-Chip Debug)
The following 100-pin VFBGA part table and drawing is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
Power
Power
C6
C7
I/O
I/O
Power
Power
Power
Power
Power
I/O I,M
I/O I,M
I/O I,M
Power
I/O I,M
I/O I,M
Power
Power
I/O
I/O
I/O
I/O
M
M
M
I/O,
M
I,M
I,M
Description
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
NC
P4[1]
P4[7]
P2[7]
P0[5]
Ground connection.
Ground connection.
No connection.
No connection.
No connection.
Supply voltage.
No connection.
No connection.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
Direct switched capacitor block input.
Analog column mux input.
Analog column mux input.
Supply voltage.
Analog column mux input.
Direct switched capacitor block input.
Ground connection.
Ground connection.
No connection.
P0[6]
P0[0]
Analog column mux input.
Analog column mux input.
Pin
No.
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
Analog column mux input and column output. H5
Document Number: 38-12018 Rev. *U
H6
H7
Analog
Name
Digital
Digital
Pin
No.
Analog
Table 8-6. 100-Ball Part Pinout (VFBGA)
Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
M
I/O
I/O
I/O
I/O
M
M
M
M
OCDE
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
OCDO
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
I/O
I/O
M
M
P1[2]
P1[4]
I/O M
I/O M
I/O M
Power
Power
I/O M
I/O M
I/O
Description
OCD even data I/O.
Ground connection.
Ground connection.
Active high pin reset with internal pull down.
OCD odd data output.
I2C Serial Clock (SCL).
I2C Serial Clock (SCL), ISSP SCLK[2].
I2C Serial Data (SDA), ISSP SDATA[2].
No connection.
I2C Serial Data (SDA).
Optional External Clock Input (EXTCLK).
Page 14 of 50
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
I/O
I/O
I,M
M
I/O
I/O
I/O
I/O
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
I/O
I/O
I/O
I/O
M
M
M
I/O,
M
I,M
M
M
M
I/O M
I/O I,M
Power
Power
I/O M
I/O M
I/O M
Pin
No.
Description
Direct switched capacitor block input.
Analog
Analog
C8
C9
C10
D1
D2
D3
D4
D5
Name
Digital
Pin
No.
Digital
Table 8-6. 100-Ball Part Pinout (VFBGA) (continued)
Name
P2[0]
P4[2]
NC
NC
P3[7]
P4[5]
P2[5]
P0[3]
H8
H9
No connection.
H10
No connection.
J1
J2
J3
J4
Analog column mux input and column output. J5
I/O M
I/O M
I/O
Power
Power
USB
USB
Power
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
DVdd
P0[4]
P2[6]
P4[6]
P4[0]
CCLK
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
HCLK
Analog column mux input.
External Voltage Reference (VREF) input.
I/O
I/O
I/O M
Power
Power
Power
Power
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
OCD CPU clock output.
No connection.
No connection.
Direct switched capacitor block input.
Ground connection.
Ground connection.
External Analog Ground (AGND) input.
OCD high speed clock output.
Power
I/O
I/O
I/O
Power
Power
Description
Ground connection.
Ground connection.
Supply voltage.
Ground connection.
Ground connection.
Ground connection.
Ground connection.
No connection.
No connection.
Supply voltage.
Ground connection.
Ground connection.
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.
Figure 8-6. CY8C24094 OCD (Not for Production)
1
2
3
4
5
6
7
8
9
10
A
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
B
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
C
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
D
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
CClk
E
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
HClk
F
ocde
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
G
ocdo
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
H
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
J
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
K
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
Document Number: 38-12018 Rev. *U
Page 15 of 50
[+] Feedback
CY8C24094, CY8C24794
CY8C24894, CY8C24994
8.7 100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
NC
NC
I/O I, M P0[1]
I/O M
P2[7]
I/O M
P2[5]
I/O I, M P2[3]
I/O I, M P2[1]
I/O M
P4[7]
I/O M
P4[5]
I/O M
P4[3]
I/O M
P4[1]
OCDE
OCDO
NC
Power
Vss
I/O M
P3[7]
I/O M
P3[5]
I/O M
P3[3]
I/O M
P3[1]
I/O M
P5[7]
I/O M
P5[5]
I/O M
P5[3]
I/O M
P5[1]
I/O M
P1[7]
NC
NC
NC
I/O
P1[5]
I/O
P1[3]
I/O
P1[1]
Power
USB
USB
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
NC
NC
NC
NC
48
I/O
P1[0]
49
I/O
P1[2]
50
I/O
P1[4]
Description
No connection.
No connection.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
OCD even data I/O.
OCD odd data output.
No connection.
Ground connection.
I2C Serial Clock (SCL).
No connection.
No connection.
No connection.
I2C Serial Data (SDA)
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP SCLK[2].
No connection.
Ground connection.
Supply voltage.
No connection.
No connection.
No connection.
No connection.
Crystal (XTALout), I2C Serial Data (SDA),
ISSP SDATA[2].
Pin
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
I/O I, M
Power
M
M
M
M
M
M
M
M
M
Input
I/O M
I/O M
Power
I/O M
I/O M
I/O I, M
I/O I, M
I/O
I/O
I/O
I
I/O
I, M
I/O
I, M
Power
I/O
I, M
I/O
I/O,
M
98
99
Optional External Clock Input (EXTCLK).
Analog
Name
Digital
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Analog
Pin
No.
Digital
Table 8-7. 100-Pin Part Pinout (TQFP)
100
I/O
I/O,
M
Name
Description
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
HCLK
CCLK
XRES
P4[0]
P4[2]
Vss
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
NC
P2[6]
NC
P0[0]
NC
NC
P0[2]
NC
P0[4]
NC
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
No connection.
External Voltage Reference (VREF) input.
No connection.
Analog column mux input.
No connection.
No connection.
Analog column mux input and column output.
No connection.
Analog column mux input and column output.
No connection.
P0[6]
Vdd
NC
Vss
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
P0[7]
NC
P0[5]
Analog column mux input.
Supply voltage.
No connection.
Ground connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
No connection.
Analog column mux input.
No connection.
Analog column mux input and column output.
NC
No connection.
P0[3]
Analog column mux input and column output.
NC
No connection.
OCD high speed clock output.
OCD CPU clock output.
Active high pin reset with internal pull down.
Ground connection.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.
Document Number: 38-12018 Rev. *U
Page 16 of 50
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Document Number: 38-12018 Rev. *U
NC
P0[2], M, AI
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
P0[0], M , AI
NC
P2[6], M , External VREF
NC
P2[4], M , External AGND
P2[2], M , AI
P2[0], M , AI
P4[6], M
P4[4], M
Vss
P4[2], M
P4[0], M
XRES
CCLK
HCLK
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
M, P1[2]
EXTCLK, M, P1[4]
46
47
48
49
50
P7[1]
P7[0]
NC
NC
NC
NC
I2C SDA, M, P1[0]
P7[3]
P7[2]
36
37
38
39
40
41
42
43
44
45
P7[7]
P7[6]
P7[5]
P7[4]
31
32
33
34
35
77
76
80
79
78
NC
Vdd
P0[6], M, AI
NC
P0[4], M, AI
NC
NC
Vss
87
86
85
84
83
82
81
90
89
88
NC
NC
NC
NC
NC
NC
NC
NC
P0[7], M, AI
NC
95
94
93
92
91
P0[3], M, AI
NC
P0[5], M, AI
98
97
96
28
29
30
26
27
TQFP
NC
I2C SDA, M, P1[5]
M, P1[3]
I2C SCL, M, P1[1]
NC
Vss
D+
DVdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
NC
AI, M , P0[1]
M , P2[7]
M , P2[5]
AI, M , P2[3]
AI, M , P2[1]
M , P4[7]
M , P4[5]
M , P4[3]
M , P4[1]
OCDE
OCDO
NC
Vss
M , P3[7]
M , P3[5]
M , P3[3]
M , P3[1]
M , P5[7]
M , P5[5]
M , P5[3]
M , P5[1]
I2C SCL, P1[7]
NC
100
99
NC
Figure 8-7. CY8C24094 OCD (Not for Production)
Page 17 of 50
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CY8C24894, CY8C24994
9. Register Reference
This section lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the
PSoC Technical Reference Manual.
9.1 Register Conventions
9.2 Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 38-12018 Rev. *U
Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Page 18 of 50
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CY8C24894, CY8C24994
9.3 Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
Addr (0,Hex) Access
Name
00
RW
PMA0_DR
01
RW
PMA1_DR
02
RW
PMA2_DR
03
RW
PMA3_DR
04
RW
PMA4_DR
05
RW
PMA5_DR
06
RW
PMA6_DR
07
RW
PMA7_DR
08
RW
USB_SOF0
09
RW
USB_SOF1
0A
RW
USB_CR0
0B
RW
USBI/O_CR0
0C
RW
USBI/O_CR1
0D
RW
0E
RW
EP1_CNT1
0F
RW
EP1_CNT
10
RW
EP2_CNT1
11
RW
EP2_CNT
12
RW
EP3_CNT1
13
RW
EP3_CNT
14
RW
EP4_CNT1
15
RW
EP4_CNT
16
RW
EP0_CR
17
RW
EP0_CNT
18
EP0_DR0
19
EP0_DR1
1A
EP0_DR2
1B
EP0_DR3
PRT7DR
1C
RW
EP0_DR4
PRT7IE
1D
RW
EP0_DR5
PRT7GS
1E
RW
EP0_DR6
PRT7DM2
1F
RW
EP0_DR7
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
AMUXCFG
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
DCB02DR1
29
W
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
30
ACB00CR3
31
ACB00CR0
32
ACB00CR1
33
ACB00CR2
34
ACB01CR3
35
ACB01CR0
36
ACB01CR1
37
ACB01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are Reserved and should not be accessed.
Document Number: 38-12018 Rev. *U
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
R
R
RW
#
RW
#
RW
#
RW
#
RW
#
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
MUL1_X
A8
MUL1_Y
A9
MUL1_DH
AA
MUL1_DL
AB
ACC1_DR1
AC
ACC1_DR0
AD
ACC1_DR3
AE
ACC1_DR2
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
DAC_D
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
RW
#
#
Page 19 of 50
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9.4 Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
Addr (1,Hex) Access
Name
00
RW
PMA0_WA
01
RW
PMA1_WA
02
RW
PMA2_WA
03
RW
PMA3_WA
04
RW
PMA4_WA
05
RW
PMA5_WA
06
RW
PMA6_WA
07
RW
PMA7_WA
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
RW
PMA0_RA
11
RW
PMA1_RA
12
RW
PMA2_RA
13
RW
PMA3_RA
14
RW
PMA4_RA
15
RW
PMA5_RA
16
RW
PMA6_RA
17
RW
PMA7_RA
18
19
1A
1B
PRT7DM0
1C
RW
PRT7DM1
1D
RW
PRT7IC0
1E
RW
PRT7IC1
1F
RW
DBB00FN
20
RW
CLK_CR0
DBB00IN
21
RW
CLK_CR1
DBB00OU
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
CMP_GO_EN
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
DCB02IN
29
RW
DCB02OU
2A
RW
2B
DCB03FN
2C
RW
TMP_DR0
DCB03IN
2D
RW
TMP_DR1
DCB03OU
2E
RW
TMP_DR2
2F
TMP_DR3
30
ACB00CR3
31
ACB00CR0
32
ACB00CR1
33
ACB00CR2
34
ACB01CR3
35
ACB01CR0
36
ACB01CR1
37
ACB01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are Reserved and should not be accessed.
Document Number: 38-12018 Rev. *U
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
USBI/O_CR2
USB_CR1
Addr (1,Hex) Access
C0
RW
C1
#
EP1_CR0
EP2_CR0
EP3_CR0
EP4_CR0
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
IMO_TR
ILO_TR
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
RW
RW
RW
RW
RW
RW
RW
CPU_F
DAC_CR
CPU_SCR1
CPU_SCR0
#
#
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RW
RW
RL
RW
#
#
Page 20 of 50
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CY8C24894, CY8C24994
10. Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by visiting http://www.cypress.com.
Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications for devices running at greater than
12 MHz are valid for -40°C ≤ TA ≤ 70°C and TJ ≤ 82°C.
Figure 10-1. Voltage versus CPU Frequency
5.25
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
3.00
93 kHz
12 MHz
24 MHz
CPU Frequency
The following table lists the units of measure that are used in this chapter.
Table 10-1. Units of Measure
Symbol
°C
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 38-12018 Rev. *U
Symbol
μW
mA
ms
mV
nA
ns
nV
Ω
pA
pF
pp
ppm
ps
sps
σ
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 21 of 50
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10.1 Absolute Maximum Ratings
Table 10-2. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
TBAKETEMP Bake Temperature
Min
-55
Typ
25
Max
+100
Units
°C
–
125
°C
–
See
package
label
72
TBAKETIME
Bake Time
TA
Vdd
VI/O
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
See
package
label
-40
-0.5
Vss - 0.5
VI/O2
DC Voltage Applied to Tri-state
Vss - 0.5
–
IMI/O
IMAI/O
Maximum Current into any Port Pin
Maximum Current into any Port Pin
Configured as Analog Driver
Electro Static Discharge Voltage
Latch-up Current
-25
-50
ESD
LU
–
–
–
Notes
Higher storage temperatures
reduces data retention time.
Recommended storage
temperature is +25oC ± 25oC.
Extended duration storage
temperatures above 65oC
degrades reliability.
Hours
–
–
+85
+6.0
Vdd +
0.5
Vdd +
0.5
+50
+50
mA
mA
2000
–
–
–
–
200
V
mA
Min
-40
-10
-40
Typ
–
–
–
Max
+85
+85
+100
Units
°C
°C
°C
°C
V
V
V
Human Body Model ESD.
10.2 Operating Temperature
Table 10-3. Operating Temperature
Symbol
TA
TAUSB
TJ
Description
Ambient Temperature
Ambient Temperature using USB
Junction Temperature
Document Number: 38-12018 Rev. *U
Notes
The temperature rise from
ambient to junction is package
specific. See Thermal
Impedance on page 43. The
user must limit the power
consumption to comply with this
requirement.
Page 22 of 50
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10.3 DC Electrical Characteristics
10.3.1 DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-4. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
Min
3.0
Typ
–
Max
5.25
Units
V
IDD5
Supply Current, IMO = 24 MHz (5V)
–
14
27
mA
IDD3
Supply Current, IMO = 24 MHz (3.3V)
–
8
14
mA
ISB
Sleep (Mode) Current with POR, LVD,
Sleep Timer, and WDT.[4]
–
3
6.5
μA
ISBH
Sleep (Mode) Current with POR, LVD,
Sleep Timer, and WDT at high temperature.[4]
–
4
25
μA
Notes
See DC POR and LVD specifications,
Table 10-14 on page 29.
Conditions are Vdd = 5.0V, TA = 25 °C,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off.
Conditions are Vdd = 3.3V, TA = 25 °C,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.367 kHz,
analog power = off.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, -40 °C ≤
TA ≤ 55 °C, analog power = off.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V,
55 °C < TA ≤ 85 °C, analog power = off.
10.3.2 DC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-5. DC GPI/O Specifications
Symbol
Description
RPU
Pull Up Resistor
RPD
Pull Down Resistor
VOH
High Output Level
Min
4
4
Vdd - 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
kΩ
kΩ
V
VOL
Low Output Level
–
–
0.75
V
IOH
High Level Source Current
10
–
–
mA
IOL
Low Level Sink Current
25
–
–
mA
VIL
VIH
VH
IIL
CIN
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
COUT
Capacitive Load on Pins as Output
–
3.5
10
pF
Document Number: 38-12018 Rev. *U
Notes
IOH = 10 mA, Vdd = 4.75 to 5.25V
(8 total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 80
mA maximum combined IOH budget.
IOL = 25 mA, Vdd = 4.75 to 5.25V
(8 total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])). 200
mA maximum combined IOL budget.
VOH = Vdd-1.0V, see the limitations of
the total current in the note for VOH
VOL = 0.75V, see the limitations of the
total current in the note for VOL
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
Gross tested to 1 μA.
Package and pin dependent.
Temp = 25oC.
Package and pin dependent.
Temp = 25oC.
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10.3.3 DC Full Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-6. DC Full Speed (12 Mbps) USB Specifications
Symbol
Description
USB Interface
Differential Input Sensitivity
VDI
Differential Input Common Mode Range
VCM
Single Ended Receiver Threshold
VSE
CIN
Transceiver Capacitance
High-Z State Data Line Leakage
II/O
REXT
External USB Series Resistor
VUOH
Static Output High, Driven
Min
Typ
Max
Units
0.2
0.8
0.8
–
-10
23
2.8
–
–
–
–
–
–
–
–
2.5
2.0
20
10
25
3.6
V
V
V
pF
μA
W
V
VUOHI
Static Output High, Idle
2.7
–
3.6
V
VUOL
Static Output Low
–
–
0.3
V
ZO
VCRS
USB Driver Output Impedance
D+/D- Crossover Voltage
28
1.3
–
–
44
2.0
W
V
Notes
| (D+) - (D-) |
0V < VIN < 3.3V.
In series with each USB pin.
15 kΩ ± 5% to Ground. Internal
pull up enabled.
15 kΩ ± 5% to Ground. Internal
pull up enabled.
15 kΩ ± 5% to Ground. Internal
pull up enabled.
Including REXT Resistor.
10.3.4 DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 10-7. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
TCVOSOA Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
IEBOA
Input Capacitance (Port 0 Analog Pins)
CINOA
VCMOA
Common Mode Voltage Range
Common Mode Voltage Range (high power or high
opamp bias)
Min
Typ
Max
Units
–
–
–
–
–
–
1.6
1.3
1.2
7.0
20
4.5
10
8
7.5
35.0
–
9.5
mV
mV
mV
μV/°C
pA
pF
0.0
0.5
–
–
Vdd
Vdd - 0.5
V
Notes
Gross tested to 1 μA.
Package and pin
dependent. Temp =
25oC.
The common-mode
input voltage range is
measured through an
analog output buffer.
The specification
includes the limitations
imposed by the characteristics of the analog
output buffer.
Note
4. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar
functions enabled.
Document Number: 38-12018 Rev. *U
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Table 10-7. 5V DC Operational Amplifier Specifications (continued)
Symbol
GOLOA
Description
Open Loop Gain
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
VOHIGHO High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
A
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
ISOA
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio
Min
Typ
–
Max
–
Units
dB
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
–
65
400
500
800
1200
2400
4600
80
800
900
1000
1600
3200
6400
–
μA
μA
μA
μA
μA
μA
dB
60
60
80
Notes
Vss ≤ VIN ≤ (Vdd - 2.25)
or (Vdd - 1.25V) ≤ VIN ≤
Vdd.
10.3.5 DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design
guidance only.
Table 10-8. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference voltage
range
LPC supply current
LPC voltage offset
Document Number: 38-12018 Rev. *U
Min
0.2
Typ
–
Max
Vdd - 1
Units
V
–
–
10
2.5
40
30
μA
mV
Notes
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10.3.6 DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-9. 5V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Min
Input Offset Voltage (Absolute Value)
–
Average Input Offset Voltage Drift
–
Common-Mode Input Voltage Range
0.5
Output Resistance
Power = Low
–
Power = High
–
High Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
0.5 x Vdd + 1.1
Power = High
0.5 x Vdd + 1.1
Low Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
–
Power = High
–
Supply Current Including Bias Cell (No Load)
–
Power = Low
–
Power = High
Supply Voltage Rejection Ratio
53
Typ
3
+6
–
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
0.6
0.6
–
–
W
W
–
–
–
–
V
V
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Typ
3
+6
-
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
1
1
–
–
W
W
–
–
–
–
V
V
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
0.8
2.0
64
2.0
4.3
–
mA
mA
dB
Notes
(0.5 x Vdd - 1.3) ≤ VOUT
≤ (Vdd - 2.3).
Table 10-10. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Min
Input Offset Voltage (Absolute Value)
–
Average Input Offset Voltage Drift
–
Common-Mode Input Voltage Range
0.5
Output Resistance
Power = Low
–
Power = High
–
High Output Voltage Swing (Load = 1K ohms
to Vdd/2)
0.5 x Vdd + 1.0
Power = Low
0.5 x Vdd + 1.0
Power = High
Low Output Voltage Swing (Load = 1K ohms
to Vdd/2)
–
Power = Low
–
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
–
Power = High
Supply Voltage Rejection Ratio
34
Document Number: 38-12018 Rev. *U
Notes
(0.5 x Vdd - 1.0) ≤ VOUT
≤ (0.5 x Vdd + 0.9).
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10.3.7 DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 10-11. 5V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
Min
Typ
Max
Bandgap Voltage Reference
1.28
1.30
1.32
AGND = Vdd/2[5, 6]
Vdd/2 - 0.04
Vdd/2 - 0.01
Vdd/2 + 0.007
AGND = 2 x BandGap[5, 6]
2 x BG - 0.048
2 x BG - 0.030
2 x BG + 0.024
[5, 6]
AGND = P2[4] (P2[4] = Vdd/2)
P2[4] - 0.011
P2[4]
P2[4] + 0.011
AGND = BandGap[5, 6]
BG - 0.009
BG + 0.008
BG + 0.016
AGND = 1.6 x BandGap[5, 6]
1.6 x BG - 0.022
1.6 x BG - 0.010
1.6 x BG + 0.018
AGND Block to Block Variation (AGND = Vdd/2)[5, 6]
-0.034
0.000
0.034
RefHi = Vdd/2 + BandGap
Vdd/2 + BG - 0.10
Vdd/2 + BG
Vdd/2 + BG + 0.10
RefHi = 3 x BandGap
3 x BG - 0.06
3 x BG
3 x BG + 0.06
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
2 x BG + P2[6] 2 x BG + P2[6] 2 x BG + P2[6] +
0.113
0.018
0.077
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6]+
0.133
0.016
0.100
RefHi = 3.2 x BandGap
3.2 x BG - 0.112
3.2 x BG
3.2 x BG + 0.076
RefLo = Vdd/2 – BandGap
Vdd/2 - BG - 0.04 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04
RefLo = BandGap
BG - 0.06
BG
BG + 0.06
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2 x BG - P2[6] 2 x BG - P2[6] +
2 x BG - P2[6] +
0.084
0.025
0.134
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
P2[4] - P2[6] P2[4] - P2[6] +
P2[4] - P2[6] +
0.057
0.026
0.110
Document Number: 38-12018 Rev. *U
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
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Table 10-12. 3.3V DC Analog Reference Specifications
Symbol
BG
–
–
–
–
–
–
–
–
–
–
–
Description
Bandgap Voltage Reference
AGND = Vdd/2[5, 6]
AGND = 2 x BandGap[5, 6]
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap[5, 6]
AGND = 1.6 x BandGap[5, 6]
AGND Column to Column Variation (AGND =
Vdd/2)[5, 6]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Min
1.28
Vdd/2 - 0.03
–
–
–
–
–
–
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048
P2[4] - 0.008
BG - 0.009
1.6 x BG - 0.027
-0.034
P2[4] + P2[6] 0.075
Typ
Max
1.30
1.32
Vdd/2 - 0.01
Vdd/2 + 0.005
Not Allowed
P2[4] + 0.001
P2[4] + 0.009
BG + 0.005
BG + 0.015
1.6 x BG - 0.010
1.6 x BG + 0.018
0.000
0.034
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[6] 0.009
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4]- P2[6] +
0.022
Units
V
V
V
V
V
V
P2[4] + P2[6] +
0.057
V
P2[4] - P2[6] +
0.092
V
10.3.8 DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-13. DC Analog PSoC Block Specifications
Symbol
Description
RCT
Resistor Unit Value (Continuous Time)
CSC
Capacitor Unit Value (Switched Capacitor)
Min
–
–
Typ
12.2
80
Max
–
–
Units
kΩ
fF
Notes
Note
5. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
6. Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the
AGND.
Document Number: 38-12018 Rev. *U
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10.3.9 DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are
for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Technical Reference Manual
for more information on the VLT_CR register.
Table 10-14. DC POR and LVD Specifications
Symbol
Description
VPPOR0R
VPPOR1R
VPPOR2R
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPH0
VPH1
VPH2
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
–
2.91
4.39
4.55
–
V
V
V
–
2.82
4.39
4.55
–
V
V
V
–
–
–
92
0
0
–
–
–
mV
mV
mV
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[7]
3.08
3.20
4.08
4.57
4.74[8]
4.82
4.91
V
V
V
V
V
V
V
V
V
Notes
Notes
7. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
8. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 38-12018 Rev. *U
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10.3.10 DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-15. DC Programming Specifications
Symbol
IDDP
VILP
Description
Supply Current During Programming or Verify
Input Low Voltage During Programming or
Verify
VIHP
Input High Voltage During Programming or
Verify
IILP
Input Current when Applying Vilp to P1[0] or
P1[1] During Programming or Verify
IIHP
Input Current when Applying Vihp to P1[0] or
P1[1] During Programming or Verify
VOLV
Output Low Voltage During Programming or
Verify
VOHV
Output High Voltage During Programming or
Verify
FlashENPB Flash Endurance (per block)[9]
FlashENT
FlashDR
Flash Endurance (total)[10]
Flash Data Retention
Min
–
–
Typ
15
–
Max
30
0.8
Units
mA
V
2.1
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
Vss + 0.75
V
Vdd - 1.0
–
Vdd
V
50,000
–
–
–
1,800,000
10
–
–
–
–
–
Years
Notes
Driving internal pull down
resistor.
Driving internal pull down
resistor.
Erase/write cycles per
block.
Erase/write cycles.
Note
9. The 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V to 5.25V.
10. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 38-12018 Rev. *U
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10.4 AC Electrical Characteristics
10.4.1 AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-16. AC Chip-Level Specifications
Symbol
FIMO245V
Min
23.04
Typ
24
Max
24.96[11,12]
Units
MHz
22.08
24
25.92[12,13]
MHz
23.94
24
24.06[12]
MHz
23.94
24
24.06[12]
MHz
-0°C ≤ TA ≤ 70°C
3.15 ≤ Vdd ≤ 3.45
FIMO6
Description
Internal Main Oscillator Frequency for 24 MHz
(5V)
Internal Main Oscillator Frequency for 24 MHz
(3.3V)
Internal Main Oscillator Frequency with USB
(5V)
Frequency locking enabled and USB traffic
present.
Internal Main Oscillator Frequency with USB
(3.3V)
Frequency locking enabled and USB traffic
present.
Internal Main Oscillator Frequency for 6 MHz
5.5
6
6.5[11,12,13]
MHz
Trimmed for 5V or 3.3V
operation using factory trim
values. See the figure on
page 19. SLIMO Mode = 1.
FCPU1
FCPU2
FBLK5
CPU Frequency (5V Nominal)
CPU Frequency (3.3V Nominal)
Digital PSoC Block Frequency (5V Nominal)
0.090
0.086
0
24
12
48
24.96[11,12]
12.96[12,13]
49.92[11,12,14]
MHz
MHz
MHz
FBLK3
F32K1
F32K_U
Digital PSoC Block Frequency (3.3V Nominal)
Internal Low Speed Oscillator Frequency
Internal Low Speed Oscillator (ILO) Untrimmed
Frequency
0
15
5
24
32
–
25.92[12,14]
64
–
MHz
kHz
kHz
Jitter32k
TXRST
DC24M
DCILO
Step24M
Fout48M
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
Internal Low Speed Oscillator Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
–
10
40
20
–
46.08
100
–
50
50
50
48.0
–
60
80
–
49.92[11,13]
ns
µs
%
%
kHz
MHz
24 MHz Period Jitter (IMO) Peak-to-Peak
Maximum frequency of signal on row input or
row output.
SRPOWER_UP Power Supply Slew Rate
–
–
300
–
12.96
ps
MHz
–
–
250
V/ms
TPOWERUP
–
16
100
ms
FIMO243V
FIMOUSB5V
FIMOUSB3V
Jitter24M1
FMAX
Time from end of POR to CPU executing code
Document Number: 38-12018 Rev. *U
Notes
Trimmed for 5V operation
using factory trim values.
Trimmed for 3.3V operation
using factory trim values.
-10°C ≤ TA ≤ 85°Cn
4.35 ≤ Vdd ≤ 5.15
Refer to the AC Digital Block
Specifications.
After a reset and before the
m8c starts to run, the ILO is
not trimmed. See the System
Resets section of the PSoC
Technical Reference Manual
for details on timing this
Trimmed. Utilizing factory
trim values.
Vdd slew rate during power
up.
Power up from 0V. See the
System Resets section of the
PSoC Technical Reference
Manual.
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Figure 10-2. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
10.4.2 AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-17. AC GPI/O Specifications
Symbol
FGPI/O
TRiseF
TFallF
TRiseS
TFallS
Description
GPI/O Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 10-3. GPI/O Timing Diagram
90%
G PIO
Pin
O utput
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
10.4.3 AC Full Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -10°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-18. AC Full Speed (12 Mbps) USB Specifications
Symbol
TRFS
TFSS
TRFMFS
TDRATEFS
Description
Transition Rise Time
Transition Fall Time
Rise/Fall Time Matching: (TR/TF)
Full Speed Data Rate
Min
4
4
90
12 0.25%
Typ
–
–
–
12
Max
20
20
111
12 +
0.25%
Units
ns
ns
%
Mbps
Notes
For 50 pF load.
For 50 pF load.
For 50 pF load.
Notes
11. 4.75V < Vdd < 5.25V.
12. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
13. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
14. See the individual user module data sheets for information on maximum frequencies for user modules
Document Number: 38-12018 Rev. *U
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10.4.4 AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 10-19. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
Table 10-20. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%)(10 pF load, Unity
Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Document Number: 38-12018 Rev. *U
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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 10-4. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 10-5. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 38-12018 Rev. *U
0.01
0.1
Freq (kHz)
1
10
100
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10.4.5 AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design
guidance only.
Table 10-21. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
10.4.6 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-22. AC Digital Block Specifications
Function
Min
Typ
Max
Units
50[15]
–
–
ns
Maximum Frequency, No Capture
–
–
49.92
MHz
Maximum Frequency, With Capture
–
–
25.92
MHz
50[15]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.92
MHz
Maximum Frequency, Enable Input
–
–
25.92
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[15]
–
–
ns
Disable Mode
50[15]
–
–
ns
Maximum Frequency
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
(PRS
Mode)
–
–
49.92
MHz
4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency
(CRC
Mode)
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
Timer
Counter
Dead
Band
Description
Capture Pulse Width
Enable Pulse Width
Notes
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Width of SS_ Negated Between Transmissions
–
–
4.1
MHz
50[15]
–
–
ns
Maximum data rate at 4.1 MHz due
to 2 x over clocking.
Transmitter
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Receiver
Maximum Input Clock Frequency
–
–
24.6
MHz
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Note
15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12018 Rev. *U
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10.4.7 AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-23. AC External Clock Specifications
Symbol
Description
FOSCEXT Frequency for USB Applications
Min
Typ
Max
Units
23.94
24
24.06
MHz
–
Duty Cycle
47
50
53
%
–
Power up to IMO Switch
150
–
–
μs
Notes
10.4.8 AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-24. 5V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
2.5
2.5
μs
μs
–
–
–
–
2.2
2.2
μs
μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.65
0.65
–
–
–
–
V/μs
V/μs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
μs
μs
–
–
–
–
2.6
2.6
μs
μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Notes
Table 10-25. 3.3V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High
Document Number: 38-12018 Rev. *U
Notes
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10.4.9 AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-26. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
TERASEALL
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Flash Erase Time (Bulk)
TPROGRAM_HOT Flash Block Erase + Flash Block Write Time
TPROGRAM_COLD Flash Block Erase + Flash Block Write Time
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
10
40
–
–
40
Max
20
20
–
–
8
–
–
45
50
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ms
–
–
–
–
100[16]
200[16]
ms
ms
Notes
Vdd > 3.6
3.0 ≤ Vdd ≤ 3.6
Erase all Blocks and protection
fields at once
0°C <= Tj <= 100°C
-40°C <= Tj <= 0°C
Note
16. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 38-12018 Rev. *U
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10.4.10 AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-27. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Symbol
Description
SCL Clock Frequency
FSCLI2C
THDSTAI2C Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
TLOWI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
THIGHI2C
TSUSTAI2C Setup Time for a Repeated START Condition
THDDATI2C Data Hold Time
TSUDATI2C Data Setup Time
TSUSTOI2C Setup Time for STOP Condition
Bus Free Time Between a STOP and START
TBUFI2C
Condition
TSPI2C
Pulse Width of spikes are suppressed by the
input filter.
Standard Mode
Min
Max
0
100
4.0
–
Fast Mode
Min
Max
0
400
0.6
–
Units
Notes
kHz
μs
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
1.3
0.6
0.6
0
100[17]
0.6
1.3
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
–
–
0
50
ns
Figure 10-6. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Note
17. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT Š 250 ns must then be met. This automatically is the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 38-12018 Rev. *U
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11. Packaging Dimensions
This section illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package
and solder reflow peak temperatures.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the Emulator Pod Dimension drawings at http://www.cypress.com.
Figure 11-1. 56-Pin (7x7x0.6 mm) QFN
001-58740 Rev **
Document Number: 38-12018 Rev. *U
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Figure 11-2. 56-Pin (8x8 mm) QFN
SIDE VIEW
TOP VIEW
BOTTOM VIEW
0.08[0.003]
7.90[0.311]
8.10[0.319]
A
C
4.5
1.00[0.039] MAX.
0.05[0.002] MAX.
7.70[0.303]
7.80[0.307]
0.80[0.031] MAX.
0.20[0.008] REF.
N
PIN1 ID
0.20[0.008] R.
N
1
2
2
5.2
0°-12°
C
SEATING PLANE
0.45[0.018]
SOLDERABLE
EXPOSED
PAD
0.30[0.012]
0.50[0.020]
0.50[0.020]
6.45[0.254]
6.55[0.258]
7.90[0.311]
8.10[0.319]
1
7.70[0.303]
7.80[0.307]
0.80[0.031]
DIA.
0.18[0.007]
0.28[0.011]
0.24[0.009]
0.60[0.024]
(4X)
6.45[0.254]
6.55[0.258]
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.162g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
LF56A
LY56A
DESCRIPTION
STANDARD
PB-FREE
001-12921 *A
Figure 11-3. 56-Pin QFN (8 X 8 X 0.9 MM) - Sawn
001-53450 *B
Document Number: 38-12018 Rev. *U
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Figure 11-4. 68-Pin (8x8 mm x 0.89 mm) QFN
TOP VIEW
BOTTOM VIEW
SIDE VIEW
7.90[0.311]
A
8.10[0.319]
0.08
7.70[0.303]
C
5.69
0.9[0.035] MAX
0.05[0.002] MAX
7.80[0.307]
0.70[0.028] MAX
0.2[0.008] REF
Ø
0.18[0.007]
0.28[0.011]
PIN1 ID
0.20 R.
N
N
1
2
3
SOLDERABLE
EXPOSED
PAD
8.10[0.319]
7.90[0.311]
7.80[0.307]
7.70[0.303]
1
2
3
5.69
0°-12°
C
NOTES:
1.
SEATING
PLANE
0.4 B.S.C.
0.24[0.009]
0.60[0.023]
6.50[0.255] REF
HATCH IS SOLDERABLE EXPOSED PAD.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.17g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
DESCRIPTION
LF68
LY68
STANDARD
PB-FREE
NOTE: EXPOSED PAD DIMENSION VARIES BY LEADFRAME CAVITY (PADDLE) SIZE
51-85214 *D
Important Note
■
For information on the preferred dimensions for mounting QFN packages, refer to Application Note, "Application Notes for Surface
Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.
■
Pinned vias for thermal conduction are not required for the low-power PSoC device.
Document Number: 38-12018 Rev. *U
Page 41 of 50
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Figure 11-5. 68-Pin Sawn QFN (8X8 mm X 0.90 mm)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
0.900±0.100
5.7±0.10
8.000±0.100
0.200 REF
5
1
PIN 1 DOT
8.000±0.100
LASER MARK
1
7
0.20±0.05
3
0.400±0.1005
C
0.08
1
8
1
7
6.40 REF
SEATING PLANE
NOTES:
1.
3
4
0.05 MAX
3
4
1
8
1
SOLDERABLE
EXPOSED
PAD
5.7±0.10
3
5
6
8
5
2
6.40 REF
5
1
1
PIN1 ID
R 0.20
0.400 PITCH
5
2
6
8
HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.17g
001-09618 *C
4. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 11-6. 100-Ball (6x6 mm) VFBGA
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.15 M C A B
A1 CORNER
Ø0.30±0.05(100X)
1 2 3 4 5 6 7 8 9 10
0.50
2.25
A
0.50
6.00±0.10
B
A
B
C
D
E
F
G
H
J
K
2.25
6.00±0.10
6.00±0.10
A
4.50
10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
B
0.08 C
0.21±0.05
0.45 REF.
0.10 C
4.50
Document Number: 38-12018 Rev. *U
1.00 MAX
0.21 REF.
SEATING PLANE
C
6.00±0.10
0.15(4X)
REFERENCE JEDEC MO-195C
PKG. WEIGHT: TBD (NEW PKG.)
51-85209 *C
Page 42 of 50
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Figure 11-7. 100-Pin (14x14 x 1.4 mm) TQFP
51-85048 *D
11.1 Thermal Impedance
Typical θJA [18]
12.93 °C/W
13.05 °C/W
65 °C/W
51 °C/W
Package
56 QFN[19]
68 QFN[19]
100 VFBGA
100 TQFP
11.2 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Package
56 QFN
68 QFN
100 VFBGA
100 TQFP
Minimum Peak Temperature[20]
240°C
240°C
240°C
240°C
Maximum Peak Temperature
260°C
260°C
260°C
260°C
Notes
18. TJ = TA + POWER x θJA
19. To achieve the thermal impedance specified for the QFN package,refer to "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages"
available at http://www.amkor.com.
20. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications
Document Number: 38-12018 Rev. *U
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12. Development Tool Selection
12.1 Software
12.3 Evaluation Tools
12.1.1 PSoC Designer
All evaluation tools can be purchased from the Cypress Online
Store.
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at http://www.cypress.com
and includes a free C compiler.
12.1.2 PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com.
12.3.1 CY3210-MiniProg1
The CY3210-MiniProg1 kit enables a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
All development kits can be purchased from the Cypress Online
Store.
■
Getting Started Guide
■
USB 2.0 Cable
12.2.1 CY3215-DK Basic Development Kit
12.3.2 CY3210-PSoCEval1
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
Advance emulation features also supported through PSoC
Designer. The kit includes:
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
12.2 Development Kits
■
PSoC Designer Software CD
■
ICE-Cube In-Circuit Emulator
■
ICE Flex-Pod for CY8C29x66 Family
■
Cat-5 Adapter
■
Mini-Eval Programming Board
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
iMAGEcraft C Compiler (Registration Required)
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
Document Number: 38-12018 Rev. *U
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
12.3.3 CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator
and plenty of bread boarding space to meet all of your evaluation
needs. The kit includes:
■
PSoCEvalUSB Board
■
LCD Module
■
MIniProg Programming Unit
■
Mini USB Cable
■
PSoC Designer and Example Projects CD
■
Getting Started Guide
■
Wire Pack
Page 44 of 50
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12.4 Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
12.4.1 CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
12.4.2 CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note: CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
Modular Programmer Base
■
PSoC ISSP Software CD
■
3 Programming Module Cards
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
MiniProg Programming Unit
■
USB 2.0 Cable
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
12.5 Accessories (Emulation and Programming)
Table 12-1. Emulation and Programming Accessories
Part #
Pin Package
Flex-Pod Kit[21]
Foot Kit[22]
CY8C24794-24LFXI
56 QFN
CY3250-24X94QFN
CY3250-56QFN-FK
CY8C24894-24LFXI
56 QFN
CY3250-24X94QFN
CY3250-56QFN-FK
CY8C24794-24LQXI
56 QFN
CY3250-24X94QFN
None
Adapter[23]
Adapters can be found at
http://www.emulation.com.
Notes
21. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
22. Foot kit includes surface mount feet that are soldered to the target PCB.
23. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are found at
http://www.emulation.com.
Document Number: 38-12018 Rev. *U
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13. Ordering Information
XRES Pin
Analog Outputs
Analog Inputs
Digital I/O Pins
Analog Blocks
Digital Blocks
Temperature
Range
SRAM
(Bytes)
100 Pin OCD TQFP[24]
100-Ball OCD (6x6 mm)
VFBGA[24]
68-Pin QFN (Sawn)
68-Pin QFN (Sawn) (Tape and
Reel)
56-Pin (8x8 mm) QFN
56-Pin (8x8 mm) QFN
(Tape and Reel)
56-Pin (8x8 mm) QFN (Sawn)
56-Pin (8x8 mm) QFN (Sawn)
(Tape and Reel)
56-Pin (8x8 mm) QFN
56-Pin (8x8 mm) QFN
(Tape and Reel)
56-Pin (8x8 mm) QFN (Sawn)
56-Pin (8x8 mm) QFN (Sawn)
(Tape and Reel)
100-Ball (6x6 mm) VFBGA
68-Pin QFN (Sawn)
68-Pin QFN (Sawn)
(Tape and Reel)
Flash
(Bytes)
Package
Ordering
Code
Table 13-1. CY8C24x94 PSoC Device’s Key Features and Ordering Information
CY8C24094-24AXI
CY8C24094-24BVXI
16K
16K
1K
1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
56
56
48
48
2
2
Yes
Yes
CY8C24094-24LTXI
CY8C24094-24LTXIT
16K
16K
1K
1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
56
56
48
48
2
2
Yes
Yes
CY8C24794-24LFXI
CY8C24794-24LFXIT
16K
16K
1K
1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
50
50
48
48
2
2
No
No
CY8C24794-24LTXI
CY8C24794-24LTXIT
16K
16K
1K
1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
50
50
48
48
2
2
No
No
CY8C24894-24LFXI
CY8C24894-24LFXIT
16K
16K
1K
1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
49
49
47
47
2
2
Yes
Yes
CY8C24894-24LTXI
CY8C24894-24LTXIT
16K
16K
1K
1K
-40°C to +85°C
-40°C to +85°C
4
4
6
6
49
49
47
47
2
2
Yes
Yes
CY8C24994-24BVXI
CY8C24994-24LTXI
CY8C24994-24LTXIT
16K
16K
16K
1K
1K
1K
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
4
4
4
6
6
6
56
56
56
48
48
48
2
2
2
Yes
Yes
Yes
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Notes
24. This part may be used for in-circuit debugging. It is NOT available for production
Document Number: 38-12018 Rev. *U
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13.1 Ordering Code Definitions
CY 8 C 24 XXX- SP XX
Package Type:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX/LKX/LQX/LTX = QFN Pb-Free
AX = TQFP Pb-Free
BVX = VFBGA Pb-Free
Speed: 24 MHz
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 38-12018 Rev. *U
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Document History Page
Document Title: CY8C24094, CY8C24794, CY8C24894, CY8C24994 PSoC® Programmable System-on-Chip
Document Number: 38-12018
Rev.
ECN No. Submission
Date
Orig. of
Change
Description of Change
**
133189
01.27.2004
NWJ
New silicon and new document – Advance Data Sheet.
*A
251672
See ECN
SFV
First Preliminary Data Sheet. Changed title to encompass only the CY8C24794
because the CY8C24494 and CY8C24694 are not being offered by Cypress.
*B
289742
See ECN
HMT
Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2
MACs. Change 512 bytes of SRAM to 1K. Add dimension key to package. Remove
HAPI. Update diagrams, registers and specs.
*C
335236
See ECN
HMT
Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP
programming pinout notation. Add Reflow Temp. table. Update features (MAC,
Oscillator, and voltage range), registers (INT_CLR2/MSK2, second MAC), and
specs. (Rext, IMO, analog output buffer...).
*D
344318
See ECN
HMT
Add new color and logo. Expand analog arch. diagram. Fix I/O #. Update Electrical
Specifications.
*E
346774
See ECN
HMT
Add USB temperature specifications. Make data sheet Final.
*F
349566
See ECN
HMT
Remove USB logo. Add URL to preferred dimensions for mounting MLF packages.
*G
393164
See ECN
HMT
Add new device, CY8C24894 56-pin MLF with XRES pin. Add Fimousb3v char. to
specs. Upgrade to CY Perform logo and update corporate address and copyright.
*H
469243
See ECN
HMT
Add ISSP note to pinout tables. Update typical and recommended Storage
Temperature per industrial specs. Update Low Output Level maximum I/OL
budget. Add FLS_PR1 to Register Map Bank 1 for users to specify which Flash
bank should be used for SROM operations. Add two new devices for a 68-pin QFN
and 100-ball VFBGA under RPNs: CY8C24094 and CY8C24994. Add two
packages for 68-pin QFN. Add OCD non-production pinouts and package
diagrams. Update CY branding and QFN convention. Add new Dev. Tool section.
Update copyright and trademarks.
*I
561158
See ECN
HMT
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add
CY8C20x34 to PSoC Device Characteristics table. Add detailed dimensions to
56-pin QFN package diagram and update revision. Secure one package
diagram/manufacturing per QFN. Update emulation pod/feet kit part numbers. Fix
pinout type-o per TestTrack.
*J
728238
See ECN
HMT
Add CapSense SNR requirement reference. Update figure standards. Update
Technical Training paragraphs. Add QFN package clarifications and dimensions.
Update ECN-ed Amkor dimensioned QFN package diagram revisions. Reword
SNR reference. Add new 56-pin QFN spec.
*K
2552459
08/14/08
AZIE/PYRS
Add footnote on AGND descriptions to avoid using P2[4] for digital signaling as it
may add noise to AGND. Remove reference to CMP_GO_EN1 in Map Bank 1
Table on Address 65; this register has no functionality on 24xxx. Add footnote on
die sales. Add description 'Optional External Clock Input’ on P1[4] to match
description of P1[4].
*L
2616550
12/05/08
*M
2657956
02/11/09
OGNE/PYRS Updated Programmable Pin Configuration detail.
Changed title from PSoC® Mixed-Signal Array to PSoC® Programmable
System-on-Chip™
DPT/PYRS
Document Number: 38-12018 Rev. *U
Added package diagram 001-09618 and updated Ordering Information table
Page 48 of 50
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Document Title: CY8C24094, CY8C24794, CY8C24894, CY8C24994 PSoC® Programmable System-on-Chip
Document Number: 38-12018
*N
2708135
05/18/2009
BRW
Added Note in the Pin Information section on page 8.
Removed reference to Hi-Tech Lite Compiler in the section Development Tools
Selection on page 42.
*O
2718162
06/11/2009
DPT
Added 56-Pin QFN (Sawn) package diagram and updated ordering information
*P
2762161
09/10/2009
RLRM
Updated the following parameters:
DCILO, F32K_U, FIMO6, TPOWERUP, TERASE_ALL, TPROGRAM_HOT, and
TPROGRAM_COLD. Added SRPOWER_UP parameter in AC specs table.
*Q
2768530
09/24/09
RLRM
Ordering Information table: Changed XRES Pin value for CY8C24894-24LTXI and
CY8C24894-24LTXIT to ‘Yes’.
*R
2817938
11/30/09
KRIS
Ordering Information: Updated CY8C24894-24LTXI and CY8C24894-24LTXIT
parts as Sawn and updated the Digital I/O and Analog Pin values
Added Contents page. Updated 68 QFN package diagram (51-85124)
*S
2846641
1/12/10
RLRM
Added package diagram 001-58740 and updated Development Tools section.
*T
2867363
01/27/10
ANUP
Modified Note 9 to remove voltage range 2.4V to 3.0V
*U
2901653
03/30/2010
NJF
Document Number: 38-12018 Rev. *U
Updated Cypress website links
Added TXRST, DC24M, TBAKETEMP and TBAKETIME parameters
Removed reference to 2.4V
Removed sections ‘Third Party Tools’ ‘Build a PSoC Emulator into your Board’
Updated package diagrams
Removed inactive parts from ordering information table.
Page 49 of 50
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12018 Rev. *U
Revised March 30, 2010
Page 50 of 50
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective
corporations.
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