ON NCP81248MNTXG Three-rail controller Datasheet

NCP81248
Three-Rail Controller with
Intel Proprietary Interface
for IMVP8 CPU Applications
The NCP81248 contains a two−phase, and two single−phase buck
regulator controllers optimized for Intel IMVP8 compatible CPUs.
The two−phase controller combines true differential voltage
sensing, differential inductor DCR current sensing, input voltage
feed−forward, and adaptive voltage positioning to provide accurately
regulated power for IMVP8 CPU.
The two single−phase controllers make use of ON Semiconductor’s
patented high performance RPM operation. RPM control maximizes
transient response while allowing smooth transitions between
discontinuous frequency scaling operation and continuous mode full
power operation. The single−phase rails have a low offset current
monitor amplifier with programmable offset compensation for high
accuracy current monitoring.
Features Common to All Rails
•
•
•
•
•
•
•
•
•
•
•
•
•
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MARKING
DIAGRAM
1 48
QFN48
CASE 485BA
NCP81248
FAWLYYWW
G
NCP81243 = Specific Device Code
F
= Wafer Fab Code
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G
= Pb−Free Package
Vin Range 4.5 V to 25 V
Startup into Pre−Charged Loads While Avoiding False OVP
Digital Soft Start Ramp
Adjustable Vboot (except Rail3)
ORDERING INFORMATION
High Impedance Differential Output Voltage Amplifiers
Device
Package
Shipping
Dynamic Reference Injection
NCP81248MNTXG
QFN48
2500 / Tape &
Programmable Output Voltage Slew Rates
(Pb−Free)
Reel
Dynamic VID Feed−Forward
†For information on tape and reel specifications, inDifferential Current Sense Amplifiers for Each Phase
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Programmable Adaptive Voltage Positioning (AVP)
Brochure, BRD8011/D.
Switching Frequency Range of 200 kHz –1.2 MHz
Single−phase Rail Features
Digitally Stabilized Switching Frequency
• Supports Intel proprietary interface Addresses 00, 01,
UltraSonic Operation
02 and 03
Two−phase Rail Features
• High Performance RPM Control System
• Supports Intel proprietary interface Addresses 00 and
• Low Offset IOUT Monitor
01
• Zero Droop Capable
• Current Mode Dual Edge Modulation for Fastest Initial
Other Features
Response to Transient Loading
• PSYS Input Monitor
• High Performance Operational Error Amplifier
• Thermal Monitors for Three Intel proprietary interface
• Accurate Total Summing Current Amplifier
Addresses
• Phase−to−Phase Dynamic Current Balancing
•
These Devices are Pb−Free, Halogen Free/BFR Free
• Power Saving Phase Shedding
and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 1
1
Publication Order Number:
NCP81248/D
37
38
39
40
41
42
43
44
45
46
1
36
2
35
3
34
NCP81248
4
5
33
32
(TOP VIEW)
6
31
7
30
8
29
Tab: GROUND
9
28
24
23
22
21
20
19
18
PWM_1b
DRVON
SCLK
ALERT#
SDIO
VR_HOT#
IOUT_1a
CSP_1a
CSN_1a
ILIM_1a
COMP_1a
VSN_1a
VCC
ROSC_COREGT
ROSC_SAUS
PWM1_2ph
PWM2_2ph
ICCMAX_2ph
ICCMAX_1a
ICCMAX_1b
ADDR_VBOOT
PWM_1a
TSENSE_1ph
VSP_1a
17
25
16
26
12
15
27
11
14
10
13
IOUT_2ph
DIFFOUT_2ph
FB_2ph
COMP_2ph
ILIM_2ph
CSCOMP_2ph
CSSUM_2ph
CSREF_2ph
CSP2_2ph
CSP1_2ph
TSENSE_2ph
VRMP
47
48
VSN_2ph
VSP_2ph
PSYS
VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b
VR_RDY
EN
NCP81248
Figure 1.
NCP81248
IMVP8
NCP81382
DrMOS
Vcc_Rail1
NCP81382
DrMOS
Vcc_Rail2
Intel[
NCP81382
DrMOS
Vcc_Rail3
NCP81382
DrMOS
SVID
Figure 2. Typical DrMOS Application Diagram
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2
NCP81248
5V
VRHOT#
VIN
VCC
5V
PSYS
VCCD
VCCIO VCCIO
TSENSE_1ph
BOOT
VCC
t
PHASE
ZCD_EN
VCC_Rail1
VSW
SMOD#
SDIO
ALERT#
SCLK
NCP81382
PWM_1a
PWM
DRVON
DISB#
VIN
t
VRMP
CSP_1a
CSN_1a
SKT_SNS +
VSP_1a
VR_RDY
EN
SKT_SNS −
VSN_1a
VIN
COMP_1a
5V
VCCD
ILIM_1a
BOOT
VCC
TSENSE_2ph
t
PHASE
ZCD_EN
IOUT_1a
VCC_Rail2
VSW
SMOD#
NCP81381
PWM1_2ph
PWM
DISB#
DIFFOUT_2ph
CSP1_2ph
CSREF_2ph
FB_2ph
CSP2_2ph
VIN
CSSUM_2ph
COMP_2ph
5V
IOUT_2ph
ILIM_2ph
VCCD
PHASE
ZCD_EN
CSCOMP_2ph
ROSC_COREGT
BOOT
VCC
t
VSW
SMOD#
NCP81381
PWM2_2ph
PWM
ROSC_SAUS
DISB#
SKT_SNS +
VSP_2ph
ICCMAX_2ph
SKT_SNS −
VSN_2ph
ICCMAX_1a
VIN
ICCMAX_1b
5V
VCCD
VCC
ZCD_EN
ADDR_VBOOT
BOOT
PHASE
VCC_Rail3
VSW
SMOD#
NCP81380
PWM_1b
PWM
t
DISB#
COMP_1b
CSP_1b
CSN_1b
ILIM_1b
IOUT_1b
SKT_SNS +
VSP_1b
SKT_SNS −
VSN_1b
GROUND
Figure 3. Application Schematic
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3
NCP81248
1.3V
VRHOT# 31
VSP
THERMAL
MONITOR
OVP
VSN
47 VSP_2ph
OCP
SCLK 34
CSCOMP
2
DIFFOUT_2ph
3
FB_2ph
4
COMP_2ph
DAC
FEED−
FORWARD
OVP
_
PS#
ENABLE
48 VSN_2ph
DAC
DAC
SVID
INTERFACE
& LOGIC
ALERT# 33
VSN
_
ENABLE
SDIO 32
VSP
DIFF
AMP
OVP
DRVON
CSREF
+
VR_RDY 38
DATA
REGISTERS
VR READY
LOGIC
ERROR
AMP
1.3V
ROSC_COREGT 14
ROSC_SAUS 15
MUX
ICCMAX_2ph 18
CURRENT
SENSE
AMP
ICCMAX_1a 19
IOUT_2ph
6
CSCOMP_2ph
_
7
CSSUM_2ph
+
8
CSREF_2ph
5
ILIM_2ph
1
IOUT_2ph
Buffer OVERCURRENT
PROGRAMMING
ICCMAX_1b 20
ADC
IOUT_1a
OVP
ADDR_VBOOT 21
IOUT_1b
OVERCURRENT
COMPARATORS
MAX
OVP
TSENSE_2ph 11
TSENSE_1ph 23
ENABLE
PSYS 46
OCP
VRMP 12
PS#
OSCILLATOR
& RAMP
GENERATORS
VRMP
DRVON
COMP
EN 37
UVLO & EN
COMPARATORS
OVP
PWM
GENERATORS
PWM2
OCP
ENABLE
PS#
GROUND 49
CURRENT
MONITOR
35 DRVON
9
CSP2_2ph
10 CSP1_2ph
PWM1
VCC 13
CURRENT
BALANCE
AMPLIFIERS
IPH2
IPH1
IOUT
PS#
ZERO
CURRENT
DETECTION
POWER
STATE
GATE
16 PWM1_2ph
17 PWM2_2ph
Figure 4. 2−Phase Rail Block Diagram
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4
NCP81248
DAC
FEED−
FORWARD
FROM SVID
INTERFACE
DAC FEEDFORWARD
CURRENT
DAC
DAC
VSN
gm
VSP
25 VSN_1a
24 VSP_1a
26 COMP_1a
gm
DROOP
CURRENT
+
CURRENT
SENSE AMP
Av=1
28 CSN_1a
_
OVP OVP REF
DRVON
COMP
gm
OVP
CURR
PWM
GENERATOR
OCP
RAMP
OCP
OVERCURRENT
PROGRAMMING
OVERCURRENT
COMPARATORS
OCP REF
CURRENT
MONITOR
IOUT
VRMP
PWM
RAMP
GENERATOR
27 ILIM_1a
gm
DAC
FREQ
29 CSP_1a
ZERO
CURRENT
DETECTION
PS#
30 IOUT_1a
22 PWM_1a
Figure 5. Single Phase “a” Block Diagram
DAC
FEED−
FORWARD
DAC
VSN
gm
VSP
44 VSN_1b
45 VSP_1b
43 COMP_1b
gm
DROOP
CURRENT
Av=1
_
INTERFACE
CURRENT
DAC
+
FROM SVID
DAC FEEDFORWARD
COMP
gm
OVP
CURR
PWM
GENERATOR
OCP
RAMP
OCP
OVERCURRENT
PROGRAMMING
OVERCURRENT
COMPARATORS
OCP REF
IOUT
FREQ
41 CSN_1b
42 ILIM_1b
gm
DAC
RAMP
GENERATOR
40 CSP_1b
OVP OVP REF
DRVON
VRMP
CURRENT
SENSE AMP
PWM
PS#
ZERO
CURRENT
DETECTION
Figure 6. Single Phase “b” Block Diagram
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5
CURRENT
MONITOR
39 IOUT_1b
36 PWM_1b
NCP81248
Table 1. NCP81248 PIN DESCRIPTIONS
Pin
No.
Symbol
1
IOUT_2ph
2
DIFFOUT_2ph
Description
IOUT gain programming pin for the 2−phase regulator
Output of the 2−phase regulator’s output differential remote sense amplifier
3
FB_2ph
4
COMP_2ph
Error amplifier voltage feedback input for the 2−phase regulator
5
ILIM_2ph
6
CSCOMP_2ph
7
CSSUM_2ph
Inverting input of total−current−sense amplifier for the 2−phase regulator
8
CSREF_2ph
Total−current−sense amplifier reference voltage input for the 2−phase regulator
9
CSP2_2ph
Non−inverting input to 2−phase regulator Phase 2 current−balance amplifier
10
CSP1_2ph
Non−inverting input to 2−phase regulator Phase 1 current−balance amplifier
11
TSENSE_2ph
12
VRMP
13
VCC
14
ROSC_COREGT
15
ROSC_SAUS
16
PWM1_2ph
2−phase regulator Phase 1 PWM output
17
PWM2_2ph
2−phase regulator Phase 2 PWM output
18
ICCMAX_2ph
During startup, the IccMax of the 2−phase regulator is programmed by a pull−down resistor on this
pin
19
ICCMAX_1a
During startup, the ICCMAX of 1−phase Regulator 1a is programmed by a pulldown resistor on this
pin
20
ICCMAX_1b
During startup, the ICCMAX of 1−phase Regulator 1b is programmed by a pulldown resistor on this
pin
21
ADDR_VBOOT
22
PWM_1a
23
TSENSE_1ph
24
VSP_1a
Positive input of 1−phase regulator 1a differential output voltage sense amplifier
25
VSN_1a
Negative input of 1−phase regulator 1a differential output voltage sense amplifier
26
COMP_1a
Output of the error amplifier and the inverting inputs of PWM comparators for the two−phase regulator
Over−current monitor input for the 2−phase regulator −− programmed with a resistor to
CSCOMP_2ph
Output of total−current−sense amplifier for the 2−phase regulator
Temperature sense input for the 2−phase regulator (see Rail Configuration Table)
VIN Feed−forward input for compensating modulator ramp−slopes. The current fed into this pin is
used to control the ramp of the PWM slopes. Also, the input monitoring VIN for undervoltage (UVLO)
Power for the internal control circuits. A decoupling capacitor must be connected from this pin to
ground
Switching frequency program input for rails configured as Rail1 and Rail2
Switching frequency program input for the 1−phase rail configured as Rail3
During startup, a resistor to GND programs Intel proprietary interface addresses and VBOOT options
for all three rails
1−phase regulator 1a PWM output
Temperature sense input for 1−phase regulator. (see Rail Configuration Table)
Compensation for 1−phase regulator 1a
27
ILIM_1a
Current−limit for 1−phase regulator 1a is programmed by a pull−down resistor on this pin
28
CSN_1a
Negative input of 1−phase regulator 1a differential current sense amplifier
29
CSP_1a
Positive input of 1−phase regulator 1a differential current sense amplifier
Pull this pin to VCC to disable 1−phase regulator 1a
30
IOUT_1a
IOUT gain programming pin for 1−phase regulator 1a
31
VR_HOT#
Open drain output for an over−temperature condition detected on any TSENSE input
32
SDIO
33
ALERT#
Serial VID data interface
34
SCLK
35
DRVON
Enable output for external discrete FET drivers and/or ON Semiconductor DrMOS.
36
PWM1b
1−phase regulator 1b PWM output
Serial VID ALERT#
Serial VID clock
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NCP81248
Table 1. NCP81248 PIN DESCRIPTIONS
Pin
No.
Symbol
37
EN
38
VR_RDY
Open drain output. High indicates all three rails are ready to accept Intel proprietary interface commands
39
IOUT_1b
IOUT gain programming pin for 1−phase regulator 1b
40
CSP_1b
Positive input of 1−phase regulator 1b differential current sense amplifier
Pull this pin to VCC to disable 1−phase regulator 1b
41
CSN_1b
Negative input of 1−phase regulator 1b differential current sense amplifier
42
ILIM_1b
Current−limit for 1−phase regulator 1b is programmed by a pull−down resistor on this pin
43
COMP_1b
44
VSN_1b
Negative input of 1−phase regulator 1b differential output voltage sense amplifier
45
VSP_1b
Positive input of 1−phase regulator 1b differential output voltage sense amplifier
46
PSYS
47
VSP_2ph
Positive input of 2−phase regulator differential output voltage sense amplifier
48
VSN−2ph
Negative input of 2−phase regulator differential output voltage sense amplifier
Description
Enable. High activates all configured rails
Compensation for 1−phase regulator 1b
System power signal input. Resistor to ground needed for scaling. When the NCP81248 is configured
with a Rail4, this input is a temperature monitor. (see Rail Configuration Table)
Table 2. MAXIMUM RATINGS
Symbol
Min
Max
Unit
Pin Voltage Range (Note 1)
Rating
VSN_x
−0.3
+0.3
V
Pin Voltage Range (Note 1)
VCC
−0.3
6.5
V
Pin Voltage Range (Note 1)
IOUT_x
−0.3
2.5
V
Pin Voltage Range (Note 1)
VRMP
−0.3
+25
V
Pin Voltage Range (Note 1)
All Other Pins
−0.3
VCC + 0.3
V
Junction Temperature
TJ(max)
−40
125
°C
Operating Ambient Temperature
TJ(OP)
−40
100
°C
Storage Temperature Range
TSTG
−40
150
°C
Moisture Sensitivity Level
QFN Package
MSL
1
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
TSLD
−
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All signals referenced to GND unless noted otherwise.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
4. Pin ratings referenced to VCC apply with VCC at any voltage within the VCC Pin Voltage Range.
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NCP81248
Table 3. THERMAL CHARACTERISTICS
Symbol
Value
Unit
Thermal Characteristic
QFN Package (Note 5)
Rating
R JA
68
_C/W
Thermal Characteristic
QFN Package (Note 5)
R JC
8
_C/W
5. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
Table 4. ELECTRICAL CHARACTERISTICS – ELEMENTS COMMON TO SINGLE & 2−PHASE RAILS (VCC = 5.0 V,
VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TA ≤ 100°C unless
noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
5.25
V
VCC INPUT SUPPLY
4.75
Supply Voltage Range
Quiescent Current
UVLO Threshold
EN = high, TA = 100°C
28
32
mA
EN = low, TA = 25°C
30
50
mA
4.5
V
VCC rising
VCC falling
UVLO Hysteresis (Note 6)
4
180
V
290
mV
VRMP
UVLO Threshold
VRMP Rising
VRMP Falling
UVLO Hysteresis (Note 6)
Ramp Feed−forward Control Range
Range in which the ramp slope
is affected by VRMP voltage
3.95
3
3.24
500
710
5
4.25
V
V
mV
20
V
1.0
mA
ENABLE INPUT
Enable High Input Leakage Current
External 1k pull−up to 3.3 V
Activation Level
VUPPER
Deactivation Level
VLOWER
Total Hysteresis (Note 6)
VRISING – VFALLING
Enable Delay Time − Rising
Time from Enable transitioning
HIGH to DRVON going HIGH
Enable Delay Time – Falling (Note 6)
Time from Enable transitioning
LOW to DRVON below 0.8 V
190
ns
Pulldown applied only prior to
softstart
20
mA
0.8
V
0.3
295
1.0
2.1
V
mV
2.5
ms
PHASE DETECTION
CSP Pin Pulldown Current (Note 6)
CSP Pin Threshold voltage
4.5
Phase Detect Timer (Note 6)
V
1.8
ms
Soft Start Slew Rate
15
mV/ms
Slew Rate Slow
15
mV/ms
Slew Rate Fast
30
mV/ms
DAC SLEW RATE
DRVON
Output High Voltage
Sourcing 500 mA
Output Low Voltage
Sinking 500 mA
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8
3.0
V
0.1
V
NCP81248
Table 4. ELECTRICAL CHARACTERISTICS – ELEMENTS COMMON TO SINGLE & 2−PHASE RAILS (VCC = 5.0 V,
VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TA ≤ 100°C unless
noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
DRVON
Rise Time
Fall Time
CL (PCB) = 20 pF,
DVo = 10% to 90%
2.5
Internal Pull Up Resistance
Internal Pull Down Resistance
ns
150
EN = Low
2.5
kW
50
kW
PWM OUTPUTS
Output High Voltage
Sourcing 500 mA
Output Mid Voltage
PS2, No Load
Output Low Voltage
Sinking 500 mA
Rise and Fall Time (Note 6)
CL (PCB) = 50 pF,
DVo = 10% to 90%
VCC−
0.2V
1.9
V
2.0
2.1
V
0.7
V
8
ns
VR_RDY OUTPUT
Output Low Saturation Voltage
IVR_RDY = 4 mA
0.3
V
Rise Time
External pull−up of 1 kW to 3.3 V
CTOT = 45 pF, DVo = 10% to
90%
120
ns
Fall Time
External pull−up of 1 kW to 3.3 V
CTOT = 45 pF, DVo = 90% to
10%
25
ns
Output Leakage Current When High
VR_RDY= 5.0 V
1.0
mA
0.3
V
−1.0
1.0
mA
0
2.00
V
1
LSB
−1.0
VR_HOT#
Output Low Voltage
IVRHOT = 4 mA
Output Leakage Current
High Impedance State
ADC
Linear Input Voltage Range
Differential Nonlinearity (DNL)
Highest 8−bits
Conversion Time
7.4
ms
Conversion Rate
136
kHz
Total Unadjusted Error (TUE)
−1.25
+1.25
%
Power Supply Sensitivity
±1
%
Round Robin Time
59
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Guaranteed by design or characterization data. Not tested in production.
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NCP81248
Table 5. ELECTRICAL CHARACTERISTICS – TWO PHASE REGULATOR (VCC = 5.0 V, VEN = 2.0 V, CVCC=0.1 mF unless
specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed
by test, design or statistical correlation.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
1
mA
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current − VSP
VSP = 1.3 V
Input Bias Current − VSN
VSN = 0 V
−1
−25
25
nA
VSP Input Voltage Range
−0.3
3.0
V
VSN Input Voltage Range
−0.3
0.3
V
−3 dB Bandwidth (Note 7)
CL = 20 pF to GND,
RL = 10 kW to GND
18
MHz
Closed Loop DC gain
VVSP − VVSN = 0.5 to 1.3 V
1.0
V/V
ERROR AMPLIFIER
Input Bias Current
VFB = 1.3 V
−400
400
Open Loop DC Gain (Note 7)
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
Open Loop Unity Gain Bandwidth (Note 7)
CL = 20 pF to GND,
RL = 10 kW to GND
20
MHz
Slew Rate (Note 7)
DVin = 100 mV, G = −10V/V,
DVout = 1.5 V – 2.5V,
CL = 20 pF to GND,
DC Load = 10k to GND
30
V/ms
Maximum Output Voltage
ISOURCE = 2.0 mA
Minimum Output Voltage
ISINK = 2.0 mA
3.5
nA
V
1
V
−375
375
mV
−7.5
7.5
nA
CURRENT SUMMING AMPLIFIER
Offset Voltage (Note 7)
Input Bias Current
VOS
VCSSUM = VCSREF = 1 V
Open Loop Gain (Note 7)
Unity Gain Bandwidth (Note 7)
CL = 20 pF to GND,
RL = 10 kW to GND
Maximum CSCOMP Output Voltage
Isource = 2 mA
Minimum CSCOMP Output Voltage
Isink = 500 mA
80
dB
10
MHz
3.5
V
100
mV
30
mV
−50
50
nA
0
2.3
V
Isink = 25 mA
7
CURRENT BALANCE AMPLIFIERS
Input Bias Current
VCSP1 = VCSP2 = VCSREF = 1.2 V
Common Mode Input Voltage Range
VCSP1 = VCSP2 = VCSREF
Differential Input Voltage Range
VCSREF = 1.2 V
−100
100
mV
Input Offset Voltage Matching
VCSP1 = VCSP2 = VCSREF = 1.2 V
Deviation from average offset
−1.5
1.5
mV
Current Sense Amplifier Gain
0 V < VCSPX − VCSREF < 0.1 V
5.7
6.3
V/V
Current Sense Gain Matching
10 mV < VCSPX − VCSREF <
30 mV
−4
4
%
−3 dB Bandwidth (Note 7)
6.0
8
MHz
IOUT OUTPUT
Input Referred Offset Voltage
ILIM to CSREF
Output Source Current
ILIM sink current = 20 mA
190
Current Gain
IIOUT / IILIM; RILIM = 20k, RIOUT =
5.0k , DAC = 0.8 V, 1.25 V, 1.52V
9.5
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10
−2.75
2.75
mV
mA
10
10.5
mA/mA
NCP81248
Table 5. ELECTRICAL CHARACTERISTICS – TWO PHASE REGULATOR (VCC = 5.0 V, VEN = 2.0 V, CVCC=0.1 mF unless
specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed
by test, design or statistical correlation.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
9.0
10
11
mA
OVERCURRENT PROTECTION
ILIM Threshold Current
(delayed OCP shutdown)
ILIM Threshold Current
(immediate OCP shutdown)
ICL0
ICL1
13.5
ICLM1
Shutdown Delay (immediate)
Shutdown Delay (delayed)
mA
6.7
ICLM0
tOCPDLY
ILIM Offset Voltage
VILIM − VCSREF; ILIM sourcing
15 mA
15
16.5
mA
10
mA
300
ns
50
ms
−2
2
mV
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Absolute Over Voltage Threshold
Over Voltage Threshold Above DAC
VOVABS2
VOVP2
Over Voltage Delay (Note 7)
Under Voltage
CSREF voltage during softstart
VVSP – VVSN – VID rising
2
365
VVSP – VVSN rising to PWM low
VUVM
Under−voltage Delay (Note 7)
VVSP – VVSN – VID falling
V
430
25
−370
VVSP – VVSN falling to VR_RDY
falling
−295
mV
ns
−225
mV
ms
5
OSCILLATOR
200
Switching Frequency Range
−
1200
kHz
MODULATORS (PWM Comparators)
0% Duty Cycle
COMP voltage when the PWM
outputs remain LO
1.3
V
100% Duty Cycle
COMP voltage when the PWM
outputs remain HI VRMP = 12.0 V
2.5
V
±15
deg
PWM Phase Angle Error
TSENSE_2ph
Alert# Assert Threshold
25°C to 100°C
488
mV
Alert# De−assert Threshold
25°C to 100°C
510
mV
VRHOT Assert Threshold
25°C to 100°C
469
mV
VRHOT Rising Threshold
25°C to 100°C
Bias Current
25°C to 100°C
116
120
124
mA
Applied only after enabling, and
prior to softstart.
9.63
9.98
10.32
mA
489
mV
ICCMAX PIN
Bias Current
IMXBIAS2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design or characterization data. Not tested in production.
www.onsemi.com
11
NCP81248
Table 6. ELECTRICAL CHARACTERISTICS – SINGLE PHASE REGULATORS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF
unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TA ≤ 100°C unless noted otherwise, and are
guaranteed by test, design or statistical correlation.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
Input Bias Current
VSP – see DROOP OUTPUT
−25
25
nA
VSP Input Voltage Range
VSN
−0.3
3.0
V
VSN Input Voltage Range
−0.3
0.3
V
1.9
mS
500
mV
Gain
1.2
gmEA
Input Offset
1.6
−500
Open loop Gain (Note 8)
Load = 1 nF in series with 1 kW
in parallel with 10 pF to ground
73
dB
Source Current
Input Differential −200 mV
200
mA
Sink Current
Input Differential 200 mV
200
mA
−3dB Bandwidth (Note 8)
Load = 1 nF in series with 1 kW
in parallel with 10 pF to ground
15
MHz
CURRENT SENSE AMPLIFIER
Input Bias Current
VCSP = VCSN = 1.2 V
−50
50
nA
Common Mode Input Range (Note 8)
VCSP = VCSN
0
2.0
V
Common Mode Rejection
VCSP = VCSN = 0.5 V to 1.2 V
45
Differential Input Voltage Range (Note 8)
VCSN = 1.2 V
−70
70
mV
−3dB Bandwidth (Note 8)
80
dB
6
MHz
IOUT
0 mV ≤ VCSP − VCSN ≤ 25 mV;
25°C
0.95
Output Offset Current
0 ≤ VIOUT ≤ 2 V
−250
Maximum Output Current (Note 8)
0 ≤ VIOUT ≤ 2 V
70
mA
Maximum Output Voltage (Note 8)
IIOUT = −100 mA
2.1
V
0 V ≤ VCSP − VCSN ≤ 0.1 V
0.94
Gain
gmIOUT
1.0
1.05
mS
250
nA
DROOP OUTPUT (VSP PIN)
Gain
gmVSP
1.0
1.06
mS
1100
nA
Output Offset Current
0.5 ≤ VVSP ≤ 1.2 V
Maximum Output Current (Note 8)
0 ≤ VVSP ≤ 1.8 V
70
mA
Output Voltage Range (Note 8)
IVSP = −100 mA
1.8
V
18 mV ≤ VCSP − VCSN ≤ 50 mV
0.90
Output Offset Current
VILIM = 1.3 V
−1.0
Maximum Output Current (Note 8)
0 ≤ VILIM ≤ 1.3 V
70
mA
Maximum Output Voltage (Note 8)
IILIM = −100 mA
1.4
V
−1100
OVERCURRENT PROTECTION (ILIM PIN)
Gain
Activation Threshold Voltage
gmILIM
VCL
1.275
Activation Delay (Note 8)
1.0
1.3
1.08
mS
1.0
mA
1.325
250
V
ns
OSCILLATOR
200
Switching Frequency Range
1200
kHz
ZCD COMPARATOR
Offset Accuracy (Note 8)
Referred to VCSP − VCSN
www.onsemi.com
12
±1.5
mV
NCP81248
Table 6. ELECTRICAL CHARACTERISTICS – SINGLE PHASE REGULATORS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF
unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TA ≤ 100°C unless noted otherwise, and are
guaranteed by test, design or statistical correlation.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
430
mV
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Threshold
Absolute Over Voltage Threshold
VOVP1
VVSP – VVSN – VID rising
CSN voltage during soft−start
2
V
Over Voltage Delay (Note 8)
VVSP rising to PWM low
25
ns
Over Voltage VR_RDY Delay (Note 8)
VVSP rising to VR_RDY low
350
ns
Under Voltage Threshold
VOVABS1
365
VUVM1
VVSP − VVSN – VID falling
−400
Under−voltage Hysteresis (Note 8)
Under−voltage Blanking Delay (Note 8)
VVSP – VVSN falling to VR_RDY
falling
−295
400
mV
25
mV
5
ms
TSENSE_1ph
Alert# Assert Threshold
25°C to 100°C
490
mV
Alert# De−assert Threshold
25°C to 100°C
502
mV
VRHOT Assert Threshold
25°C to 100°C
476
mV
VRHOT Rising Threshold
25°C to 100°C
480
mV
Bias Current
25°C to 100°C
116
120
124
mA
Applied only after enabling, and
prior to soft−start.
9.53
9.98
10.33
mA
9.53
9.94
10.33
mA
ICCMAX PINS
Bias Current (Note 8)
IMXBIAS1A
IMXBIAS1B
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design or characterization data. Not tested in production.
www.onsemi.com
13
NCP81248
General Information
The table below specifies the ADDR_VBOOT pin
pulldown resistor (1% tolerance required) needed to
program all possible supply rail configurations. Four boot
voltages are available for all rails except for the SA rail.
The NCP81248 is a three−rail IMVP8 controller with an
Intel proprietary control interface.
Serial VID interface (Intel proprietary interface)
For Intel proprietary interface communication details
please contact Intel®, Inc.
RAIL CONFIGURATION TABLE
SYSTEM RAIL
ADDR_VBOOT
Resistance
PHASE
COUNT
10k
Rail1
Rail2
TSENSE
_1PH
TSENSE
_2PH
a/b
Boot
Voltage
PHASE
COUNT
1
a
0V
16.2k
1
a
22.1k
1
28.7k
1
ADDR_VBOOT
Resistance
PHASE
COUNT
Rail3
Boot
Voltage
PHASE
COUNT
a/b
Boot
Voltage
2 or 1
0V
1
b
1.05 V
1.2 V
2 or 1
1.2 V
1
b
a
1.05 V
2 or 1
1.05 V
1
b
a
1.0 V
2 or 1
1.0 V
1
b
Rail1
Rail2
TSENSE
_2PH
TSENSE
_1PH
Boot
Voltage
PHASE
COUNT
Boot
Voltage
PHASE
COUNT
a/b
35.7k
2 or 1
0V
1
a
0V
1
b
43.2k
2 or 1
1.2 V
1
a
1.2 V
1
b
51.1k
2 or 1
1.05 V
1
a
1.05 V
1
b
61.9k
2 or 1
1.0 V
1
a
1.0 V
1
b
ADDR_VBOOT
Resistance
PHASE
COUNT
Rail2
TSENSE
_1PH
TSENSE
_2PH
a/b
Boot
Voltage
PHASE
COUNT
Boot
Voltage
PHASE
COUNT
a/b
1
b
0V
2 or 1
0V
1
a
82.5k
1
b
1.2 V
2 or 1
1.2 V
1
a
95.3k
1
b
1.05 V
2 or 1
1.05 V
1
a
110k
1
b
1.0 V
2 or 1
1.0 V
1
a
ADDR_VBOOT
Resistance
PHASE
COUNT
127k
Rail1
Rail2
TSENSE
_2PH
a/b
Boot
Voltage
PHASE
COUNT
1
b
0V
143k
1
b
165k
1
187k
1
Boot
Voltage
1.05 V
2+1+1
Rail1+Rail2+R
ail3
Boot
Voltage
1.05 V
Configuration
1+2+1
Rail3+Rail2+R
ail1
Rail4
Boot
Voltage
PHASE
COUNT
2 or 1
0V
1.2 V
2 or 1
b
1.05 V
b
1.0 V
TSENSE
_1PH
a/b
Boot
Voltage
1
a
0V
1.2 V
1
a
1.2 V
2 or 1
1.05 V
1
a
1.05 V
2 or 1
1.0 V
1
a
1.0 V
www.onsemi.com
14
Configuration
Rail3
71.5k
TSENSE
PSYS
1+2+1
Rail1+Rail2+R
ail3
Rail3
a/b
Rail1
Configuration
Configuration
1+2+1
Rail1+Rail2+R
ail4
NCP81248
Start Up
the gate drivers. A digital counter steps the DAC up from
zero to the target voltage based on the Soft Start Slew Rate
in the spec table. As the DAC ramps, the PWM outputs of
each rail will change from Mid−level to high when the first
PWM pulse for that rail is produced. When the controller is
disabled, the PWM signals return to Mid−level.
Following the rise of VCC above the UVLO threshold,
externally programmed configuration data is collected, and
the PWM outputs are set to Mid−level to prepare the gate
drivers of the power stages for activation. When the
controller is enabled, DRVON is asserted (high) to activate
DRVON
Figure 7.
Phase Count, Rail Disabling & PSYS Disabling
Detection Sequence
Also, whether or not the PSYS function is active and
responds to an address call on the Intel proprietary interface
bus is determined by the internal circuitry monitoring the
PSYS input. Tying the PSYS input to VCC will cause the
NCP81248 to not respond to any calls to address 0Dh on the
Intel proprietary interface bus.
During start−up, the number of operational phases of the
2−phase rail, and whether or not each single−phase rail
becomes active and responds to an address call on the Intel
proprietary interface bus, is determined by the internal
circuitry monitoring the CSP inputs. Normally, the 2−phase
rail operates with both phases. If CSP2_2ph is externally
pulled to VCC with a resistor during startup, the two−phase
rail operates as a single−phase rail, and does not use
PWM2_2ph and CSP2_2ph. Likewise, if CSP of either or
both single−phase rails is pulled to VCC during startup, it is
disabled and will not respond to any address calls on the Intel
proprietary interface bus.
Switching Frequency
Switching frequencies between 200 kHz and 1.2 MHz are
programmed at startup with pulldown resistors on pins 14
and 15. The 1a and 2−phase regulators are programmed to
the same switching frequency by the pin 14 resistor, and the
Rail3 or Rail1 (usually the 1b regulator) is programmed by
the pin 15 resistor.
www.onsemi.com
15
NCP81248
Figure 8. Switching Frequency vs. ROSC Resistance
Input Voltage Feed−Forward (VRAMP pin)
The Rail1/Rail2 oscillator serves as the master clock for
the 2−phase rail ramp generator when configured for
2−phase operation, and as a frequency stabilization clock for
a single phase rail and for the 2−phase rail when it is
configured for single phase operation. The SA/US oscillator
serves as a frequency stabilization clock for the Rail3.
The formulas to calculate the switching frequency and
programming resistances are:
R OSC + 2 * 10 )11 * Frequency −1.192 [ W]
Frequency + 3 * 10 )9 * Frequency −0.838 [Hz]
Ramp generator circuits are provided for both the
dual−edge modulator (only when 2−phases are operating)
and three RPM modulators. The ramp generators implement
input voltage feed−forward control by varying the ramp
slopes proportional to the VRMP pin voltage. The VRMP
pin also has a 4 V UVLO function, which is active only after
the controller is enabled. The VRMP pin is high impedance
input when the controller is disabled.
For 2−phase operation, the dual−edge PWM ramp
amplitude is changed according to the following,
(eq. 1)
(eq. 2)
V RAMP_pp + 0.1 * V VRMP
Vin
Vramp_pp
Comp−IL
Duty
Figure 9.
www.onsemi.com
16
(eq. 3)
NCP81248
Interleaving
Ultrasonic Mode
In order to minimize stress on the input voltage and
simplify input filter design, the NCP81248 monitors the
phase−angle relationship between the rails. Small
adjustments are made to keep phases of both rails from
turning on at the same time. But if a phase must turn on to
respond to a sudden load increase, it will do so even if the
other rail has a phase that is turned on. This feature is
intended to reduce loading on the input supply during
steady−state conditions. If either rail is operating in DCM
mode, this feature is disabled.
The switching frequency of a rail in DCM will decrease
at very light loads. Ultrasonic Mode forces the switching
frequency to stay above the audible range.
Two−Phase Rail Remote Sense Amplifier
A high performance high input impedance true
differential amplifier is provided to accurately sense
regulator output voltage. The VSP and VSN inputs should
be connected to the regulator’s output voltage sense points.
The remote sense amplifier takes the difference of the output
voltage with the DAC voltage and adds the droop voltage.
V DIFFOUT + ǒV VSP * V VSNǓ ) ǒ1.3 V * V DACǓ
Programming Two−Phase Rail ICC_MAX
A resistor to ground on the ICCMAX_2ph pin programs
the register for the 2−phase rail at the time the part is enabled.
Current IMXBIAS2 is sourced from this pin to generate a
voltage on the program resistor. The resistor value should be
no less than 10k.
ICC_MAX 21h +
R * I MXBIAS2 * 128 A
) ǒV DROOP * V CSREFǓ
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier.
Two−phase Rail Voltage Compensation
(eq. 4)
2V
The Remote Sense Amplifier output feeds a Type III
compensation network formed by the Error Amplifier and
external tuning components. The non−inverting input of the
error amplifier is connected to the same reference voltage
used to bias the Remote Sense Amplifier output.
Programming TSENSE
Two temperature sense inputs are provided – one for the
2−phase rail, and the other for single−phase rail 1a. A
precision current is sourced out the output of the TSENSE
pins to generate a voltage on the temperature sense
networks. The voltages on the temperature sense inputs are
sampled by the internal A/D converter. A 100k NTC similar
to the Murata NCP15WF104E03RC should be used.
Rcomp1 in the following Figure is optional, and can be used
to slightly change the hysteresis. See the specification table
for the thermal sensing voltage thresholds and source
current.
TSENSE
Figure 11.
Two−Phase Rail Differential Current Feedback
Amplifiers
Rcomp1
0.0
Each phase of the two−phase rail has a low offset,
differential amplifier to sense the current of that phase in
order to balance current. The CSREF and CSPx pins are high
impedance inputs, but it is recommended that any external
filter resistor RCSN does not exceed 10 kW to avoid offset
due to leakage current. It is also recommended that the
voltage sense element be no less than 0.5 mW for best
current balance. The external filter RCSN and CCSN time
constant should match the inductor L/DCR time constant,
but fine tuning of this time constant is generally not required.
Phase current signals are summed with the COMP or ramp
signals at their respective PWM comparator inputs in order
to balance phase currents via a current mode control
approach.
Cfilter
0.1uF
Rcomp2
8.2k
AGND
(eq. 5)
RNTC
100k
AGND
Figure 10.
www.onsemi.com
17
NCP81248
RCSN
CSNx
CSPx
Two−Phase Rail Total Current Sense Amplifier
CCSN
SWNx
The NCP81248 uses a patented approach to sum the phase
currents into a single, temperature compensated, total
current signal. This signal is then used to generate the output
voltage droop, total current limit, and the output current
monitoring functions. The Rref(n) resistors average the
voltages at the output terminals of the inductors to create a
low impedance reference voltage at CSREF. The Rph
resistors sum currents from the switchnodes to the virtual
CSREF potential created at the CSSUM pin by the amplifier.
The total current signal is the difference between the
CSCOMP and CSREF voltages. The amplifier filters, and
amplifies, the voltage across the inductors in order to extract
only the voltage across the inductor series resistances
(DCR). An NTC thermistor (Rth) in the feedback network
placed near the Phase 1 inductor senses the inductor
temperature, and compensates both the DC gain and the
filter time constant for the change in DCR with temperature.
The Phase 1 inductor is chosen for the thermistor location so
that the temperature of the inductor providing current in the
PS1 power mode.
VOUT
DCR
LPHASE
1
R CSN +
2
L PHASE
C CSN * DCR
[W]
Figure 12.
Rth
Rcs2
Ccs2
Ccs1
SWN1
SWN2
Rph1
Rph2
CSN1
CSN2
Rcs1
_
CSSUM
CSREF
CONTROLLER
CSCOMP
+
to Remote
Sense Amplifier
Rref1
buffer
Rref2
ILIM
Cref
Rilim
IOUT
Current
Mirror
Current Limit
Comparators
Riout
Figure 13.
proportional to inductor current. Connecting Ccs2 in
parallel with Ccs1 allows fine tuning of the pole frequency
using commonly available capacitor values. It is best to
perform fine tuning during transient testing.
The DC gain equation for the DC total current signal is:
R CS2 )
V CSCOMP−CSREF +
R
R
CS1
CS1
Rph
*Rth
)Rth
(eq. 6)
* ǒIout Total * DCRǓ
Set the DC gain by adjusting the value of the Rph resistors
in order to make the ratio of total current signal to output
current equal the desired loadline.
The values of Rcs1 and Rcs2 are set based on the effect of
temperature on both the thermistor and inductor, and may
need to be adjusted to eliminate output voltage temperature
drift with the final product enclosure and cooling.
The pole frequency of the CSCOMP filter should be set
equal to the zero of the output inductor. This causes the total
current signal to contain only the component of inductor
voltage caused by the DCR voltage, and therefore to be
FZ +
FP +
DCR@25C
2 * p * L Phase
[Hz]
(eq. 8)
1
2 * p * ǒRcs2 )
(eq. 7)
Ǔ(Ccs1 ) Ccs2)
Rcs1)Rth@25C
[Hz]
Rcs1*Rth@25C
The value of the CREF capacitor (in nF) on the CSREF pin
should be:
C REF +
www.onsemi.com
18
0.02 * R PH
R REF
[nF]
(eq. 9)
NCP81248
Two−Phase Rail Loadline Programming (DROOP)
Two−Phase Rail Programming IOUT
An output loadline is a power supply characteristic
wherein the regulated (DC) output voltage decreases
proportional to load current. This characteristic can reduce
the output capacitance required to maintain output voltage
within limits during load transients faster than those to
which the regulation loop can respond. In the NCP81248, a
loadline is produced by adding a signal proportional to
output load current (VDROOP) to the output voltage feedback
signal – thereby satisfying the voltage regulator at an output
voltage reduced proportional to load current.
The loadline is programmed by setting the gain of the
Total Current Sense Amplifier such that the total current
signal is equal to the desired output voltage droop.
The IOUT pin sources a current proportional to the ILIM
current. The voltage on the IOUT pin is monitored by the
internal A/D converter and should be scaled with an external
resistor to ground such that a load equal to ICCMAX
generates a 2 V signal on IOUT. A pull−up resistor from 5 V
VCC can be used to offset the IOUT signal positive if desired.
R LIMIT +
(eq. 11)
[W]
* ǒIout ICC_MAX * DCRǓ
Two−Phase Rail Programming DAC Feed−Forward
Filter
The NCP81248 outputs a pulse of current from the VSN
pin upon each increment of the internal DAC following a
DVID UP command. A parallel RC network inserted into
the path from VSN to the output voltage return sense
point, VSS_SENSE, causes these current pulses to
temporarily decrease the voltage between VSP and VSN.
This causes the output voltage during DVID to be regulated
slightly higher, in order to compensate for the response of
the Droop function to current flowing into the charging
output capacitors. In the following equations, Cout is the
total output capacitance of the system.
The current limit thresholds are programmed with a
resistor between the ILIM and CSCOMP pins. The
NCP81248 generates a replica of the CSREF pin voltage at
the ILIM pin, and compares ILIM pin current to ICL0 and
ICLM0. The NCP81248 latches off if ILIM pin current
exceeds ICL0 (ICL1 for PS1, PS2, and PS3) for tOCPDLY, and
latches off immediately if ILIM pin current exceeds ICLM0
(ICLM1 for PS1, PS2 and PS3). Set the value of the current
limit resistor RLIMIT according to the desired current limit
IoutLIMIT.
Rcs1*Rth
Rcs1)Rth
Rph
Rcs1*Rth
Rcs1)Rth
Rph
Rcs2)
10 *
Two−Phase Rail Programming the Current Limit
Rcs2)
2.0 V * R LIMIT
R IOUT +
* ǒIout LIMIT * DCRǓ
(eq. 10)
10m
VCC_SENSE
VSP
VSS_SENSE
VSN
+
_
REMOTE SENSE
AMPLIFIER
RFF
CONTROLLER
+_
CFF
DVID UP
INCREMENT
CURRENT
PULSES
DAC
DAC
VSN
Figure 14.
R FF +
Loadline * Cout
9.35 * 10 −10
C FF +
200
R FF
[nF]
[W]
Two−Phase Rail PWM Comparators
(eq. 12)
The noninverting input of each comparator (one for each
phase) is connected to the summation of the error amplifier
output (COMP) and each phase current (IL*DCR*Phase
Balance Gain Factor). The inverting input is connected to
the triangle ramp voltage of that phase. The output of the
comparator generates the PWM output.
(eq. 13)
www.onsemi.com
19
NCP81248
connected to the regulator’s output voltage sense points
through filter networks described in the Droop
Compensation and DAC Feedforward Compensation
sections. The remote sense error amplifier outputs a current
proportional to the difference between the VSP, VSN and
DAC voltages:
The main rail PWM pulses are centered on the valley of
the triangle ramp waveforms and both edges of the PWM
signals are modulated. During a transient event, the duty
cycle can increase rapidly as the error amp signal increases
with respect to the ramps, to provide a highly linear and
proportional response to the step load.
I COMP + gm EA
Single−Phase Rails
The architecture of the two single−phase rails makes use
of a digitally enhanced, high performance, current mode
RPM control method that provides excellent transient
response while minimizing transient aliasing. The average
operating frequency is digitally stabilized to remove
frequency drift under all continuous mode operating
conditions.
ƪV DAC * ǒV VSP * VVSNǓƫ
Single−phase rail voltage compensation
The Remote Sense Amplifier output current is applied to
a standard Type II compensation network formed by
external tuning components CLF, RZ and CHF.
DAC
gm
Features of the single−phase rails
• Supports Intel proprietary interface Addresses 00, 01,
•
•
•
•
•
•
•
•
•
02, 03
Adjustable Vboot
Programmable Slew Rate
Dynamic VID Feed−Forward
High performance RPM control system
Programmable Droop Gain (Zero Droop Capable)
Low Offset IOUT monitor
Thermal Monitor
Digitally Controlled Operating Frequency
UltraSonic Operation
VSN
VSN
VSP
VSP
COMP
RZ
CHF
CLF
Figure 15.
Single−phase Rail − Programming the DAC
Feed−Forward Filter
The DAC feed−forward implementation for the
single−phase rail is the same as for the 2−phase rail. The
NCP81248 outputs a pulse of current from the VSN pin upon
each increment of the internal DAC following a DVID UP
command. A parallel RC network inserted into the path from
VSN to the output voltage return sense point, VSS_SENSE,
causes these current pulses to temporarily decrease the
voltage between VSP and VSN. This causes the output
voltage during DVID to be regulated slightly higher, in order
to compensate for the Droop function response to inductor
current flowing into the charging output capacitors. RFFSP
sets the gain of the DAC feed−forward and CFFSP provides
the time constant to cancel the time constant of the system
per the following equations. Cout is the total output
capacitance of the system.
Single−phase Rail Frequency Programming
One of the two single−phase rails has frequency
programmed by the ROSC_COREGT pin, and the other has
frequency programmed by the ROSC_SAUS pin.
ROSC_COREGT always controls the frequency of the
Rail1 and Rail2 unless there are two Rail2. In that case,
ROSC_COREGT controls the frequency of both Rail2, and
ROSC_SAUS controls the frequency of the Rail1.
Single−phase Rail Remote Sense Error Amplifier
A high performance, high input impedance, differential
transconductance amplifier is provided to accurately sense
the regulator output voltage and provide high bandwidth
transient performance. The VSP and VSN inputs should be
DAC
FEED−
FORWARD
FROM SVID
INTERFACE
(eq. 14)
DAC FEEDFORWARD
CURRENT
CFFSP
TO
VSS_SENSE
DAC
DAC
gm
VSN
VSN
VSP
VSP
RFFSP
CSNSSP
Figure 16.
R FFSP +
Loadline * Cout
1.35 * 10 −9
[W]
C FFSP +
(eq. 15)
www.onsemi.com
20
200
R FFSP
[nF]
(eq. 16)
NCP81248
Single−phase Rail – Differential Current Feedback
Amplifier
inductor, and may need to be adjusted to eliminate output
voltage temperature drift with the final product enclosure
and cooling.. The CSP and CSN pins are high impedance
inputs, but it is recommended that the lowpass filter
resistance not exceed 10 kW in order to avoid offset due to
leakage current. It is also recommended that the voltage
sense element (inductor DCR) be no less than 0.5 mW for
sufficient current accuracy. Recommended values for the
external filter components are:
Each single−phase controller has a low offset, differential
amplifier to sense output inductor current. An external
lowpass filter can be used to superimpose a reconstruction
of the AC inductor current onto the DC current signal sensed
across the inductor. To do this, the lowpass filter time
constant should match the inductor L/DCR time constant by
setting the filter pole frequency equal to the zero of the
output inductor. This makes the filter AC output mimic the
product of AC inductor current and DCR, with the same gain
as the filter DC output. It is best to perform fine tuning of the
filter pole during transient testing.
FZ +
DCR@25C
2*p*L
[Hz]
1
FP +
2*p*
R
PHSP
R
ǒ
* Rth)R
PHSP
CSSP
)Rth)R
Ǔ
CSSP
C CSSP +
R
ǒ
* Rth)R
PHSP
CSSP
)Rth)R
Ǔ
[F]
(eq. 19)
* DCR
CSSP
• RPHSP = 7.68 kW
• RCSSP = 14.3 kW
• Rth
= 100 kW, Beta = 4300
(eq. 18)
Using two parallel capacitors in the lowpass filter allows
fine tuning of the pole frequency using commonly available
capacitor values.
The DC gain equation for the current sense amplifier
output is:
* C CSSP
Forming the lowpass filter with an NTC thermistor (Rth)
placed near the output inductor, compensates both the DC
gain and the filter time constant for the inductor DCR change
with temperature. The values of RPHSP and RCSSP are set
based on the effect of temperature on both the thermistor and
V CURR +
Rth ) R CSSP
R PHSP ) Rth ) R CSSP
+
CURRENT
SENSE AMP
* Iout * DCR
(eq. 20)
RPHSP
CSP
Av=1
PHSP
R
(eq. 17)
[Hz]
L PHASE
CSN
RCSSP
_
CCSSP
t
TO
INDUCTOR
Rth
COMP
PWM
GENERATOR
CURR
Figure 17.
The amplifier output signal is combined with the COMP
and RAMP signals at the PWM comparator inputs to
produce the Ramp Pulse Modulation (RPM) PWM signal.
maintain output voltage within limits during load transients
faster than those to which the regulation loop can respond.
In the NCP81248, a loadline is produced by adding VDROOP
to the output voltage feedback signal – thereby satisfying the
voltage regulator at an output voltage reduced in proportion
to load current. VDROOP is developed across a resistance
between the VSP pin and the output voltage sense point by
forcing current from the VSP pin that is proportional to the
difference between the CSP and CSN voltages.
Single−phase Rail – Loadline Programming (DROOP)
An output loadline is a power supply characteristic
wherein the regulated (DC) output voltage decreases by a
voltage (VDROOP) proportional to load current. This
characteristic can reduce the output capacitance required to
www.onsemi.com
21
NCP81248
VSN
RDRPSP
VSP
VSP
CSNSSP
TO
VCC_SENSE
CDRPSP
gm
RCDRPSP
DROOP
CURRENT
RPHSP
CSP
+
CURRENT
SENSE AMP
Av=1
CSN
RCSSP
TO
INDUCTOR
t
_
CCSSP
Rth
Figure 18.
(eq. 21)
V DROOP + R DRPSP
I OUT
gm VSP
Single−phase Rail – Programming IOUT
Rth ) R CSSP
The IOUT pin sources a current proportional to the
voltage between the CSP and CSN pins. The voltage on the
IOUT pin is monitored by the internal A/D converter and
should be scaled with an external resistor to ground such that
a load equal to ICCMAX generates a 2 V signal on IOUT. A
high−value pull−up resistor from 5 V VCC can be used to
offset the IOUT signal positive if desired.
R PHSP ) Rth ) R CSSP
DCR
(eq. 22)
DCR
Rth ) R CSSP
Av=1
_
gm VSP
R PHSP ) Rth ) R CSSP
+
R DRPSP +
Loadline
[W]
RPHSP
CSP
CURRENT
SENSE AMP
CSN
RCSSP
t
CCSSP
gm
TO
INDUCTOR
Rth
IOUT
IOUT
CURRENT
MONITOR
RIOUTSP
Figure 19.
2V
R IOUTSP +
Rth)R
gm IOUT
R
CSSP
)Rth)R
PHSP
CSSP
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22
ICCMax
DCR
(eq. 23)
NCP81248
Programming the Single−Phase Rail ICC_MAX
inductor current (IL*DCR*Phase Current Gain Factor). The
PWM pulse ends when scaled inductor current added to a
compensating reset ramp exceeds the COMP voltage. Both
edges of the PWM signals are modulated. During a transient
event, the duty cycle can increase rapidly as the COMP
voltage increases with respect to the trigger threshold and
reset ramp, to provide a highly linear and proportional
response to the step load.
Resistors to ground on the ICCMAX_1a and
ICCMAX_1b pins program these registers for the single
phase rails at the time the part is enabled. IMXBIAS1A and
IMXBIAS1B currents are sourced from these pins to generate
a voltage on the program resistors. The resistor value should
be no less than 10k.
ICC_MAX 21h +
R * I MXBIAS1 * 64 A
(eq. 24)
2V
Disabling a Single−Phase Rail
If the NCP81248 is to provide fewer than three rails, either
or both of the single−phase regulators can be disabled by
pulling up their respective CSP pin to VCC. The two−phase
regulator cannot be disabled.
Single−phase Rail Pulsewidth Modulator
A PWM pulse starts when the Error Amp output (COMP
voltage) exceeds a trigger threshold including a scaled
PROTECTION FEATURES
Two−Phase Regulator Over Current Protection (OCP)
current mode, if the ILIM pin current exceeds ICL0, an
internal latch−off timer starts. If the fault is not removed, the
controller shuts down when the timer expires. If the current
into the pin exceeds ICLM0, the controller shuts down
immediately. When operating in PS1, PS2, or PS3, the ILIM
pin current limits are ICL1 and ICLM1. To recover from an
OCP fault, the EN pin or VCC voltage must be cycled low.
A programmable total phase current limit is provided that
is decreased when not operating in full current mode. This
limit is programmed with a resistor between the CSCOMP
and ILIM pins. The current from the ILIM pin to this resistor
is compared to the ILIM Threshold Currents (ICL0, ICLM0,
ICL1, and ICLM1). When the 2−phase rail is operating in full
Rth
Rcs2
Ccs2
Ccs1
SWN1
SWN2
Rph1
Rph2
CSN1
CSN2
Rcs1
_
CSSUM
CSREF
CONTROLLER
CSCOMP
+
to Remote
Sense Amplifier
Rref1
buffer
Rref2
ILIM
Cref
Rilim
IOUT
Current Limit
Comparators
Current
Mirror
Riout
Figure 20.
latches the single−phase rail off immediately if the ILIM pin
voltage exceeds the ILIM Threshold Voltage (VCL). Set the
value of the current limit resistor based on the equation
shown below.
Use Equation 10 to calculate the ILIM resistor value.
Single−phase Rail Over Current Protection (OCP)
The current limit threshold is programmed with a resistor
(RILIMSP) from the ILIM pin to ground. The current limit
www.onsemi.com
23
NCP81248
+
Av=1
RPHSP
CSP
CURRENT
SENSE AMP
CSN
RCSSP
_
CCSSP
gm
TO
INDUCTOR
t
Rth
ILIM
OVERCURRENT
PROGRAMMING
OVERCURRENT
COMPARATORS
OCP OCP REF
RILIMSP
CILIMSP
Figure 21.
V CL
R ILIMSP +
R
gm ILIM
R
)R
th
)R
PHSP
)R
th
C ILIMSP +
[W]
CSSP
Iout LIMIT
CSSP
5 * 10 )7
R ILIMSP
[pF]
(eq. 26)
If the CSN voltage falls more than VUVM1 below the DAC
voltage, the UVM comparator will trip – sending the
VR_RDY signal low.
A capacitor (CILIMSP) in parallel with the ILIM pin
resistor creates a time delay to give some tolerance for
output currents that momentarily exceed the current limit.
The CILIMSP value given in the equation below will give up
to a 50 ms delay with a 150% overload depending on the load
current prior to overload.
To recover from an OCP fault, the EN pin or VCC voltage
must be cycled low.
Output Over Voltage Protection
The 2−phase output voltage is monitored for OVP at the
output of the differential amplifier and also at the CSREF
pin. The single−phase regulator outputs are monitored for
overvoltage at the VSP & VSN inputs, and also at the CSN
inputs. During normal operation, if an output voltage
exceeds the DAC voltage by VOVP, the VR_RDY flag goes
low, and the DAC voltage of the overvoltage rail will be
slowly ramped down to 0 V to avoid producing a negative
output voltage. At the same time, the PWM outputs of the
overvoltage rail are sent low. The PWM output will pulse to
mid−level during the DAC ramp down period if the output
decreases below the DAC + OVP Threshold as DAC
decreases. When the DAC gets to zero, the PWMs will be
held low, and the NCP81248 will stay in this mode until the
VCC voltage or EN is toggled.
Input Under−voltage Lockouts (UVLO)
NCP81248 monitors the 5 V VCC supply as well as the
VRMP pin voltage. Hysteresis is incorporated within these
monitors.
Output Under Voltage Monitor
The 2−phase rail output voltage is monitored for
undervoltage at the output of the differential amplifier. If the
2−phase rail output falls more than VUVM2 below the
DAC−DROOP voltage, the UVM comparator will trip –
sending the VR_RDY signal low.The single−phase rail
outputs are monitored for undervoltage at the CSN inputs.
Vcc
UVLO RISING
2.0 V
(eq. 25)
DCR
OVP Threshold
DAC+~400mV
DAC
DRON
Figure 22. OVP Threshold Behavior
www.onsemi.com
24
NCP81248
2.0 V
OVP Threshold
Vout
DAC
DRON
PWM
Figure 23. OVP Behavior at Startup
During start up, the OVP threshold is set to the Absolute
Over Voltage Threshold. This allows the controller to start
up without false triggering OVP.
OVP Threshold
DAC
VSP_VSN
OVP
Triggered
Latch Off
PWM
Figure 24. OVP During Normal Operation Mode
www.onsemi.com
25
NCP81248
PIN 1
TYPICAL PCB LAYOUT
Top Layer
Bottom Layer viewed from top
Figure 25.
www.onsemi.com
26
NCP81248
PACKAGE DIMENSIONS
QFN48 6x6, 0.4P
CASE 485BA
ISSUE A
PIN ONE
LOCATION
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
L1
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
2X
EXPOSED Cu
TOP VIEW
0.10 C
A
(A3)
0.10 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉ
ÉÉ
0.10 C
2X
L
L
A B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MOLD CMPD
DETAIL B
DETAIL B
ALTERNATE
CONSTRUCTION
0.08 C
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.15
0.25
6.00 BSC
4.40
4.60
6.00 BSC
4.40
4.60
0.40 BSC
0.20 MIN
0.30
0.50
0.00
0.15
A1
NOTE 4
SIDE VIEW
C
D2
DETAIL A
SEATING
PLANE
SOLDERING FOOTPRINT*
K
6.40
4.66
13
48X
0.68
25
E2
48X
L
4.66
6.40
1
48
37
e
48X
e/2
BOTTOM VIEW
b
0.07 C A B
0.05 C
PKG
OUTLINE
NOTE 3
0.40
PITCH
48X
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP81248/D