AD AD8314ACP-REEL 100 mhz to 2.7 ghz, 45 db rf detector/controller Datasheet

100 MHz to 2.7 GHz, 45 dB
RF Detector/Controller
AD8314
For convenience, the signal is internally ac-coupled, using a
5 pF capacitor to a load of 3 kΩ in shunt with 2 pF. This highpass coupling, with a corner at approximately 16 MHz,
determines the lowest operating frequency. Therefore, the
source can be dc grounded.
FEATURES
Complete RF detector/controller function
Typical range:−58 dBV to −13 dBV
−45 dBm to 0 dBm, re 50 Ω
Frequency response from 100 MHz to 2.7 GHz
Temperature-stable linear-in-dB response
Accurate to 2.7 GHz
Rapid response: 70 ns to a 10 dB step
Low power: 12 mW at 2.7 V
Power down to 20 μA
The AD8314 provides two voltage outputs. The first, V_UP,
increases from close to ground to about 1.2 V as the input signal
level increases from 1.25 mV to 224 mV. This output is intended
for use in measurement mode. Consult the Applications section
for information on this mode. A capacitor can be connected
between the V_UP and FLTR pins when it is desirable to
increase the time interval over which averaging of the input
waveform occurs.
APPLICATIONS
Cellular handsets (TDMA, CDMA , GSM)
RSSI and TSSI for wireless terminal devices
Transmitter power measurement and control
The second output, V_DN, is an inversion of V_UP but with
twice the slope and offset by a fixed amount. This output starts
at about 2.25 V (provided the supply voltage is ≥3.3 V) for the
minimum input and falls to a value close to ground at the
maximum input. This output is intended for analog control
loop applications. A setpoint voltage is applied to VSET, and
V_DN is then used to control a VGA or power amplifier. Here
again, an external filter capacitor can be added to extend the
averaging time. Consult the Applications section for
information on this mode.
GENERAL DESCRIPTION
The AD8314 is a complete low cost subsystem for the
measurement and control of RF signals in the frequency range
of 100 MHz to 2.7 GHz, with a typical dynamic range of 45 dB,
intended for use in a wide variety of cellular handsets and other
wireless devices. It provides a wider dynamic range and better
accuracy than possible using discrete diode detectors. In
particular, its temperature stability is excellent over the full
operating range of −40°C to +85°C.
The AD8314 is available in 8-lead MSOP and 8-lead LFCSP
packages and consumes 4.5 mA from a 2.7 V to 5.5 V supply.
When powered down, the typical sleep current is 20 μA.
Its high sensitivity allows control at low power levels, thus
reducing the amount of power that needs to be coupled to the
detector. It is essentially a voltage-responding device, with a
typical signal range of 1.25 mV to 224 mV rms or –58 dBV to
−13 dBV. This is equivalent to −45 dBm to 0 dBm, re 50 Ω.
FUNCTIONAL BLOCK DIAGRAM
FLTR
V-I
VSET
–
+
DET
DET
DET
DET
–
OFFSET
COMPENSATION
10dB
10dB
AD8314
X2
V_DN
+
BAND GAP
REFERENCE
VPOS
ENBL
01086-001
10dB
V_UP
DET
RFIN
10dB
I-V
COMM
(PADDLE)
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8314
TABLE OF CONTENTS
Features .............................................................................................. 1
dBV vs. dBm ............................................................................... 13
Applications....................................................................................... 1
Filter Capacitor ........................................................................... 13
General Description ......................................................................... 1
Operating in Controller Mode ................................................. 13
Functional Block Diagram .............................................................. 1
Power-On and Enable Glitch .................................................... 14
Revision History ............................................................................... 2
Input Coupling Options ............................................................ 14
Specifications..................................................................................... 3
Increasing the Logarithmic Slope in Measurement Mode ... 15
Absolute Maximum Ratings............................................................ 4
Effect of Waveform Type on Intercept .................................... 15
ESD Caution.................................................................................. 4
Mobile Handset Power Control Examples.............................. 16
Pin Configurations and Function Descriptions............................ 5
Operation at 2.7 GHz................................................................. 18
Typical Performance Characteristics ............................................. 6
Using the LFCSP Package.......................................................... 18
Theory of Operation ...................................................................... 10
Evaluation Board ........................................................................ 18
Inverted Output .......................................................................... 11
Outline Dimensions ....................................................................... 20
Applications..................................................................................... 12
Ordering Guide .......................................................................... 20
Basic Connections ...................................................................... 12
Transfer Function in Terms of Slope and Intercept ............... 12
REVISION HISTORY
5/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Inserted Figure 3; Renumbered Sequentially................................ 5
Changes to Figure 4, Figure 5, Figure 6, Figure 7,
and Figure 8 ...................................................................................... 6
Changes to Figure 9, Figure 10, and Figure 12 ............................. 7
Changes to Figure 37...................................................................... 14
Changes to Table 5.......................................................................... 15
Changes to Figure 39...................................................................... 16
Changes to Table 7.......................................................................... 19
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
3/02—Rev. 0 to Rev. A
Edit to Product Description.............................................................1
Edit to Specifications.........................................................................2
Edit to Ordering Guide ....................................................................3
Edit to TPC 1......................................................................................4
New Section (Operation at 2.7 GHz) Added.............................. 14
Addition of New Figures 14 and 15 ............................................. 14
Changes to Evaluation Board Section.......................................... 14
Addition of Chip Scale Package.................................................... 16
Rev. B | Page 2 of 20
AD8314
SPECIFICATIONS
VS = 3 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range 1
Input Voltage Range
Equivalent Power Range
Logarithmic Slope
Logarithmic Intercept
Equivalent dBm Level
INPUT INTERFACE
DC Resistance to COMM
Inband Input Resistance
Input Capacitance
MAIN OUTPUT
Voltage Range
Minimum Output Voltage
Maximum Output Voltage 3
General Limit
Available Output Current
Response Time
Residual RF (at 2f )
INVERTED OUTPUT
Gain Referred to V_UP
Minimum Output Voltage
Maximum Output Voltage
Available Output Current
Output-Referred Noise
Response Time
Full-Scale Settling Time
SETPOINT INPUT
Voltage Range
Input Resistance
Logarithmic Scale Factor
ENABLE INTERFACE
Logic Level to Enable Power
Input Current when HI
Logic Level to Disable Power
POWER INTERFACE
Supply Voltage
Quiescent Current
Overtemperature
Total Supply Current when Disabled
Overtemperature
Conditions
Min
To meet all specifications
Internally ac-coupled
52.3 Ω external termination
Main output, V_UP, 100 MHz 2
Main output, V_UP, 100 MHz
52.3 Ω external termination
Pin RFIN
0.1
1.25
−45
18.85
−68
−55
f = 0.1 GHz
f = 0.1 GHz
Pin V_UP
V_UP connected to VSET
No signal at RFIN, RL ≥ 10 kΩ
RL ≥ 10 kΩ
2.7 V ≤ VS ≤ 5.5 V
Sourcing/sinking
10% to 90%, 10 dB step
f = 0.1 GHz (worst condition)
Pin V_DN
VDN = 2.25 V − 2 × VUP
VS ≥ 3.3 V
VS ≥ 3.3 V 4
Sourcing/sinking
RF input = 2 GHz, –33 dBV, fNOISE = 10 kHz
10% to 90%, 10 dB input step
−40 dBm to 0 dBm input step to 95%
Pin VSET
Corresponding to central 40 dB
f = 0.900 GHz
f = 1.900 GHz
Pin ENBL
HI condition, −40°C ≤ TA ≤ +85°C
2.7 V at ENBL, −40°C ≤ TA ≤ +85°C
LO condition, −40°C ≤ TA ≤ +85°C
Pin VPOS
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +85°C
1
For a discussion on operation at higher frequencies, see Applications section.
Mean and standard deviation specifications are available in Table 4.
3
Increased output possible when using an attenuator between V_UP and VSET to raise the slope.
4
Refer to Figure 22 for details.
2
Rev. B | Page 3 of 20
Typ
Max
Unit
21.3
−62
−49
2.5
224
0
23.35
−56
−43
GHz
mV rms
dBm
mV/dB
dBV
dBm
100
3
2
0.01
0.01
1.9
VS − 1.1
1/0.5
0.01
2.1
4/100
0.15
7
0.02
2
VS − 1
2/1
70
100
−2
0.05
2.2
6/200
1.05
70
150
1.2
0.05
V
V
V
V
mA
ns
μV
0.1
2.5
V
V
mA/μA
μV/√Hz
ns
ns
1.2
V
kΩ
mV/dB
mV/dB
VPOS
300
+0.8
V
μA
V
5.5
5.7
6.6
95
V
mA
mA
μA
μA
10
20.7
19.7
1.6
20
−0.5
2.7
3.0
2.7
kΩ
kΩ
pF
3.0
4.5
4.4
20
40
AD8314
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VPOS
V_UP, V_DN, VSET, ENBL
Input Voltage
Equivalent Power
Internal Power Dissipation
θJA (MSOP)
θJA (LFCSP, Paddle Soldered)
θJA (LFCSP, Paddle Not Soldered)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
8-Lead MSOP
8-Lead LFCSP
Value
5.5 V
0 V, VPOS
1.6 V rms
17 dBm
200 mW
200°C/W
80°C/W
200°C/W
125°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
300°C
240°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 4 of 20
AD8314
RFIN 1
AD8314
ENBL 2
TOP VIEW
(Not to Scale)
VSET 3
FLTR 4
8
VPOS
7
V_DN
6
V_UP
5
COMM
01086-002
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 2. RM-8 Pin Configuration
AD8314
7 V_DN
VSET 3
TOP VIEW
(Not to Scale)
5 V_UP
FLTR 4
5 COMM
01086-003
8 VPOS
RFIN 1
ENBL 2
Figure 3. CP-8-1 Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
RFIN
ENBL
VSET
FLTR
5
6
7
8
COMM
V_UP
V_DN
VPOS
Description
RF Input.
Connect Pin to VS for Normal Operation. Connect pin to ground for disable mode.
Setpoint Input for Operation in Controller Mode. To operate in detector mode connect VSET to V_UP.
Connection for an External Capacitor to Slow the Response of the Output. Capacitor is connected between
FLTR and V_UP.
Device Common (Ground)
Logarithmic Output. Output voltage increases with increasing input amplitude.
Inversion of V_UP, Governed by: V_DN = 2.25 V − 2 × VUP.
Positive Supply Voltage (VS), 2.7 V to 5.5 V.
Rev. B | Page 5 of 20
AD8314
TYPICAL PERFORMANCE CHARACTERISTICS
1.2
4
0.1GHz
3
1.0
2.5GHz
2
1.9GHz
0.6
2.5GHz
0.1GHz
1
ERROR (dB)
0.8
VUP (V)
1.9GHz
0.9GHz
0
–1
0.4
0.9GHz
–2
0.2
–65
–55
(–52dBm)
–45
–35
–25
INPUT AMPLITUDE (dBV)
–5
–15
(–2dBm)
–4
–70
01086-004
0
–75
–60
–50
(–47dBm)
Figure 4. VUP vs. Input Amplitude
–40
–30
–20
INPUT AMPLITUDE (dBV)
–10
0
(+3dBm)
01086-007
–3
Figure 7. Log Conformance vs. Input Amplitude
1.2
1.0
3
1.2
3
2
1.0
2
1
0.8
0
+25°C
0.4
SLOPE AND INTERCEPT
NORMALIZED AT +25°C AND
APPLIED TO –40°C AND +85°C
0.2
0
–70
–60
(–47dBm)
–50
–40
–30
–20
INPUT AMPLITUDE (dBV)
–10
0
+25°C
0.6
0.4
–2
0.2
(+3dBm)
0
–40°C
–1
–3
1
0
–70
ERROR (dB)
–40°C
0.6
+85°C
–1
–2
SLOPE AND INTERCEPT
NORMALIZED AT +25°C AND
APPLIED TO –40°C AND +85°C
–60
–50
(–47dBm)
–40
–30
–20
INPUT AMPLITUDE (dBV)
–10
0
–3
01086-008
+85°C
VUP (V)
VUP (V)
–40°C
01086-005
0.8
ERROR (dB)
+25°C
(+3dBm)
Figure 5. VUP and Log Conformance vs. Input Amplitude at 0.1 GHz;
−40°C, +25°C, and +85°C
Figure 8. VUP and Log Conformance vs. Input Amplitude at 1.9 GHz;
−40°C, +25°C, and +85°C
1.2
3
1.2
3
2
1.0
2
1
0.8
1.0
+25°C
0.4
0.2
0
–70
SLOPE AND INTERCEPT
NORMALIZED AT +25°C AND
APPLIED TO –40°C AND +85°C
–60
(–47dBm)
–50
–40
–30
–20
INPUT AMPLITUDE (dBV)
–10
0
–2
0.2
Figure 6. VUP and Log Conformance vs. Input Amplitude at 0.9 GHz;
−40°C, +25°C, and +85°C
0
–70
ERROR (dB)
0
–40°C
0.4
(+3dBm)
+25°C
0.6
–1
–3
1
–1
–2
SLOPE AND INTERCEPT
NORMALIZED AT +25°C AND
APPLIED TO –40°C AND +85°C
–60
(–47dBm)
–50
–40
–30
–20
INPUT AMPLITUDE (dBV)
–10
0
–3
(+3dBm)
Figure 9. VUP and Log Conformance vs. Input Amplitude at 2.5 GHz;
−40°C, +25°C, and +85°C
Rev. B | Page 6 of 20
01086-009
0
–40°C
VUP (V)
0.6
+85°C
+85°C
ERROR (dB)
VUP (V)
+85°C
01086-006
0.8
AD8314
23
–55
–40°C
–40°C
–60
VUP INTERCEPT (dBV)
VUP SLOPE (mV/dB)
22
21
+25°C
20
+85°C
+25°C
–65
+85°C
–70
0.5
0
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
–75
01086-010
18
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
Figure 10. Slope vs. Frequency; −40°C, +25°C, and +85°C
Figure 13. VUP Intercept vs. Frequency; −40°C, +25°C, and +85°C
22
–61
VUP INTERCEPT (dBV)
21
0.9GHz
20
0.1GHz
–62
0.1GHz
VUP SLOPE (mV/dB)
0.5
0
01086-013
19
1.9GHz
2.5GHz
–63
0.9GHz
–64
–65
–66
2.5GHz
4.0
4.5
5.0
5.5
VS (V)
3.5
4.0
4.5
5.0
5.5
2.6
VS (V)
Figure 11. VUP Slope vs. Supply Voltage
3500
3.0
01086-014
3.5
01086-015
3.0
1.9GHz
–67
2.5
01086-011
19
2.5
Figure 14. VUP Intercept vs. Supply Voltage
0
6
–200
5
FREQUENCY (GHz)
0.1
0.9
1.9
2.5
2000
1500
–600
–800
X
R
1000
–1000
R
500
0
–400
–1200
0
0.5
1.0
1.5
FREQUENCY (GHz)
2.0
–1400
2.5
4
DECREASING
VENBL
3
INCREASING
VENBL
2
1
0
01086-012
RESISTANCE (Ω)
2500
R || - jXΩ
3030 || - j748Ω
760 || - j106Ω
301 || - j80Ω
90 || - j141Ω
REACTANCE (Ω)
3000
SUPPLY CURRENT (mA)
X
Figure 12. Input Impedance
–1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
VENBL (V)
Figure 15. Supply Current vs. ENBL Voltage, VS = 3 V
Rev. B | Page 7 of 20
AD8314
AVERAGE: 128 SAMPLES
AVERAGE: 128 SAMPLES
VDN 1V/VERTICAL
DIVISION
VDN 500mV/VERTICAL
DIVISION
VDN GND
GND
1µs PER
HORIZONTAL
DIVISION
PULSED RF
0.1GHz, –13dBV
GND
5V PER VERTICAL DIVISION
Figure 19. VUP and VDN Response Time, −40 dBm to 0 dBm
Figure 16. ENBL Response Time
HP8648B
SIGNAL
GENERATOR
–33dBV
EXT TRIG
10MHz REF OUTPUT
RF OUT
HP8116A
PULSE
GENERATOR
TRIG
OUT
HP8648B
SIGNAL
GENERATOR
PULSE
MODULATION
MODE
PULSE OUT
52.3Ω
1 RFIN
VPOS 8
2 ENBL
V_DN 7
TEK P6204
FET PROBE
TEK P6204
FET PROBE
V_UP 6
3 VSET
OUT
VPOS 8
52.3Ω
3.0V
2 ENBL
V_DN 7
AD8314
COMM 5
NC = NO CONNECT
TRIG
OUT
3.0V
0.1µF
1 RFIN
TEK
TDS784C
SCOPE
PICOSECOND
PULSE LABS
PULSE
GENERATOR
TEK P6204
FET PROBE
–3dB
01086-017
NC 4 FLTR
RF
SPLITTER
TRIG
AD8314
PULSE MODE IN
RF OUT
–3dB
3.0V
0.1µF
EXT TRIG
10MHz REF OUTPUT
3 VSET
V_UP 6
NC 4 FLTR
COMM 5
TRIG
TEK P6204
FET PROBE
TEK P6204
FET PROBE
TEK
TDS784C
SCOPE
01086-020
VENBL GND
100ns PER
HORIZONTAL
DIVISION
200mV PER
VERTICAL
DIVISION
01086-016
VENBL
RF INPUT
01086-019
VUP 500mV/VERTICAL DIVISION
VUP GND
VUP 500mV/
VERTICAL
DIVISION
NC = NO CONNECT
Figure 20. Text Setup for Pulse Response
1k
10k
100k
1M
FREQUENCY (Hz)
10
NOISE SPECTRAL DENSITY (µV/√Hz)
RF INPUT
–70dBm
–50dBm
–40dBm
1
–60dBm
–20dBm
–30dBm
0.1
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 21. VDN Noise Spectral Density
Figure 18. AC Response from VSET to V_DN
Rev. B | Page 8 of 20
10M
01086-021
100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
10M
PHASE (Degrees)
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
–5
10
01086-018
AMPLITUDE (dB)
Figure 17. Test Setup for ENBL Response Time
AD8314
2.3
2mA
2.2
SHADING INDICATES
±3 SIGMA
4mA
2.1
VDN (V)
2.0
6mA
2.0
1.9
1.9
1.8
1.8
2.8
2.9
3.0
3.1
3.2
3.3
3.4
1.7
2.7
01086-022
1.7
2.7
3.5
VS (V)
2.8
2.9
VUP 500mV/VERTICAL
DIVISION
VPOS AND ENABLE
2V PER
VERTICAL
DIVISION
EXT TRIG
RF OUT
1 RFIN
VPOS 8
732Ω
2 ENBL
V_DN 7
TEK P6204
FET PROBE
AD8314
3 VSET
V_UP 6
NC 4 FLTR
COMM 5
TEK P6204
FET PROBE
10MHz REF OUTPUT
EXT TRIG
PULSE
OUT
AD811
49.9Ω
TRIG
52.3Ω
TEK
TDS784C
SCOPE
NC = NO CONNECT
1 RFIN
VPOS 8
732Ω
2 ENBL
V_DN 7
TEK P6204
FET PROBE
AD8314
0.2
3 VSET
NC 4 FLTR
Figure 24. Test Setup for Power-On and Power-Off Response
TRIG
OUT
HP8112A
PULSE
GENERATOR
RF OUT
01086-024
52.3Ω
HP8648B
SIGNAL
GENERATOR
PULSE
OUT
AD811
01086-026
Figure 26. Power-On Response, VDN, Controller Mode with VSET Held Low
TRIG
OUT
HP8116A
PULSE
GENERATOR
100ns PER
HORIZONTAL
DIVISION
2V PER
VERTICAL
DIVISION
GND
01086-023
1µs PER
HORIZONTAL
DIVISION
Figure 23. Power-On and Power-Off Response, Measurement Mode
10MHz REF OUTPUT
3.5
VDN
VDN GND
GND
3.4
200mV PER
VERTICAL
DIVISION
VDN GND
VPOS AND ENABLE
3.3
AVERAGE: 128 SAMPLES
VUP 500mV/VERTICAL
DIVISION
VUP GND
3.2
Figure 25. Maximum VDN Voltage vs. VS with 3 mA Load
AVERAGE: 128 SAMPLES
VUP
–33dBV
3.1
VS (V)
Figure 22. Maximum VDN Voltage vs. VS by Load Current
HP8648B
SIGNAL
GENERATOR
3.0
V_UP 6 NC
49.9Ω
TRIG
TEK
TDS784C
SCOPE
COMM 5
NC = NO CONNECT
Figure 27. Test Setup for Power-On Response at V_DN Output,
Controller Mode with VSET Pin Held Low
Rev. B | Page 9 of 20
01086-027
2.1
01086-025
2.2
VDN (V)
2.3
0mA
AD8314
THEORY OF OPERATION
The AD8314 is a logarithmic amplifier (log amp) similar in
design to the AD8313; further details about the structure and
function can be found in the AD8313 data sheet and other log
amps produced by ADI. Figure 28 shows the main features of
the AD8314 in block schematic form.
However, in using this part, it must be understood that log
amps do not fundamentally respond to power. It is for this
reason the dBV is used (decibels above 1 V rms) rather than the
commonly used metric of dBm. While the dBV scaling is fixed,
independent of termination impedance, the corresponding
power level is not. For example, 224 mV rms is always −13 dBV
(with one further condition of an assumed sinusoidal waveform;
see the Applications section for more information on the effect
of waveform on logarithmic intercept), and it corresponds to a
power of 0 dBm when the net impedance at the input is 50 Ω.
When this impedance is altered to 200 Ω, the same voltage
clearly represents a power level that is four times smaller
(P = V2/R), that is, −6 dBm. Note that dBV can be converted to
dBm for the special case of a 50 Ω system by simply adding
13 dB (0 dBV is equivalent to +13 dBm).
The AD8314 combines two key functions needed for the
measurement of signal level over a moderately wide dynamic
range. First, it provides the amplification needed to respond to
small signals, in a chain of four amplifier/limiter cells, each
having a small signal gain of 10 dB and a bandwidth of
approximately 3.5 GHz. At the output of each of these amplifier
stages is a full-wave rectifier, essentially a square-law detector
cell, that converts the RF signal voltages to a fluctuating current
having an average value that increases with signal level. A
further passive detector stage is added prior to the first stage.
Therefore, there are five detectors, each separated by 10 dB,
spanning some 50 dB of dynamic range. The overall accuracy at
the extremes of this total range, viewed as the deviation from an
ideal logarithmic response, that is, the law-conformance error,
can be judged by reference to Figure 7, which shows that errors
across the central 40 dB are moderate. Figure 5, Figure 6, Figure 8
through Figure 11, Figure 13, and Figure 14 show how the
conformance to an ideal logarithmic function varies with
supply voltage, temperature, and frequency.
Therefore, the external termination added prior to the AD8314
determines the effective power scaling. This often takes the
form of a simple resistor (52.3 Ω provides a net 50 Ω input),
but more elaborate matching networks can be used. This
impedance determines the logarithmic intercept, the input
power for which the output would cross the baseline (V_UP =
zero) if the function were continuous for all values of input.
Because this is never the case for a practical log amp, the
intercept refers to the value obtained by the minimum-error
straight-line fit to the actual graph of V_UP vs. PIN (more
generally, VIN). Again, keep in mind that the quoted values
assume a sinusoidal (CW) signal. Where there is complex
modulation, as in CDMA, the calibration of the power response
needs to be adjusted accordingly. Where a true power (waveformindependent) response is needed, the use of an rms-responding
detector, such as the AD8361, should be considered.
The output of these detector cells is in the form of a differential
current, making their summation a simple matter. It can easily
be shown that such summation closely approximates a logarithmic
function. This result is then converted to a voltage, at Pin V_UP,
through a high-gain stage. In measurement modes, this output
is connected back to a voltage-to-current (V-I) stage, in such a
manner that V_UP is a logarithmic measure of the RF input
voltage, with a slope and intercept controlled by the design. For
a fixed termination resistance at the input of the AD8314, a
given voltage corresponds to a certain power level.
FLTR
V-I
VSET
–
+
DET
DET
DET
DET
–
10dB
10dB
X2
V_DN
AD8314
+
BAND GAP
REFERENCE
VPOS
ENBL
01086-028
OFFSET
COMPENSATION
10dB
V_UP
DET
RFIN
10dB
I-V
COMM
(PADDLE)
Figure 28. Block Schematic
Rev. B | Page 10 of 20
AD8314
Table 4. Typical Specifications at Selected Frequencies at 25°C (Mean and Σ)
±1 dB Dynamic Range 1 (dBV)
Frequency (GHz)
0.1
0.9
1.9
2.5
Intercept (dBV)
μ
σ
High Point
μ
σ
Low Point
μ
σ
21.3
20.7
19.7
19.2
−62.2
−63.6
−66.3
−62.1
–11.8
–13.8
–19
–16.4
0.3
0.3
0.7
1.7
−59
−61.4
−64
−61
0.5
0.4
0.6
1.3
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.7
Refer to Figure 32.
V_UP
CURRENTS FROM
DETECTORS
I-V
V_DN
VDN = 2.25V – 2.0 × V_UP
FLTR
BAND GAP
REFERENCE
1.125V
Figure 29. Output Interfaces
2.5
OUTPUT FOR
PA CONTROL
2.0
INVERTED OUTPUT
V_DN
1.5
VOLTS
The second provision is the inclusion of an inverting amplifier
to the output, for use in controller applications. Most power
amplifiers require a gain-control bias that must decrease from a
large positive value toward ground level as the power output is
required to decrease. This control voltage, which appears at
Pin V_DN, is not only of the opposite polarity to V_UP, but also
needs to have an offset added to determine its most positive value
when the power level (assumed to be monitored through a
directional coupler at the output of the PA) is minimal.
VSET
V-I
AD8314
+2
+
01086-029
However, the logarithmic slope, the amount by which the
output V_UP changes for each decibel of input change (voltage
or power) is, in principle, independent of waveform or termination
impedance. In practice, it usually falls off somewhat at higher
frequencies, due to the declining gain of the amplifier stages
and other effects in the detector cells. For the AD8314, the slope
at low frequencies is nominally 21.3 mV/dB, falling almost
linearly with frequency to about 19.2 mV/dB at 2.5 GHz. These
values are sensibly independent of temperature (see Figure 10)
and almost totally unaffected by the supply voltage from 2.7 V
to 5.5 V (see Figure 11).
1.0
0.5
0
–60
OUTPUT FOR
MEASUREMENT
–50
–40
V_UP
–30
–20
–10
INPUT AMPLITUDE (dBV)
The starting value of V_DN is nominally 2.25 V, and it falls on a
slope of twice that of V_UP; in other words,−43 mV/dB. Figure 29
shows how this is achieved: the reference voltage that determines
the maximum output is derived from the on-chip voltage
reference and is substantially independent of the supply voltage
or temperature. However, the full output cannot be attained for
supply voltages under 3.3 V; Figure 22 shows this dependency.
The relationship between V_UP and V_DN is shown in Figure 30.
Rev. B | Page 11 of 20
Figure 30. Showing V_UP and V_DN Relationship
0
01086-030
1
Slope (mV/dB)
μ
σ
AD8314
APPLICATIONS
BASIC CONNECTIONS
Figure 31 shows connections for the basic measurement mode.
A supply voltage of 2.7 V to 5.5 V is required. The supply to the
VPOS pin should be decoupled with a low inductance 0.1 μF
surface-mount ceramic capacitor. A series resistor of about 10 Ω
can be added; this resistor slightly reduces the supply voltage to the
AD8314 (maximum current into the VPOS pin is approximately
9 mA when V_DN is delivering 5 mA). Its use should be
avoided in applications where the power supply voltage is very
low (that is, 2.7 V). A series inductor provides similar power
supply filtering with minimal drop in supply voltage.
While V_DN can deliver up to 6 mA, the load resistance on
V_UP should not be lower than 10 kΩ in order that the fullscale output of 1 V can be generated with the limited available
current of 200 μA maximum. Figure 32 shows the logarithmic
conformance under the same conditions.
1.2
3
VS = 3V
RT = 52.3Ω
VPOS 8
2 ENBL
V_DN 7
OPTIONAL
(SEE TEXT)
VS
VDN
AD8314
V_UP 6
4 FLTR
COMM 5
VUP
CF
OPTIONAL
(SEE TEXT)
01086-031
3 VSET
0.8
1
0.6
0
0.4
–1
0.2
Figure 31. Basic Connections for Operation in Measurement Mode
0
–70
The ENBL pin is here connected to VPOS. The AD8314 can be
disabled by pulling this pin to ground when the chip current is
reduced to about 20 μA from its normal value of 4.5 mA. The
logic threshold is around +VS/2 and the enable function occurs
in about 1.5 μs. Note, however, further settling time is generally
needed at low input levels.
The AD8314 has an internal input coupling capacitor. This
eliminates the need for external ac coupling. A broadband input
match is achieved in this example by connecting a 52.3 Ω resistor
between RFIN and ground. This resistance combines with the
internal input impedance of approximately 3 kΩ to give an
overall broadband input resistance of 50 Ω. Several other
coupling methods are possible, which are described in the
Input Coupling Options section.
The measurement mode is selected by connecting VSET to
V_UP, which establishes a feedback path and sets the
logarithmic slope to its nominal value. The peak voltage range
of the measurement extends from −58 dBV to −13 dBV at
0.9 GHz, and only slightly less at higher frequencies up to
2.5 GHz. Therefore, using the 50 Ω termination, the equivalent
power range is −45 dBm to 0 dBm. At a slope of 21.5 mV/dB,
this would amount to an output span of 967 mV. Figure 32
shows the transfer function for V_UP at a supply voltage of 3 V
and input frequency of 0.9 GHz.
–2
±3dB DYNAMIC RANGE
INTERCEPT
–60
(–47dBm)
–50
–40
–30
–20
INPUT AMPLITUDE (dBV)
ERROR (dB)
1 RFIN
2
±1dB DYNAMIC RANGE
–10
0
–3
(+3dBm)
01086-032
1.0
VUP (V)
VS
VDN = 2.25 V − 2 VUP
0.1µF
52.3Ω
INPUT
V_DN, which is generally not used when the AD8314 is used in
measurement mode, is essentially an inverted version of V_UP.
The voltage on V_UP and V_DN are related by
Figure 32. VUP and Log Conformance Error vs.
Input Level vs. Input Level at 900 MHz
TRANSFER FUNCTION IN TERMS OF SLOPE AND
INTERCEPT
The transfer function of the AD8314 is characterized in terms
of its slope and intercept. The logarithmic slope is defined as the
change in the RSSI output voltage for a 1 dB change at the input.
For the AD8314, slope is nominally 21.5 mV/dB. Therefore, a
10 dB change at the input results in a change at the output of
approximately 215 mV. Log conformance plot, Figure 32, shows
the range over which the device maintains its constant slope.
The dynamic range can be defined as the range over which the
error remains within a certain band, usually ±1 dB or ±3 dB. In
Figure 32 for example, the ±1 dB dynamic range is approximately
50 dB (from −13 dBV to −63 dBV).
Rev. B | Page 12 of 20
AD8314
VUP = VSLOPE × (PIN − PO)
where:
VUP is the demodulated and filtered RSSI output.
VSLOPE is the logarithmic slope, expressed in V/dB.
PIN is the input signal, expressed in decibels relative to some
reference level (either dBm or dBV in this case).
PO is the logarithmic intercept, expressed in decibels relative to
the same reference level.
For example, at an input level of −40 dBV (−27 dBm), the
output voltage is
VOUT = 0.020 V/dB × [−40 dBV − (−63 dBV)] = 0.46 V
OPERATING IN CONTROLLER MODE
Figure 33 shows the basic connections for operation in the
controller mode, and Figure 34 shows a block diagram of a
typical controller mode application. The feedback from V_UP
to VSET is broken and the desired setpoint voltage is applied to
VSET from the controlling source (often this is a DAC). VDN
rails high (2.2 V on a 3.3 V supply, and 1.9 V on a 2.7 V supply)
when the applied power is less than the value corresponding to
the setpoint voltage. When the input power slightly exceeds this
value, VDN would, in the absence of the loop via the power
amplifier gain pin, decrease rapidly toward ground. In the
closed loop, however, the reduction in VDN causes the power
amplifier to reduce its output. This restores a balance between
the actual power level sensed at the input of the AD8314 and
the demanded value determined by the setpoint. This assumes
that the gain control sense of the variable gain element is
positive, that is, an increasing voltage from V_DN tends to
increase gain. The output swing and current sourcing capability
of V_DN are shown in Figure 22 and Figure 25.
dBV VS. dBm
0.1µF
52.3Ω
INPUT
VS
1 RFIN
VPOS 8
VS
2 ENBL
V_DN 7
VDN
AD8314
VSET
3 VSET
V_UP 6
4 FLTR
COMM 5
CF
Figure 33. Basic Connections for Operation in Controller Mode
POWER
AMPLIFIER
RF INPUT
DIRECTIONAL
COUPLER
GAIN
CONTROL
VOLTAGE
CF
FILTER CAPACITOR
V_UP
The video bandwidth of both V_UP and V_DN is
approximately 3.5 MHz. In CW applications where the input
frequency is much higher than this, no further filtering of the
demodulated signal is required. Where there is a low frequency
modulation of the carrier amplitude, however, the low-pass
corner must be reduced by the addition of an external filter
capacitor, CF (see Figure 31). The video bandwidth is related
to CF by
Video Bandwidth =
01086-033
The most widely used convention in RF systems is to specify
power in dBm, that is, decibels above 1 mW in 50 Ω. Specification
of log amp input levels in terms of power is strictly a concession
to popular convention; they do not respond to power (tacitly
power absorbed at the input), but to the input voltage. The use
of dBV, defined as decibels with respect to a 1 V rms sine wave,
is more precise, although this is still not unambiguous because
waveform is also involved in the response of a log amp, which,
for a complex input (such as a CDMA signal), does not follow
the rms value exactly. Since most users specify RF signals in
terms of power (more specifically, in dBm/50 Ω), both dBV and
dBm are used in specifying the performance of the AD8314
showing equivalent dBm levels for the special case of a
50 Ω environment. Values in dBV are converted to
dBm re 50 Ω by adding 13.
1
2 π × 13 kΩ × (3.5 pF + C F )
FLTR
V_DN
VSET
DAC
AD8314
RFIN
52.3Ω
01086-034
The intercept is the point at which the extrapolated linear
response would intersect the horizontal axis (see Figure 32).
Using the slope and intercept, the output voltage can be
calculated for any input level within the specified input range by
Figure 34. Typical Controller Mode Application
The relationship between the input level and the setpoint
voltage follows from the nominal transfer function of the device
(VUP vs. input amplitude, see Figure 4). For example, a voltage of
1 V on VSET demands a power level of 0 dBm at RFIN. The
corresponding power level at the output of the power amplifier
is greater than this amount due to the attenuation through the
directional coupler.
Rev. B | Page 13 of 20
AD8314
As previously mentioned, the AD8314 can be put into a low
power mode by pulling the ENBL pin to ground. This reduces
the quiescent current from 4.5 mA to 20 μA. Alternatively, the
supply can be turned off to eliminate the quiescent current.
Figure 16 and Figure 26 show the behavior of the V_DN output
under these two conditions (in Figure 26, ENBL is tied to
VPOS). The glitch that results in both cases can be reduced by
loading the V_DN output.
INPUT COUPLING OPTIONS
The impedance matching characteristics of a reactive matching
network provide voltage gain ahead of the AD8314; this increases
the device sensitivity (see Table 5). The voltage gain is calculated by
Voltage GaindB = 20 log 10
R2
R1
where R2 is the input impedance of the AD8314, and R1 is the
source impedance to which the AD8314 is being matched. Note
that this gain is only achieved for a perfect match. Component
tolerances and the use of standard values tend to reduce gain.
The internal 5 pF coupling capacitor of the AD8314, along with
the low frequency input impedance of 3 kΩ, gives a high-pass
input corner frequency of approximately 16 MHz. This sets the
minimum operating frequency. Figure 35 through Figure 37
show three options for input coupling. A broadband resistive
match can be implemented by connecting a shunt resistor to
ground at RFIN (see Figure 35). This 52.3 Ω resistor (other
values can also be used to select different overall input
impedances) combines with the input impedance of the
AD8314 (3 kΩ||2 pF) to give a broadband input impedance of
50 Ω. While the input resistance and capacitance (CIN and
RIN) varies by approximately ±20% from device to device, the
dominance of the external shunt resistor means that the variation
in the overall input impedance is close to the tolerance of the
external resistor.
50Ω SOURCE
50Ω
RSHUNT
52.3Ω
Rev. B | Page 14 of 20
CC
RIN
CIN
VBIAS
Figure 35. Broadband Resistive
50Ω SOURCE
50Ω
AD8314
RFIN
X1
CC
X2
CIN
VBIAS
Figure 36. Narrowband Reactive
50Ω
At frequencies above 2 GHz, the input impedance drops below
250 Ω (see Figure 12), so it is appropriate to use a larger value
shunt resistor. This value is calculated by plotting the input
impedance (resistance and capacitance) on a Smith Chart and
choosing the best value shunt resistor to bring the input
impedance closest to the center of the chart. At 2.5 GHz, a
shunt resistor of 165 Ω is recommended.
AD8314
RFIN
01086-035
POWER-ON AND ENABLE GLITCH
In Figure 36, the matching components are drawn as general
reactances. Depending on the frequency, the input impedance at
that frequency, and the availability of standard value components,
either a capacitor or an inductor is used. As in the previous
case, the input impedance at a particular frequency is plotted on
a Smith Chart and matching components are chosen (shunt or
Series L, shunt or Series C) to move the impedance to the center
of the chart. Table 5 gives standard component values for some
popular frequencies. Matching components for other frequencies
can be calculated using the input resistance and reactance data
over frequency, which is given in Figure 12. Note that the
reactance is plotted as though it appears in parallel with the
input impedance (which it does because the reactance is
primarily due to input capacitance).
STRIPLINE
RATTN
AD8314
RFIN
CC
CIN
VBIAS
Figure 37. Series Attenuation
RIN
RIN
01086-036
The transient response of this control loop is determined by the
filter capacitor, CF. When this is large, the loop is unconditionally
stable (by virtue of the dominant pole generated by this
capacitor), but the response is sluggish. The minimum value
ensuring stability should be used, requiring full attention to the
particulars of the power amplifier control function. Because this
is invariably nonlinear, the choice must be made for the worstcase condition, which usually corresponds to the smallest
output from the PA, where the gain function is steepest. In
practice, an improvement in loop dynamics can often be
achieved by adding a response zero, formed by a resistor in
series with CF.
A reactive match can also be implemented as shown in Figure 36.
This is not recommended at low frequencies as device
tolerances dramatically varies the quality of the match because
of the large input resistance. For low frequencies, Figure 35 or
Figure 37 is recommended.
01086-037
When connected in a PA control loop, as shown in Figure 34,
the voltage VUP is not explicitly used but is implicated in again
setting up the required averaging time, by choice of CF.
However, now the effective loop response time is a much more
complicated function of the PA’s gain-control characteristics,
which are very nonlinear. A complete solution requires specific
knowledge of the power amplifier.
AD8314
Figure 37 shows a third method for coupling the input signal
into the AD8314, applicable in applications where the input
signal is larger than the input range of the log amp. A series
resistor, connected to the RF source, combines with the input
impedance of the AD8314 to resistively divide the input signal
being applied to the input. This has the advantage of very little
power being tapped off in RF power transmission applications.
EFFECT OF WAVEFORM TYPE ON INTERCEPT
Table 5. X1 and X2 Recommended Components in Figure 36
The effect of differing signal waveforms is to shift the effective
value of the intercept upwards or downwards. Graphically, this
looks like a vertical shift in the log amp’s transfer function. The
logarithmic slope, however, is not affected. For example,
consider the case of the AD8314 being alternately fed by an
unmodulated sine wave and by a single CDMA channel of the
same rms power. The AD8314’s output voltage differs by the
equivalent of 3.55 dB (70 mV) over the complete dynamic range
of the device (the output for a CDMA input being lower).
Frequency (GHz)
0.1
X1
Short
X2
52.3 Ω
Voltage Gain (dB)
0.9
1.9
2.5
33 nH
10 nH
1.5 pF
39 nH
15 nH
3.9 nH
11.8
7.8
2.55
INCREASING THE LOGARITHMIC SLOPE IN
MEASUREMENT MODE
The nominal logarithmic slope of 21.5 mV/dB (see Figure 10
for the variation of slope with frequency) can be increased to an
arbitrarily high value by attenuating the signal between V_UP
and VSET, as shown in Figure 38. The ratio R1/R2 is set by
⎛ New Slope ⎞
⎟ −1
R1/ R2 = ⎜
⎜ Original Slope ⎟
⎝
⎠
In the example shown, two 5 kΩ resistors combine to change
the slope at 1900 MHz from 20 mV/dB to 40 mV/dB. The slope
can be increased to higher levels. This, however, reduces the
usable dynamic range of the device.
VSET
AD8314
R1
5kΩ
40mV/dB
@ 1900MHz
R2
5kΩ
Figure 38. Increasing the Output Slope
01086-038
V_UP
Although specified for input levels in dBm (dB relative to
1 mW), the AD8314 fundamentally responds to voltage and not
to power. A direct consequence of this characteristic is that
input signals of equal rms power but differing crest factors
produces different results at the log amp’s output.
Table 6 shows the correction factors that should be applied to
measure the rms signal strength of various signal types. A sine
wave input is used as a reference. To measure the rms power of
a square wave, for example, the mV equivalent of the dB value
given in the table (20 mV/dB times 3.01 dB) should be
subtracted from the output voltage of the AD8314.
Table 6. Shift in AD8314 Output for Signals with Differing
Crest Factors
Signal Type
Correction
Factor (Add
to Measured
Input Level)
Sine Wave
Square Wave
GSM Channel (All Time Slots On)
CDMA Channel (Forward Link, 9 Channels On)
CDMA Channel (Reverse Link)
PDC Channel (All Time Slots On)
0 dB
−3.01 dB
+0.55 dB
+3.55 dB
+0.5 dB
+0.58 dB
Rev. B | Page 15 of 20
AD8314
MOBILE HANDSET POWER CONTROL EXAMPLES
Figure 39 shows a complete power amplifier control circuit for a
dual mode handset. This circuit is applicable to any dual mode
handset using TDMA or CDMA technologies. The PF08107B
(Hitachi) is driven by a nominal power level of 3 dBm. Some of
the output power from the PA is coupled off using an
LDC15D190A0007A (Murata) directional coupler. This has a
coupling factor of approximately 19 dB for its lower frequency
band (897.5 MHz ± 17.5 MHz) and 14 dB for its upper band
(1747.5 MHz ± 37.5 MHz) and an insertion loss of 0.38 dB
and 0.45 dB, respectively. Because the PF08107B transmits a
maximum power level of 35 dBm, additional attenuation of
15 dB is required before the coupled signal is applied to
the AD8314.
3.5V
The setpoint voltage, in the 0 V to 1.1 V range, is applied to the
VSET pin of the AD8314. This is typically supplied by a DAC.
This voltage is compared to the input level of the AD8314. Any
imbalance between VSET and the RF input level is corrected by
V_DN, which drives the VAPC (gain control) of the power
amplifier. V_DN reaches a maximum value of approximately
1.9 V on a 2.7 V supply (this is higher for higher supply
voltages) while delivering approximately 3 mA to the VAPC input.
A filter capacitor (CF) must be used to stabilize the loop. The
choice of CF depends to a large degree on the gain control
dynamics of the power amplifier, something that is frequently
characterized poorly, so some trial and error can be necessary.
In this example, a 220 pF capacitor gives the loop sufficient
speed to follow the GSM and DCS1800 time slot ramping
profiles, while still having a stable, critically damped response.
4.7µF
1000pF
BAND
SELECT
0V/2V
POUT BAND 1
35dBm MAX
TO
LDC15D190A0007A
ANTENNA
7
1
8
4
5
3
2
ATTN
15dB
49.9Ω
6
PIN BAND 1
3dBm
VCTL
PF08107B
(HITACHI)
POUT BAND 2
32dBm MAX
PIN BAND 2
3dBm
VAPC
52.3Ω
0.1µF
0dBm
MAX
VS
VPOS 8
2 ENBL
V_DN 7
VS
2.7V
AD8314
3 VSET
V_UP 6
4 FLTR
COMM 5
CF
220pF
01086-039
VSET
0V TO 1.1V
1 RFIN
Figure 39. A Dual Mode Power Amplifier Control Circuit
Rev. B | Page 16 of 20
AD8314
3.5V
Figure 40 shows the relationship between the setpoint voltage,
VSET and output power at 0.9 GHz. The overall gain control
function is linear in dB for a dynamic range of over 40 dB.
Figure 41 shows a similar circuit for a single band handset
power amplifier. The BGY241 (Phillips) is driven by a nominal
power level of 0 dBm. A 20 dB directional coupler, DC09-73
(Alpha), is used to couple the signal in this case. Figure 42
shows the relationship between the control voltage and the
output power at 0.9 GHz.
47µF
2.2µF
680pF
TO
ANTENNA
3
15dBm
In both of these examples, noise on the V_DN pin can be reduced
by placing a simple RC low-pass filter between VDN and the gain
control pin of the power amplifier. However, the value of the
resistor should be kept low to minimize the voltage drop across
it due to the dc current flowing into the gain control input.
ATTN
15dB
RF INPUT
1
PIN
0dBm
2
0.1µF
0dBm
MAX
VS
1 RFIN
VPOS 8
2 ENBL
V_DN 7
VS
2.7V
AD8314
VSET
0V TO 1.1V
20
3 VSET
V_UP 6
4 FLTR
COMM 5
01086-041
10
CF
220pF
0
Figure 41. A Single Mode Power Amplifier Control Circuit
–10
40
–20
20
0.2
0.4
0.6
VSET (V)
0.8
1.0
1.2
Figure 40. POUT vs. VSET at 0.9 GHz for Dual Mode Handset Power Amplifier
Application
10
POUT (dBm)
0
01086-040
–30
30
0
–10
–20
–30
–40
–50
0
0.2
0.4
0.6
0.8
1.0
VSET (V)
Figure 42. POUT vs. VSET at 0.9 GHz for Single Mode Handset
Rev. B | Page 17 of 20
01086-042
POUT (dBm)
BGY241
5
52.3Ω
40
30
35dBm
MAX
DC09-73
6
4
AD8314
OPERATION AT 2.7 GHz
USING THE LFCSP PACKAGE
While the AD8314 is specified to operate at frequencies up to
2.5 GHz, it works at higher frequencies, although it does exhibit
slightly higher output voltage temperature drift. Figure 43
shows the transfer function of a typical device at 2.7 GHz, at
ambient as well as hot and cold temperatures.
On the underside of the LFCSP package, there is an exposed,
compressed paddle. This paddle is internally connected to the
chip’s ground. While the paddle can be connected to the printed
circuit board’s ground plane, there is no thermal or electrical
requirement to do this.
Figure 44 shows the transfer function of the AD8314 when
driven by both an unmodulated sine wave and a 64 QAM
signal. As previously discussed, the higher peak-to-average ratio
of the 64 QAM signal causes an increase in the intercept.
EVALUATION BOARD
Figure 45 shows the schematic of the AD8314 MSOP
evaluation board. The layout and silkscreen of the component
side are shown in Figure 46 and Figure 47. An evaluation board
is also available for the LFCSP package. (For exact part numbers,
see the Ordering Guide.) Apart from the slightly smaller device
footprint, the LFCSP evaluation board is identical to the MSOP
board. The board is powered by a single supply in the 2.7 V to
5.5 V range. The power supply is decoupled by a single 0.1 μF
capacitor. Additional decoupling, in the form of a series resistor
or inductor in R9, can also be added. Table 7 details the various
configuration options of the evaluation board.
In this case, the intercept increases by approximately 1.5 dB,
causing the overall transfer function to drop by the same
amount. For precision operation, the AD8314 should be
calibrated for each signal type that is driving it.
1.2
3
1.2
2
1.0
3
+25°C
1.0
2
CW
0.4
+80°C
0.6
–1
0.4
–2
0.2
0
ERROR (dB)
0
1
CW
–1
64 QAM
+80°C
0.2
–2
–60
–50
–40
–30
–20
–10
–3
10
0
0
–70
INPUT POWER (dBm)
R1
0Ω
1 RFIN
VPOS 8
2 ENBL
V_DN 7
SW1
R8
OPEN
–30
–20
–10
C1
0.1µF
VPOS
LK1
–40
0
Figure 44. Shift in Transfer Function due to 64 QAM
R2
52.3Ω
VSET
–50
INPUT POWER (dBm)
Figure 43. Operating at 2.7 GHz
INPUT
–60
R9
0Ω
R4
(OPEN)
AD8314
3 VSET
V_UP 6
4 FLTR
COMM 5
C2
(OPEN)
R5
0Ω
C4
(OPEN)
R6
(OPEN)
R7
0Ω
Figure 45. Evaluation Board Schematic
Rev. B | Page 18 of 20
VPOS
R3
0Ω
C3
(OPEN)
V_DN
V_UP
01086-045
0
–70
–3
10
01086-044
64 QAM
01086-043
VUP (V)
0.6
0.8
1
VUP (V)
–40°C
0.8
ERROR (dB)
+25°C
–40°C
01086-047
01086-046
AD8314
Figure 46. Layout of Component Side (MSOP)
Figure 47. Silkscreen of Component Side (MSOP)
Table 7. Evaluation Board Configuration Options
Component
TP1, TP2
SW1
R1, R2
R3, R4, C2,
R5, R6, C3
C1, R9
C4
R7, R8
LK1
Function
Supply and Ground Vector Pins.
Device Enable: When in Position A, the ENBL pin is connected to +VS and the AD8314 is in
operating mode. In Position B, the ENBL pin is grounded, putting the device in power-down mode.
Input Interface. The 52.3 Ω resistor in Position R2 combines with the AD8314’s internal input
impedance to give a broadband input impedance of around 50 Ω. A reactive match can be
implemented by replacing R2 with an inductor and R1 (0 Ω) with a capacitor. Note that the
AD8314’s RF input is internally ac-coupled.
Output Interface. R4, C2, R6, and C3 can be used to check the response of V_UP and V_DN to
capacitive and resistive loading. R3/R4 and R5/R6 can be used to reduce the slope of V_UP
and V_DN.
Power Supply Decoupling. The nominal supply decoupling consists of a 0.1 μF capacitor (C1).
A series inductor or small resistor can be placed in R9 for additional decoupling.
Filter Capacitor. The response time of V_UP and V_DN can be modified by placing a capacitor
between FILTR and V_UP.
Slope Adjust. By installing resistors in R7 and R8, the nominal slope of 20 mV/dB can be
increased. See Increasing the Logarithmic Slope in Measurement Mode for more details.
Measurement/Controller Mode. LK1 shorts V_UP to VSET, placing the AD8314 in measurement
mode. Removing LK1 places the AD8314 in controller mode.
Rev. B | Page 19 of 20
Default Condition
Not Applicable
SW1 = A
R2 = 52.3 Ω (Size 0603)
R1 = 0 Ω (Size 0402)
R4 = C2 = R6 =
C3 = Open (Size 0603)
R3= R5 = 0 Ω (Size 0603)
C1 = 0.1 μF (Size 0603)
R9 = 0 Ω (Size 0603)
C4 = Open (Size 0603)
R7 = 0 Ω (Size 0603)
R8 = Open (Size 0603)
LK1 = Installed
AD8314
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5
5.15
4.90
4.65
1.95
1.75
1.55
4
PIN 1
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
TOP VIEW
0.23
0.08
1.00
0.85
0.80
0.80
0.60
0.40
8°
0°
SEATING
PLANE
0.60
0.45
0.30
2.25
2.00
1.75
12° MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.55
0.40
0.30
5 BOTTOM VIEW
* 8
EXPOSED PAD
4
2.95
2.75
2.55
PIN 1
INDICATOR
0.65 BSC
0.95
0.85
0.75
1.89
1.74
1.59
3.25
3.00
2.75
0.50 BSC
0.15
0.10
0.05
1
0.25
0.20
0.15
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.20 REF
Figure 49. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
2 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-1)
Dimensions shown in millimeters
Figure 48. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8314ARM
AD8314ARM-REEL
AD8314ARM-REEL7
AD8314ARMZ 1
AD8314ARMZ-REEL1
AD8314ARMZ-REEL71
AD8314-EVAL
AD8314ACP-REEL
AD8314ACP-REEL7
AD8314ACP-WP
AD8314ACPZ-REEL1
AD8314ACPZ-RL71
AD8314ACP-EVAL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead MSOP, Tube
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP, Tube
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
MSOP Evaluation Board
8-Lead LFCSP_VD, 13" Tape and Reel
8-Lead LFCSP_VD, 7" Tape and Reel
8-Lead LFCSP_VD, Waffle Pack
8-Lead LFCSP_VD, 13" Tape and Reel
8-Lead LFCSP_VD, 7" Tape and Reel
LFCSP_VD Evaluation Board
Package Option
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
J5A
J5A
J5A
J5A#
J5A#
J5A#
Ordering
Quantity
50
3,000
1,000
50
3,000
1,000
CP-8-1
CP-8-1
CP-8-1
CP-8-1
CP-8-1
J5
J5
J5
0F
0F
10,000
3,000
50
10,000
3,000
Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01086-0-5/06(B)
T
T
Rev. B | Page 20 of 20