SpectraLinear CY28301PVCT Frequency generator for intel(r) integrated chipset Datasheet

CY28301
Frequency Generator for Intel(r) Integrated Chipset
Features
Key Specifications
®
• Single chip FTG solution for Intel Solano/810E/810
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
• Support SMBus byte Read/Write and block Read/Write
operations to simplify system BIOS development
APIC, 48 MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ................................................... 500 ps
• Vendor ID and revision ID support
CPU, 3V66 Output Skew:............................................ 175 ps
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
SDRAM, APIC, 48-MHz Output Skew:........................ 250 ps
• Low jitter and tightly controlled clock skew
CPU to SDRAM Skew (@ 133 MHz) ......................... ±0.5 ns
• Two copies of CPU clock
CPU to SDRAM Skew (@ 100 MHz)..................4.5 to 5.5 ns
• Thirteen copies of SDRAM clock
CPU to 3V66 Skew (@ 66 MHz) ........................7.0 to 8.0 ns
• Eight copies of PCI clock
3V66 to PCI Skew (3V66 lead)...........................1.5 to 3.5 ns
• One copy of synchronous APIC clock
PCI to APIC Skew ...................................................... ±0.5 ns
PCI Output Skew:........................................................ 500 ps
• Three copies of 66 MHz outputs
• Two copies of 48 MHz outputs
• One copy of 14.31818 MHz reference clock
Pin Configuration[1]
Block Diagram
VDD_REF
X1
X2
PLL REF FREQ
SDATA
SCLK
SMBus
Logic
Divider,
Delay, and
Phase
Control
Logic
(FS0:4)
PLL 1
PD#
PLL2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CY28301
VDD_REF
X1
X2
GND_REF
VDD_CPU
GND_3V66
3V66_0
CPU0:1
3V66_1
2
3V66_2
VDD_3V66
VDD_APIC
VDD_PCI
APIC
PCI0
PCI1
VDD_3V66
PCI2/SEL24_48MHz#*
3V66_0:2
GND_PCI
3
VDD_PCI
PCI3
PCI4
PCI0
PCI5
PCI1
VDD_PCI
PCI2/SEL24_48MHz#*
PCI6
PCI3:7
5
PCI7
GND_PCI
VDD_SDRAM
PD#*
SDRAM0:11,
SCLK
13
SDRAM_F
SDATA
VDD_SDRAM
SDRAM11
SDRAM10
VDD_48MHz
GND_SDRAM
REF/FS1
XTAL
OSC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF/FS1*
VDD_APIC
APIC
VDD_CPU
CPU0
CPU1
GND_CPU
GND_SDRAM
SDRAM0
SDRAM1
SDRAM2
VDD_SDRAM
SDRAM3
SDRAM4
SDRAM5
GND_SDRAM
SDRAM6
SDRAM7
SDRAM_F
VDD_SDRAM
GND_48MHz
24_48MHz
48MHz/FS0*
VDD_48MHz
VDD_SDRAM
SDRAM8
SDRAM9
GND_SDRAM
48MHz/FS0
/2
24_48MHz
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design
should not rely solely on internal pull-up resistor to set I/O pins HIGH.
Rev 1.0, November 27, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 13
Tel:(408) 855-0555
Fax:(408) 855-0550
www.SpectraLinear.com
CY28301
Pin Definitions
Pin No.
Pin
Type
REF/FS1
56
I/O
Reference Clock /Frequency Select 1: 3.3V 14.318-MHz clock output.
This pin also serves as the select strap to determine the device operating
frequency (as described in Table 5).
X1
2
I
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency
input.
X2
3
O
Crystal Output: An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left
unconnected.
PCI0
11
O
PCI Clock 0: 3.3V 33-MHz PCI clock output.
PCI1
12
O
PCI Clock 1: 3.3V 33-MHz PCI clock output.
PCI2/SEL24_48MHz#
13
O
PCI Clock 2/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This
pin also serves as the select strap to determine the output frequency for
24_48MHz output. Logic 1 = 24 MHz on pin 35.
15, 16, 17, 19,
20
O
PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be
individually turned off via the SMBus interface.
6, 7, 8
O
66-MHz Clock Output: 3.3V output clocks. The operating frequency is
controlled by FS0:1 (see Table 5).
48MHz/FS0
34
I/O
48-MHz Output/Frequency Selection 1: 3.3V 48-MHz non-spread
spectrum output. This pin also serves as the select strap to determine the
device operating frequency (as described in Table 5.)
24_48MHz
35
O
24- or 48-MHz Output: 3.3V 24- or 48-MHz non-spread spectrum output.
PD#
22
I
Power-down Input: LVTTL-compatible asynchronous input that places
the device in power-down mode when held LOW.
52, 51
O
CPU Clock Outputs: Clock outputs for the host bus interface. Output
frequencies depending on the configuration of FS0:1. Voltage swing is set
by VDDQ2.
48, 47, 46, 44,
43, 42, 40, 39,
31, 30, 27, 26,
38
O
SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The
operating frequency is controlled by FS0:1 (see Table 5).
APIC
54
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous
with the PCI clock outputs. Voltage swing set by VDDQ2.
SDATA
24
I/O
Data pin for SMBus circuitry.
SCLK
23
I
Clock pin for SMBus circuitry.
1, 9, 10, 18, 25,
32, 37, 45, 33
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI
output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
53, 55
P
2.5V Power Connection: Power supply for APIC and CPU output buffers.
Connect to 2.5V.
4, 5, 14, 21, 28,
29, 41, 49, 50,
36
G
Ground Connections: Connect all ground pins to the common system
ground plane.
Pin Name
PCI3:7
3V66_0:2
CPU0:1
SDRAM0:11,
SDRAM_F
VDD_REF,
VDD_3V66, VDD_PCI,
VDD_SDRAM,
VDD_48MHz
VDD_CPU,
VDD_APIC
GND_REF,
GND_3V66,
GND_PCI,
GND_SDRAM,
GND_48MHZ,
GND_CPU
Rev 1.0, November 27, 2006
Pin Description
Page 2 of 13
CY28301
Serial Data Interface
The CY28301 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions.
Data Protocol
The clock driver serial protocol supports byte/word Write,
byte/word Read, block Write, and block Read operations from
the controller. For block Write/Read operation, the bytes must
be accessed in sequential order from lowest to highest byte
with the ability to stop after any complete byte has been transferred. For byte/word Write and byte Read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code.
The definition for the command code is defined as follows.
Table 1. Command Code Definition
Bit
Descriptions
7
0 = Block Read or block Write operation
1 = Byte/Word Read or byte/word Write operation
6:0
Byte offset for byte/word Read or Write operation. For block Read or Write operations, these bits
need to be set at ‘0000000.’
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
Block Read Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
28
29:36
37
38:45
46
Command code – 8-bits
‘00000000’ stands for block operation
11:18
Command code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
19
Acknowledge from slave
Byte count – 8 bits
20
Repeat start
Acknowledge from slave
21:27
Slave address – 7 bits
Data byte 0 – 8 bits
28
Read
Acknowledge from slave
29
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
...
Data byte N/Slave acknowledge...
...
Data byte N – 8 bits
...
Acknowledge from slave
...
Stop
Rev 1.0, November 27, 2006
30:37
38
39:46
47
48:55
56
Byte count from slave –8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
...
Data bytes from slave/acknowledge
...
Data byte N from slave – 8 bits
...
Not acknowledge
...
Stop
Page 3 of 13
CY28301
Table 3. Word Read and Word Write Protocol
Word Write Protocol
Bit
1
2:8
Description
Start
Word Read Protocol
Bit
1
Slave address – 7 bits
2:8
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
28
29:36
Command Code – 8-bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Data byte low – 8 bits
Acknowledge from slave
11:18
19
20
21:27
Command code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Data byte high – 8 bits
28
Read
37
Acknowledge from slave
29
Acknowledge from slave
38
Stop
30:37
38
39:46
Data byte low from slave – 8 bits
Acknowledge
Data byte high from slave – 8 bits
47
Not acknowledge
48
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
Byte Read Protocol
Bit
1
2:8
Description
Start
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
Command code 8 – bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Data byte 8 – bits
28
Acknowledge from slave
29
Stop
11:18
19
20
21:27
Acknowledge from slave
Repeat start
Slave address – 7 bits
28
Read
29
Acknowledge from slave
30:37
Rev 1.0, November 27, 2006
Command code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Data byte from slave – 8 bits
38
Not Acknowledge
39
Stop
Page 4 of 13
CY28301
CY28301 Serial Configuration Map
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to “0”
during initialization.
Byte 0: Control Register 0
Bit
Pin#
Name
Default
Description
Bit 7
–
SEL1
0
See 5
Bit 6
–
SEL0
0
See 5
Bit 5
–
Reserved
0
Reserved
Bit 4
–
Reserved
0
Reserved
Bit 3
–
FS_Override
0
0 = Select operating frequency by FS[1:0] input pins
1 = Select operating frequency by SEL[1:0] settings
Bit 2
–
Spread Select2
0
‘000’ = Normal (spread off)
Bit 1
–
Spread Select1
0
‘001’ = Test mode
Bit 0
–
Spread Select0
0
‘010’ = Reserved
‘011’ = Three-stated
‘100’ = –0.5%
‘101’ = –0.75%
‘110’ = –1.0%
‘111’ = –0.3%
Byte 1: Control Register 1
Bit
Pin#
Name
Default
Description
Bit 7
56
Latched FS1 input
X
Bit 6
34
Latched FS0 input
X
Bit 5
–
Reserved
0
Reserved
Bit 4
–
Reserved
0
Reserved
Bit 3
–
Reserved
0
Reserved
Bit 2
–
Reserved
0
Reserved
Bit 1
56
REF
1
(Active/Inactive)
Bit 0
56
REF_DRV
0
REF Clock output drive strength
0 = Normal
1= High drive
Rev 1.0, November 27, 2006
Latched FS[1:0] inputs. These bits are Read-only.
Page 5 of 13
CY28301
Byte 2: Control Register 2
Bit
Pin#
Name
Default
Description
Bit 7
20
PCI7
1
(Active/Inactive)
Bit 6
19
PCI6
1
(Active/Inactive)
Bit 5
17
PCI5
1
(Active/Inactive)
Bit 4
16
PCI4
1
(Active/Inactive)
Bit 3
15
PCI3
1
(Active/Inactive)
Bit 2
13
PCI2
1
(Active/Inactive)
Bit 1
12
PCI1
1
(Active/Inactive)
Bit 0
11
PCI0
1
(Active/Inactive)
Byte 3: Control Register 3
Bit
Pin#
Name
Default
Description
Bit 7
8
3V66_2
1
(Active/Inactive)
Bit 6
7
3V66_1
1
(Active/Inactive)
Bit 5
6
3V66_0
1
(Active/Inactive)
Bit 4
54
APIC
1
(Active/Inactive)
Bit 3
–
Reserved
0
Reserved
Bit 2
–
Reserved
0
Reserved
Bit 1
51
CPU1
1
(Active/Inactive)
Bit 0
52
CPU0
1
(Active/Inactive)
Byte 4: Control Register 4
Bit
Pin#
Name
Default
Description
Bit 7
39
SDRAM7
1
(Active/Inactive)
Bit 6
40
SDRAM6
1
(Active/Inactive)
Bit 5
42
SDRAM5
1
(Active/Inactive)
Bit 4
43
SDRAM4
1
(Active/Inactive)
Bit 3
44
SDRAM3
1
(Active/Inactive)
Bit 2
46
SDRAM2
1
(Active/Inactive)
Bit 1
47
SDRAM1
1
(Active/Inactive)
Bit 0
48
SDRAM0
1
(Active/Inactive)
Byte 5: Control Register 5
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
Reserved
0
Reserved
Bit 5
–
Reserved
0
Reserved
Bit 4
38
SDRAM_F
1
(Active/Inactive)
Bit 3
26
SDRAM11
1
(Active/Inactive)
Bit 2
27
SDRAM10
1
(Active/Inactive)
Bit 1
30
SDRAM9
1
(Active/Inactive)
Bit 0
31
SDRAM8
1
(Active/Inactive)
Byte 6: Vendor ID and Revision ID Register (Read-only)
Bit
Name
Default
Pin Description
Bit 7
Revision_ID3
0
Revision ID bit[3]
Bit 6
Revision_ID2
0
Revision ID bit[2]
Rev 1.0, November 27, 2006
Page 6 of 13
CY28301
Byte 6: Vendor ID and Revision ID Register (Read-only)
Bit
Name
Default
Pin Description
Bit 5
Revision_ID1
0
Revision ID bit[1]
Bit 4
Revision_ID0
0
Revision ID bit[0]
Bit 3
Vendor_ID3
1
Bit[3] of Cypress’s Vendor ID. This bit is Read-only.
Bit 2
Vendor_ID2
0
Bit[2] of Cypress’s Vendor ID. This bit is Read-only.
Bit 1
Vendor _ID1
0
Bit[1] of Cypress’s Vendor ID. This bit is Read-only.
Bit 0
Vendor _ID0
0
Bit[0] of Cypress’s Vendor ID. This bit is Read-only.
Byte 7: Control Register 7
Bit
Pin#
Name
Default
Pin Description
Bit 7
–
Reserved
0
Reserved
Bit 6
35
24_48MHz_DRV
1
0 = Norm, 1 = High drive
Bit 5
34
48MHz_DRV
1
0 = Norm, 1 = High drive
Bit 4
–
Reserved
0
Reserved
Bit 3
35
24_48MHz
1
(Active/Inactive)
Bit 2
34
48 MHz
1
(Active/Inactive)
Bit 1
–
Reserved
0
Reserved
Bit 0
–
Reserved
0
Reserved
Byte 8: Reserved Register
Bit
Name
Default
Pin Description
Bit 7
PCI_Skew1
0
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
Bit 6
PCI_Skew0
0
Bit 5
Reserved
1
Reserved. Write with ‘1’
Bit 4
Reserved
1
Reserved. Write with ‘1’
Bit 3
Reserved
1
Reserved. Write with ‘1’
Bit 2
Reserved
1
Reserved. Write with ‘1’
Bit 1
Reserved
1
Reserved. Write with ‘1’
Bit 0
Reserved
0
Reserved
Byte 9: Reserved Register
Bit
Name
Default
Pin Description
Bit 7
SDRAM_DRV
0
SDRAM clock output drive strength
0 = Normal
1 = High Drive
Bit 6
PCI_DRV
0
PCI and AGP clock output drive strength
0 = Normal
1 = High drive
Bit 5
Reserved
0
Reserved
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
Reserved
0
Reserved
Bit 0
Reserved
0
Reserved
Rev 1.0, November 27, 2006
Page 7 of 13
CY28301
Byte 10: Reserved Register
Bit
Name
Default
Bit 7
CPU_Skew2
0
Bit 6
CPU_Skew1
0
Bit 5
CPU_Skew0
0
Bit 4
SDRAM_Skew2
0
Bit 3
SDRAM_Skew1
0
Bit 2
SDRAM_Skew0
0
Bit 1
AGP_Skew1
0
Bit 0
AGP_Skew0
0
Description
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
SDRAM skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
AGP skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Byte 11: Reserved Register
Bit
Name
Default
Pin Description
Bit 7
Reserved
0
Reserved
Bit 6
Reserved
0
Reserved
Bit 5
Reserved
0
Reserved
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
Reserved
0
Reserved
Bit 0
Reserved
0
Reserved
Byte 12: Reserved Register
Bit
Name
Default
Pin Description
Bit 7
Reserved
0
Reserved
Bit 6
Reserved
0
Reserved
Bit 5
Reserved
0
Reserved
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
Reserved
0
Reserved
Bit 0
Reserved
0
Reserved
Byte 13: Reserved Register
Bit
Name
Default
Pin Description
Bit 7
Reserved
0
Reserved
Bit 6
Reserved
0
Reserved
Bit 5
Reserved
0
Reserved
Rev 1.0, November 27, 2006
Page 8 of 13
CY28301
Byte 13: Reserved Register
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
Reserved
0
Reserved
Bit 0
Reserved
0
Reserved
Byte 14: Reserved Register
Bit
Name
Default
Description
Bit 7
Reserved
0
Reserved
Bit 6
Reserved
0
Reserved
Bit 5
Reserved
0
Reserved
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
Reserved
0
Reserved
Bit 0
Reserved
0
Reserved
Byte 15: Reserved Register
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
Reserved
0
Reserved
Bit 5
–
Reserved
0
Reserved
Bit 4
–
Reserved
0
Reserved
Bit 3
–
Reserved
0
Reserved
Bit 2
–
Reserved
0
Reserved
Bit 1
–
Reserved
1
Reserved. Write with ‘1’
Bit 0
–
Reserved
1
Reserved. Write with ‘1’
Byte 16: Reserved Register
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
Reserved
0
Reserved
Bit 5
–
Reserved
0
Reserved
Bit 4
–
Reserved
0
Reserved
Bit 3
–
Reserved
0
Reserved
Bit 2
–
Reserved
0
Reserved
Bit 1
–
Reserved
0
Reserved
Byte 17: Reserved Register
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
Reserved
0
Reserved
Bit 5
–
Reserved
0
Reserved
Bit 4
–
Reserved
0
Reserved
Bit 3
–
Reserved
0
Reserved
Bit 2
–
Reserved
0
Reserved
Bit 1
–
Reserved
0
Reserved
Rev 1.0, November 27, 2006
Page 9 of 13
CY28301
Table 5. Frequency Selections through HW Strap Option and Serial Data Interface Data Bytes
Input Conditions
Output Frequency
FS1
FS0
SEL1
SEL0
CPU
SDRAM
3V66
PCI
APIC
0
0
66.6
100.0
66.6
33.3
16.6
0
1
100.0
100.0
66.6
33.3
16.6
1
0
133.3
133.3
66.6
33.3
16.6
1
1
133.3
100.0
66.6
33.3
16.6
DC Electrical Characteristics[2]
DC parameters must be sustainable under steady state (DC) conditions.
Absolute Maximum DC Power Supply
Min.
Max.
Unit
VDDQ3
Parameter
3.3V Core Supply Voltage
Description
–0.5
4.6
V
VDDQ2
2.5V I/O Supply Voltage
–0.5
3.6
V
TS
Storage Temperature
–65
150
°C
Min.
Max.
Unit
Absolute Maximum DC I/O
Parameter
Description
Vi/o3
3.3V Core Supply Voltage
–0.5
4.6
V
Vi/o3
2.5V I/O Supply Voltage
–0.5
3.6
V
ESD prot.
Input ESD Protection
2000
V
DC Operating Requirements
Min.
Max.
Unit
VDD3
Parameter
3.3V Core Supply Voltage
Description
3.3V ±5%
Condition
3.135
3.465
V
VDDQ3
3.3V I/O Supply Voltage
3.3V ±5%
3.135
3.465
V
VDDQ2
2.5V I/O Supply Voltage
2.5V ±5%
2.375
2.625
V
Vih3
3.3V Input High Voltage
VDD3
2.0
VDD + 0.3
V
Vil3
3.3V Input Low Voltage
VSS – 0.3
0.8
V
0 < Vin <VDD3
–5
+5
µA
2.0
VDD3 = 3.3V ±5%
Iil
Input Leakage
Current[3]
VDDQ2 = 2.5V ±5%
Voh2
2.5V Output High Voltage
Ioh = (–1 mA)
Vol2
2.5V Output Low Voltage
Iol = (1 mA)
Voh3
3.3V Output High Voltage
Ioh = (–1 mA)
Vol3
3.3V Output Low Voltage
Iol = (1 mA)
Vpoh3
PCI Bus Output High Voltage
Ioh = (–1 mA)
Vpol3
PCI Bus Output Low Voltage
Iol = (1 mA)
V
0.4
V
VDDQ3 = 3.3V ±5%
.4
V
0.4
V
VDDQ3 = 3.3V ±5%
2.4
V
0.55
V
Note:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Input leakage current does not include inputs with pull-up or pull-down resistors.
Rev 1.0, November 27, 2006
Page 10 of 13
CY28301
DC Operating Requirements (continued)
Parameter
Description
Cin
Input Pin Capacitance
Cxtal
Xtal Pin Capacitance
Cout
Output Pin Capacitance
Lpin
Pin Inductance
Ta
Ambient Temperature
Condition
Min.
13.5
No airflow
Max.
Unit
5
pF
22.5
pF
6
pF
0
7
nH
0
70
°C
AC Electrical Characteristics[2] (TA = 0°C to +70°C, VDDQ3 = 3.3V ±5%, VDDQ2= 2.5V ±5% fXTL = 14.31818 MHz)
Parameter
Description
66.6-MHz Host
100-MHz Host
133-MHz Host
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Notes
CPUCLK
TPeriod
Host/CPUCLK Period
15.0
15.5
10.0
10.5
7.5
8.0
ns
4
THIGH
Host/CPUCLK High Time
5.2
N/A
3.0
N/A
1.87
N/A
ns
5
TLOW
Host/CPUCLK Low Time
5.0
N/A
2.8
N/A
1.67
N/A
ns
6
TRISE
Host/CPUCLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
Host/CPUCLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
SDRAM
TPeriod
SDRAM CLK Period
10.0
10.5
10.0
10.5
10.0
10.5
ns
THIGH
SDRAM CLK High Time
3.0
N/A
3.0
N/A
3.0
N/A
ns
5
TLOW
SDRAM CLK Low Time
2.8
N/A
2.8
N/A
2.8
N/A
ns
6
TRISE
SDRAM CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
SDRAM CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
APIC
TPeriod
APIC CLK Period
60.0
64.0
60.0
N/A
60.0
64.0
ns
4
THIGH
APIC CLK High Time
25.5
N/A
25.5
N/A
25.5
N/A
ns
5
TLOW
APIC CLK Low Time
25.3
N/A
25.30
N/A
25.30
N/A
ns
6
TRISE
APIC CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
APIC CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
3V66
TPeriod
3V66 CLK Period
15.0
16.0
15.0
16.0
15.0
16.0
ns
4, 8
THIGH
3V66 CLK High Time
5.25
N/A
5.25
N/A
5.25
N/A
ns
5
TLOW
3V66 CLK Low Time
5.05
N/A
5.05
N/A
5.05
N/A
ns
6
TRISE
3V66 CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TFALL
3V66 CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
4
Notes:
4. Period, jitter, offset, and skew measured on the rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
5. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and
operating within specifications.
6. TRISE and TFALL are measured as transitions through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.
7. THIGH is measured at 2.0V for 2.5V outputs, and 2.4V for 3.3V outputs.
8. TLOW is measured at 0.4V for all outputs.
Rev 1.0, November 27, 2006
Page 11 of 13
CY28301
AC Electrical Characteristics[2] (TA = 0°C to +70°C, VDDQ3 = 3.3V ±5%, VDDQ2= 2.5V ±5% fXTL = 14.31818 MHz)
Parameter
Description
66.6-MHz Host
100-MHz Host
133-MHz Host
Min.
Min.
Min.
Max.
Max.
Max.
Unit
Notes
PCI
TPeriod
PCI CLK Period
30.0
N/A
30.0
N/A
30.0
N/A
ns
4, 7
THIGH
PCI CLK High Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
5
TLOW
PCI CLK Low Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
6
TRISE
PCI CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TFALL
PCI CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
tpZL, tpZH
Output Enable Delay (All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tpLZ, tpZH
Output Disable Delay
(All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tstable
All Clock Stabilization from
Power-Up
3
ms
3
3
Group Skew and Jitter Limits
Output Group
Pin-Pin Skew Max.
Cycle-Cycle Jitter
Duty Cycle
Nom. VDD
Skew, Jitter
Measure Point
CPU
175 ps
250 ps
45/55
2.5V
1.25V
SDRAM
250 ps
250 ps
45/55
3.3V
1.5V
APIC
250 ps
500 ps
45/55
2.5V
1.25V
48MHz
250 ps
500 ps
45/55
3.3V
1.5V
3V66
175 ps
500 ps
45/55
3.3V
1.5V
PCI
500 ps
500 ps
45/55
3.3V
1.5V
REF
N/A
1000 ps
45/55
3.3V
1.5V
Output
Buffer
Test Point
Test Load
Clock Output Wave
TPERIOD
Duty Cycle
THIGH
2.0
2.5V Clocking
Interface
1.25
0.4
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
3.3V Clocking
Interface
1.5
0.4
TLOW
TRISE
TFALL
Figure 1. Output Buffer
Rev 1.0, November 27, 2006
Page 12 of 13
CY28301
Ordering Information
Ordering Code
Package Type
Operating Range
CY28301PVC
56-pin SSOP (300 mils)
Commercial, 0°C to 70°C
CY28301PVCT
56-pin SSOP (300 mils) - Tape and Reel
Commercial, 0°C to 70°C
Package Drawing and Dimension
56-Lead Shrunk Small Outline Package O56
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 27, 2006
Page 13 of 13