AD AD603ARZ-REEL Low noise, 90 mhz variable gain amplifier Datasheet

Low Noise, 90 MHz
Variable Gain Amplifier
AD603
impedance (50 MΩ), low bias (200 nA) differential input; the
scaling is 25 mV/dB, requiring a gain control voltage of only 1 V
to span the central 40 dB of the gain range. An overrange and
underrange of 1 dB is provided whatever the selected range. The
gain control response time is less than 1 µs for a 40 dB change.
FEATURES
Linear-in-dB gain control
Pin programmable gain ranges
−11 dB to +31 dB with 90 MHz bandwidth
9 dB to 51 dB with 9 MHz bandwidth
Any intermediate range, for example −1 dB to +41 dB
with 30 MHz bandwidth
Bandwidth independent of variable gain
1.3 nV/√Hz input noise spectral density
±0.5 dB typical gain accuracy
The differential gain control interface allows the use of either
differential or single-ended positive or negative control voltages.
Several of these amplifiers may be cascaded and their gain
control gains offset to optimize the system S/N ratio.
The AD603 can drive a load impedance as low as 100 Ω with
low distortion. For a 500 Ω load in shunt with 5 pF, the total
harmonic distortion for a ±1 V sinusoidal output at 10 MHz is
typically −60 dBc. The peak specified output is ±2.5 V
minimum into a 500 Ω load.
APPLICATIONS
RF/IF AGC amplifier
Video gain control
A/D range extension
Signal measurement
The AD603 uses a patented proprietary circuit topology—the
X-AMP®. The X-AMP comprises a variable attenuator of 0 dB
to −42.14 dB followed by a fixed-gain amplifier. Because of the
attenuator, the amplifier never has to cope with large inputs and
can use negative feedback to define its (fixed) gain and dynamic
performance. The attenuator has an input resistance of 100 Ω,
laser trimmed to ±3%, and comprises a seven-stage R-2R ladder
network, resulting in an attenuation between tap points of
6.021 dB. A proprietary interpolation technique provides a
continuous gain control function which is linear in dB.
GENERAL DESCRIPTION
The AD603 is a low noise, voltage-controlled amplifier for use
in RF and IF AGC systems. It provides accurate, pin selectable
gains of −11 dB to +31 dB with a bandwidth of 90 MHz or 9 dB
to 51 dB with a bandwidth of 9 MHz. Any intermediate gain
range may be arranged using one external resistor. The input
referred noise spectral density is only 1.3 nV/√Hz and power
consumption is 125 mW at the recommended ±5 V supplies.
The decibel gain is linear in dB, accurately calibrated, and stable
over temperature and supply. The gain is controlled at a high
The AD603 is specified for operation from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VPOS 8
SCALING
REFERENCE
PRECISION PASSIVE
INPUT ATTENUATOR
FIXED-GAIN
AMPLIFIER
VNEG 6
GPOS 1
7
VOUT
5
FDBK
VG
GNEG 2
6.44kΩ1
AD603
GAINCONTROL
INTERFACE
694Ω1
0dB
–6.02dB
–12.04dB –18.06dB –24.08dB
–30.1dB
–36.12dB –42.14dB
VINP 3
R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
20Ω1
COMM 4
1NOMINAL
VALUES.
00539-001
R-2R LADDER NETWORK
Figure 1.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD603
TABLE OF CONTENTS
Specifications..................................................................................... 3
Using the AD603 in Cascade ........................................................ 14
Absolute Maximum Ratings............................................................ 4
Sequential Mode (Optimal S/N Ratio).................................... 14
ESD Caution.................................................................................. 4
Parallel Mode (Simplest Gain Control Interface) .................. 16
Pin Configuration and Function Descriptions............................. 5
Low Gain Ripple Mode (Minimum Gain Error) ................... 16
Typical Performance Characteristics ............................................. 6
Applications..................................................................................... 18
Theory of Operation ...................................................................... 11
A Low Noise AGC Amplifier .................................................... 18
Noise Performance ..................................................................... 11
Caution ........................................................................................ 19
The Gain Control Interface....................................................... 12
Outline Dimensions ....................................................................... 20
Programming the Fixed-Gain Amplifier
Using Pin Strapping ................................................................... 12
Ordering Guide .......................................................................... 20
REVISION HISTORY
3/05—Rev. F to Rev. G
Updated Format.................................................................. Universal
Change to Features ............................................................................1
Changes to General Description .....................................................1
Change to Figure 1 ............................................................................1
Changes to Specifications .................................................................3
New Figure 4 and Renumbering Subsequent Figures...................6
Change to Figure 10 ..........................................................................7
Change to Figure 23 ..........................................................................9
Change to Figure 29 ........................................................................12
Updated Outline Dimensions ........................................................20
4/04—Rev. E to Rev. F
Changes to Specifications .................................................................2
Changes to Ordering Guide .............................................................3
8/03—Rev. D to Rev E
Updated Format.................................................................. Universal
Changes to Specifications .................................................................2
Changes to TPCs 2, 3, 4.....................................................................4
Changes to Sequential Mode (Optimal S/N Ratio) section .........9
Change to Figure 8 ..........................................................................10
Updated Outline Dimensions ........................................................14
Rev. G | Page 2 of 20
AD603
SPECIFICATIONS
@ TA = 25°C, VS = ±5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB gain range, RL = 500 Ω, and CL = 5 pF, unless otherwise
noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Noise Spectral Density1
Noise Figure
1 dB Compression Point
Peak Input Voltage
OUTPUT CHARACTERISTICS
−3 dB Bandwidth
Slew Rate
Peak Output2
Output Impedance
Output Short-Circuit Current
Group Delay Change vs. Gain
Group Delay Change vs. Frequency
Differential Gain
Differential Phase
Total Harmonic Distortion
Third Order Intercept
ACCURACY
Gain Accuracy, f = 100 kHz; Gain (dB) = (40 VG + 10) dB
TMIN to TMAX
Gain, f = 10.7 MHz
Output Offset Voltage3
TMIN to TMAX
Output Offset Variation vs. VG
TMIN to TMAX
GAIN CONTROL INTERFACE
Gain Scaling Factor
TMIN to TMAX
Conditions
Min
Typ
Max
Unit
Pin 3 to Pin 4
97
100
2
1.3
8.8
−11
±1.4
103
Ω
pF
nV/√Hz
dB
dBm
V
Input short-circuited
f = 10 MHz, gain = max, RS = 10 Ω
f = 10 MHz, gain = max, RS = 10 Ω
VOUT = 100 mV rms
RL ≥ 500 Ω
RL ≥ 500 Ω
f ≤ 10 MHz
f = 3 MHz; full gain range
VG = 0 V; f = 1 MHz to 10 MHz
f = 10 MHz, VOUT = 1 V rms
f = 40 MHz, gain = max, RS = 50 Ω
−500 mV ≤ VG ≤ +500 mV,
VG = -0.5 V
VG = 0.0 V
VG = 0.5 V
VG = 0 V
−500 mV ≤ VG ≤ +500 mV
100 kHz
10.7 MHz
GNEG, GPOS Voltage Range4
Input Bias Current
Input Offset Current
Differential Input Resistance
Response Rate
POWER SUPPLY
Specified Operating Range
Quiescent Current
TMIN to TMAX
±2.5
−1
−1.5
−10.3
+9.5
+29.3
−20
−30
−20
−30
39.4
38
38.7
−1.2
90
275
±3.0
2
50
±2
±2
0.2
0.2
−60
15
±0.5
−9.0
+10.5
+30.3
40
39.3
MHz
V/µs
V
Ω
mA
ns
ns
%
Degree
dBc
dBm
+1
+1.5
−8.0
+11.5
+31.3
+20
+30
+20
+30
dB
dB
dB
dB
dB
mV
mV
mV
mV
40.6
42
39.9
+2.0
dB/V
dB/V
dB/V
V
nA
nA
MΩ
dB/µs
±6.3
17
20
V
mA
mA
200
10
50
80
Pin 1 to Pin 2
Full 40 dB gain change
±4.75
12.5
1
±2
Typical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. This figure includes the effects of both voltage
and current noise sources.
2
Using resistive loads of 500 Ω or greater, or with the addition of a 1 kΩ pull-down resistor when driving lower loads.
3
The dc gain of the main amplifier in the AD603 is ×35.7; thus, an input offset of 100 µV becomes a 3.57 mV output offset.
4
GNEG and GPOS, gain control, and voltage range are guaranteed to be within the range of −VS + 4.2 V to +VS − 3.4 V over the full temperature range of −40°C to +85°C.
Rev. G | Page 3 of 20
AD603
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage ±VS
Internal Voltage VINP (Pin 3)
GPOS, GNEG (Pins 1, 2)
Internal Power Dissipation1
Operating Temperature Range
AD603A
AD603S
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
1
Rating
±7.5 V
±2 V Continuous
±VS for 10 ms
±VS
400 mW
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +85°C
−55°C to +125°C
−65°C to +150°C
300°C
Thermal Characteristics:
8-Lead SOIC Package: θJA = 155°C/W, θJC = 33°C/W,
8-Lead CERDIP Package: θJA = 140°C/W, θJC = 15°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. G | Page 4 of 20
AD603
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VINP 3
8
VPOS
GPOS 1
7
VOUT
GNEG 2
6 VNEG
TOP VIEW
COMM 4 (Not to Scale) 5 FDBK
7
Figure 3. 8-Lead Ceramic CERDIP (Q) Package
Table 3. Pin Function Descriptions
Mnemonic
GPOS
GNEG
VINP
COMM
FDBK
VNEG
VOUT
VPOS
VPOS
VOUT
TOP VIEW
6 VNEG
(Not to Scale)
5 FDBK
COMM 4
VINP 3
Figure 2. 8-Lead Plastic SOIC (R) Package
Pin No.
1
2
3
4
5
6
7
8
8
AD603
00539-003
AD603
00539-002
GPOS 1
GNEG 2
Description
Gain Control Input High (Positive Voltage Increases Gain).
Gain Control Input Low (Negative Voltage Increases Gain).
Amplifier Input.
Amplifier Ground.
Connection to Feedback Network.
Negative Supply Input.
Amplifier Output.
Positive Supply Input.
Rev. G | Page 5 of 20
AD603
TYPICAL PERFORMANCE CHARACTERISTICS
@ TA = 25°C, VS = ±5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB gain range, RL = 500 Ω, and CL = 5 pF, unless otherwise
noted.
225
3
180
2
135
1
0
GAIN (dB)
10.7MHz
10
PHASE
100kHz
0
VG (V)
0.2
0.4
0.6
–45
–3
–90
–4
–135
–5
–180
10M
FREQUENCY (Hz)
100M
Figure 7. Frequency and Phase Response vs. Gain
(Gain = +10 dB, PIN = −30 dBm)
Figure 4. Gain vs. VG at 100 kHz and 10.7 mHz
2.5
45MHz
2.0
–225
1M
1.5
4
225
3
180
2
135
1
1.0
90
GAIN
70MHz
GAIN (dB)
0
10.7MHz
0.5
45
0
–1
PHASE
–2
–45
–3
–90
–4
–135
–1.0
–5
–180
–1.5
–0.5
–6
100k
0
455kHz
–0.5
–0.4
–0.3
–0.2 –0.1
0
0.1
0.2
GAIN VOLTAGE (Volts)
0.3
0.4
0.5
00539-005
70MHz
PHASE (Degrees)
–0.2
–2
–6
100k
00539-004
–0.4
0
–1
0
–10
–0.6
45
–225
1M
10M
FREQUENCY (Hz)
00539-008
GAIN (dB)
20
GAIN ERROR (dB)
90
GAIN
PHASE (Degrees)
30
4
00539-007
40
100M
Figure 8. Frequency and Phase Response vs. Gain
(Gain = +30 dB, PIN = −30 dBm)
Figure 5. Gain Error vs. Gain Control Voltage at 455 kHz,
10.7 MHz, 45 MHz, 70 MHz
4
225
3
180
2
135
7.60
7.40
PHASE
–2
–45
–3
–90
–4
–135
–5
–180
–6
100k
–225
1M
10M
FREQUENCY (Hz)
100M
PHASE (Degrees)
0
–1
7.20
7.00
6.80
6.60
00539-006
GAIN (dB)
45
GROUP DELAY (ns)
90
GAIN
0
6.40
–0.6
–0.4
–0.2
0
0.2
GAIN CONTROL VOLTAGE (V)
0.4
Figure 9. Group Delay vs. Gain Control Voltage
Figure 6. Frequency and Phase Response vs. Gain
(Gain = −10 dB, PIN = −30 dBm)
Rev. G | Page 6 of 20
0.6
00539-009
1
AD603
–1.0
8
3
2
4
1
10×
PROBE
HP3585A
SPECTRUM
ANALYZER
511Ω
6
0.1µF
00539-010
–5V
DATEL
DVC 8500
–1.8
–2.0
–2.2
–2.4
–2.6
–2.8
–3.0
–3.2
–3.4
0
Figure 10. Third Order Intermodulation Distortion Test Setup
50
100
200
500
1000
LOAD RESISTANCE (Ω)
2000
Figure 13. Typical Output Voltage Swing vs. Load Resistance
(Negative Output Swing Limits First)
10dB/DIV
00539-011
INPUT IMPEDANCE (Ω)
102
100
98
96
94
100k
Figure 11. Third Order Intermodulation Distortion at 455 kHz
(10× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, PIN = 0 dBm)
1M
10M
FREQUENCY (Hz)
100M
00539-014
100Ω
7
–1.6
Figure 14. Input Impedance vs. Frequency (Gain = −10 dB)
10dB/DIV
00539-012
INPUT IMPEDANCE (Ω)
102
100
98
96
94
100k
Figure 12. Third Order Intermodulation Distortion at 10.7 MHz
(10× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, PIN = 0 dBm)
Rev. G | Page 7 of 20
1M
10M
FREQUENCY (Hz)
100M
Figure 15. Input Impedance vs. Frequency (Gain = +10 dB)
00539-015
5
AD603
–1.4
00539-013
0.1µF
+5V
HP3326A
DUALCHANNEL
SYNTHESIZER
NEGATIVE OUTPUT VOLTAGE (V)
–1.2
AD603
3V
INPUT IMPEDANCE (Ω)
102
INPUT GND
100MV/DIV
100
98
1V
OUTPUT GND
1V/DIV
96
1M
10M
FREQUENCY (Hz)
100M
Figure 16. Input Impedance vs. Frequency (Gain = +30 dB)
–2V
–49ns
50ns
451ns
00539-019
100k
00539-016
94
Figure 19. Output Stage Overload Recovery Time
(Input Is 500 ns Period, 50% Duty Cycle Square Wave, Output is Captured
Using Tektronix 11402 Digitizing Oscilloscope)
3.5V
1V
INPUT
500mV/DIV
100
90
GND
500mV
OUTPUT
500mV/DIV
GND
–1.5V
–44ns
Figure 17. Gain Control Channel Response Time
50ns
00539-020
200ns
1V
00539-017
10
0%
456ns
Figure 20. Transient Response, G = 0 dB
(Input is 500 ns Period, 50% Duty Cycle Square Wave, Output is Captured
Using Tektronix 11402 Digitizing Oscilloscope)
4.5V
3.5V
INPUT GND
1V/DIV
INPUT GND
100mV/DIV
500mV
500mV
OUTPUT GND
500mV/DIV
50ns
451ns
Figure 18. Input Stage Overload Recovery Time
(Input is 500 ns Period, 50% Duty Cycle Square Wave, Output is Captured
Using Tektronix 11402 Digitizing Oscilloscope)
–1.5V
–44ns
50ns
456ns
00539-021
–500mV
–49ns
00539-018
OUTPUT GND
500mV/DIV
Figure 21. Transient Response, G = +20 dB
(Input is 500 ns Period, 50% Duty Cycle Square Wave, Output is Captured
Using Tektronix 11402 Digitizing Oscilloscope)
Rev. G | Page 8 of 20
AD603
21
0
TA = 25°C
RS = 50Ω
TEST SETUP FIGURE 23
10MHz
19
–10
17
NOISE FIGURE (dB)
PSRR (dB)
–20
–30
–40
–50
–60
20MHz
15
13
11
9
10M
FREQUENCY (Hz)
100M
5
30
31
32
33
34
35
36
GAIN (dB)
0
8
3
50Ω
5
AD603
100Ω
7
2
4
HP3585A
SPECTRUM
ANALYZER
1
6
0.1µF
TA = 25°C
TEST SETUP FIGURE 23
–10
–15
00539-023
DATEL
DVC 8500
–25
10
Figure 23. Test Setup Used for: Noise Figure, Third Order Intercept and
1 dB Compression Point Measurements
21
30
50
INPUT FREQUENCY (MHz)
70
Figure 26. 1 dB Compression Point, −10 dB/+30 dB Mode, Gain = +30 dB
20
TA = 25°C
RS = 50V
TEST SETUP FIGURE 23
70MHz
40
–20
–5V
23
39
–5
0.1µF
INPUT LEVEL (dBm)
HP3326A
DUALCHANNEL
SYNTHESIZER
38
Figure 25. Noise Figure in 0 dB/40 dB Mode
Figure 22. PSRR vs. Frequency
(Worst Case is Negative Supply PSRR, Shown Here)
+5V
37
00539-026
1M
00539-022
100k
00539-025
7
TA = 25°C
TEST SETUP FIGURE 23
18
OUTPUT LEVEL (dBm)
30MHz
17
50MHz
15
13
30MHz
11
10MHz
9
16
40MHz
14
12
70MHz
10
5
20
21
22
23
24
25
26
GAIN (dB)
27
28
29
30
0
–20
Figure 24. Noise Figure in −10 dB/+30 dB Mode
–10
INPUT LEVEL (dBm)
0
00539-027
7
00539-024
NOISE FIGURE (dB)
19
Figure 27. Third Order Intercept −10 dB/+30 dB Mode, Gain = +10 dB
Rev. G | Page 9 of 20
AD603
20
18
16
40MHz
14
12
70MHz
10
8
–40
–30
INPUT LEVEL (dBm)
–20
00539-028
OUTPUT LEVEL (dBm)
30MHz
TA = 25°C
RS = 50Ω
RIN = 50Ω
RL = 100Ω
TEST SETUP FIGURE 23
Figure 28. Third Order Intercept −10 dB/+30 dB Mode, Gain = +30 dB
Rev. G | Page 10 of 20
AD603
THEORY OF OPERATION
The AD603 comprises a fixed-gain amplifier, preceded by a
broadband passive attenuator of 0 dB to 42.14 dB, having a gain
control scaling factor of 40 dB per volt. The fixed gain is lasertrimmed in two ranges, to either 31.07 dB (×35.8) or 50 dB
(×358), or may be set to any range in between using one
external resistor between Pin 5 and Pin 7. Somewhat higher
gain can be obtained by connecting the resistor from Pin 5 to
common, but the increase in output offset voltage limits the
maximum gain to about 60 dB. For any given range, the
bandwidth is independent of the voltage-controlled gain. This
system provides an underrange and overrange of 1.07 dB in all
cases; for example, the overall gain is −11.07 dB to +31.07 dB in
the maximum bandwidth mode (Pin 5 and Pin 7 strapped).
This X-AMP structure has many advantages over former
methods of gain control based on nonlinear elements. Most
importantly, the fixed-gain amplifier can use negative feedback
to increase its accuracy. Since large inputs are first attenuated,
the amplifier input is always small. For example, to deliver a
±1 V output in the −1 dB/+41 dB mode (that is, using a fixed
amplifier gain of 41.07 dB) its input is only 8.84 mV; thus the
distortion can be very low. Equally important, the small-signal
gain and phase response, and thus the pulse response, are
essentially independent of gain.
Figure 29 is a simplified schematic. The input attenuator is a
seven-section R-2R ladder network, using untrimmed resistors
of nominally R = 62.5 Ω, which results in a characteristic
resistance of 125 Ω ±20%. A shunt resistor is included at the
input and laser trimmed to establish a more exact input
resistance of 100 Ω ±3%, which ensures accurate operation
(gain and HP corner frequency) when used in conjunction with
external resistors or capacitors.
The nominal maximum signal at input VINP is 1 V rms (±1.4 V
peak) when using the recommended ±5 V supplies, although
operation to ±2 V peak is permissible with some increase in HF
distortion and feedthrough. Pin 4 (COMM) must be connected
directly to the input ground; significant impedance in this
connection will reduce the gain accuracy.
The signal applied at the input of the ladder network is
attenuated by 6.02 dB by each section; thus, the attenuation to
each of the taps is progressively 0 dB, 6.02 dB, 12.04 dB,
18.06 dB, 24.08 dB, 30.1 dB, 36.12 dB, and 42.14 dB. A unique
circuit technique is employed to interpolate between these tap
points, indicated by the slider in Figure 29, thus providing
continuous attenuation from 0 dB to 42.14 dB. It will help in
understanding the AD603 to think in terms of a mechanical
means for moving this slider from left to right; in fact, its
position is controlled by the voltage between Pin 1 and Pin 2.
The details of the gain control interface are discussed later.
The gain is at all times very exactly determined, and a linear-indB relationship is automatically guaranteed by the exponential
nature of the attenuation in the ladder network (the X-AMP
principle). In practice, the gain deviates slightly from the ideal
law, by about ±0.2 dB peak (see, for example, Figure 5).
NOISE PERFORMANCE
An important advantage of the X-AMP is its superior noise
performance. The nominal resistance seen at inner tap points is
41.7 Ω (one third of 125 Ω), which exhibits a Johnson noise
spectral density (NSD) of 0.83 nV/√Hz (that is, √4kTR) at 27°C,
which is a large fraction of the total input noise. The first stage
of the amplifier contributes a further 1 nV/√Hz, for a total input
noise of 1.3 nV/√Hz. It will be apparent that it is essential to use
a low resistance in the ladder network to achieve the very low
specified noise level. The signal’s source impedance forms a
voltage divider with the AD603’s 100 Ω input resistance. In
some applications, the resulting attenuation may be
unacceptable, requiring the use of an external buffer or
preamplifier to match a high impedance source to the low
impedance AD603.
The noise at maximum gain (that is, at the 0 dB tap) depends on
whether the input is short-circuited or open-circuited: when
shorted, the minimum NSD of slightly over 1 nV/√Hz is
achieved; when open, the resistance of 100 Ω looking into the
first tap generates 1.29 nV/√Hz, so the noise increases to a total
of 1.63 nV/√Hz. (This last calculation would be important if the
AD603 were preceded by, for example, a 900 Ω resistor to allow
operation from inputs up to 10 V rms.) As the selected tap
moves away from the input, the dependence of the noise on
source impedance quickly diminishes.
Apart from the small variations just discussed, the signal-tonoise (S/N) ratio at the output is essentially independent of the
attenuator setting. For example, on the −11 dB/+31 dB range,
the fixed gain of ×35.8 raises the output NSD to 46.5 nV/√Hz.
Thus, for the maximum undistorted output of 1 V rms and a
1 MHz bandwidth, the output S/N ratio would be 86.6 dB, that
is, 20 log (1 V/46.5 µV).
Rev. G | Page 11 of 20
AD603
VPOS 8
SCALING
REFERENCE
PRECISION PASSIVE
INPUT ATTENUATOR
FIXED-GAIN
AMPLIFIER
VNEG 6
GPOS 1
7
VOUT
5
FDBK
VG
GNEG 2
6.44kΩ1
AD603
GAINCONTROL
INTERFACE
694Ω1
0dB
–6.02dB
–12.04dB –18.06dB –24.08dB
–30.1dB
–36.12dB –42.14dB
VINP 3
R
R
2R
R
2R
R
R
2R
2R
R
2R
R
2R
20Ω1
R
COMM 4
1NOMINAL
VALUES.
00539-029
R-2R LADDER NETWORK
Figure 29. Simplified Block Diagram
THE GAIN CONTROL INTERFACE
The attenuation is controlled through a differential, high
impedance (50 MΩ) input, with a scaling factor which is lasertrimmed to 40 dB per volt, that is, 25 mV/dB. An internal band
gap reference ensures stability of the scaling with respect to
supply and temperature variations.
When the differential input voltage VG = 0 V, the attenuator
slider is centered, providing an attenuation of 21.07 dB. For the
maximum bandwidth range, this results in an overall gain of
10 dB (= −21.07 dB + 31.07 dB). When the control input is
−500 mV, the gain is lowered by 20 dB (= 0.500 V × 40 dB/V) to
−10 dB; when set to +500 mV, the gain is increased by 20 dB to
30 dB. When this interface is overdriven in either direction, the
gain approaches either −11.07 dB (= − 42.14 dB + 31.07 dB) or
31.07 dB (= 0 + 31.07 dB), respectively. The only constraint on
the gain control voltage is that it be kept within the commonmode range (−1.2 V to +2.0 V assuming +5 V supplies) of the
gain control interface.
The basic gain of the AD603 can thus be calculated using the
following simple expression:
Gain (dB) = 40 VG +10
(1)
where VG is in volts. When Pin 5 and Pin 7 are strapped (see
next section), the gain becomes
For example, if the gain is to be controlled by a DAC providing
a positive only ground-referenced output, the Gain Control Low
(GNEG) pin should be biased to a fixed offset of 500 mV to set
the gain to −10 dB when Gain Control High (GPOS) is at zero,
and to 30 dB when at 1.00 V.
It is a simple matter to include a voltage divider to achieve other
scaling factors. When using an 8-bit DAC having an FS output
of 2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)
would result in a gain-setting resolution of 0.2 dB/bit. The use
of such offsets is valuable when two AD603s are cascaded, when
various options exist for optimizing the S/N profile, as will be
shown later.
PROGRAMMING THE FIXED-GAIN AMPLIFIER
USING PIN STRAPPING
Access to the feedback network is provided at Pin 5 (FDBK).
The user may program the gain of the AD603’s output amplifier
using this pin, as shown in Figure 30, Figure 31, and Figure 32.
There are three modes: in the default mode, FDBK is
unconnected, providing the range +9 dB/+51 dB; when VOUT
and FDBK are shorted, the gain is lowered to −11 dB/+31 dB;
and when an external resistor is placed between VOUT and FDBK
any intermediate gain can be achieved, for example, −1 dB/+41
dB. Figure 33 shows the nominal maximum gain vs. external
resistor for this mode.
Gain (dB) = 40 VG + 20 for 0 to +40 dB
and
VC1
1
GPOS
VPOS 8
VPOS
AD603
(2)
The high impedance gain control input ensures minimal
loading when driving many amplifiers in multiple channel or
cascaded applications. The differential capability provides
flexibility in choosing the appropriate signal levels and
polarities for various control schemes.
Rev. G | Page 12 of 20
VC2
VIN
2
GNEG
VOUT 7
3
VINP
VNEG 6
4
COMM
FDBK 5
VOUT
VNEG
Figure 30. −10 dB to +30 dB; 90 MHz Bandwidth
00539-030
Gain (dB) = 40 VG + 30 for +10 to +50 dB
AD603
VC1
1
VPOS 8
GPOS
Optionally, when a resistor is placed from FDBK to COMM,
higher gains can be achieved. This fourth mode is of limited
value because of the low bandwidth and the elevated output
offsets; it is thus not included in Figure 30, Figure 31, or
Figure 32.
VPOS
AD603
VC2
VIN
2
GNEG
VOUT 7
3
VINP
VNEG 6
4
COMM
FDBK 5
VOUT
VNEG
2.15kΩ
The gain of this amplifier in the first two modes is set by the
ratio of on-chip laser-trimmed resistors. While the ratio of these
resistors is very accurate, the absolute value of these resistors
can vary by as much as ±20%. Thus, when an external resistor is
connected in parallel with the nominal 6.44 kΩ ±20% internal
resistor, the overall gain accuracy is somewhat poorer. The
worst-case error occurs at about 2 kΩ (see Figure 34).
00539-031
5.6pF
Figure 31. 0 dB to 40 dB; 30 MHz Bandwidth
VC1
1
VPOS 8
GPOS
VPOS
AD603
VC2
VIN
2
GNEG
VOUT 7
3
VINP
VNEG 6
VOUT
1.2
VNEG
–1:VdB (OUT) – (–1):VdB (OREF)
1.0
FDBK 5
18pF
0.8
0.6
0.4
DECIBELS
Figure 32. 10 dB to 50 db; 9 MHz to Set Gain
52
0
–0.2
–0.4
–1:VdB (OUT)
48
–0.6
46
–0.8
44
–1.0
10
VdB (OUT)
42
–2:VdB (OUT)
40
1k
10k
100k
1M
Figure 34. Worst-Case Gain Error, Assuming Internal Resistors have a
Maximum Tolerance of −20% (Top Curve) or =20% (Bottom Curve)
38
36
34
32
30
10
VdB (OUT) – VdB (OREF)
100
REXT (Ω)
100
1k
10k
REXT (Ω)
100k
1M
00539-033
DECIBELS
50
0.2
00539-034
COMM
00539-032
4
Figure 33. Gain vs. REXT, Showing Worst-Case Limits Assuming Internal
Resistors have a Maximum Tolerance of 20%
While the gain bandwidth product of the fixed-gain amplifier is
about 4 GHz, the actual bandwidth is not exactly related to the
maximum gain. This is because there is a slight enhancing of
the ac response magnitude on the maximum bandwidth range,
due to higher order poles in the open-loop gain function; this
mild peaking is not present on the higher gain ranges. Figure 30,
Figure 31, and Figure 32 show how an optional capacitor may
be added to extend the frequency response in high gain modes.
Rev. G | Page 13 of 20
AD603
USING THE AD603 IN CASCADE
be provided by resistive dividers operating from a common
voltage reference.
Two or more AD603s can be connected in series to achieve
higher gain. Invariably, ac coupling must be used to prevent the
dc offset voltage at the output of each amplifier from
overloading the following amplifier at maximum gain. The
required high-pass coupling network will usually be just a
capacitor, chosen to set the desired corner frequency in
conjunction with the well-defined 100 Ω input resistance of the
following amplifier.
90
85
S/N RATIO (dB)
80
For two AD603s, the total gain control range becomes 84 dB
(2 × 42.14 dB); the overall −3 dB bandwidth of cascaded stages
will be somewhat reduced. Depending on the pin strapping, the
gain and bandwidth for two cascaded amplifiers can range from
−22 dB to +62 dB (with a bandwidth of about 70 MHz) to
+22 dB to +102 dB (with a bandwidth of about 6 MHz).
70
65
60
55
50
–0.2
In the sequential mode of operation, the ISNR is maintained at
its highest level for as much of the gain control range as
possible. Figure 35 shows the SNR over a gain range of −22 dB
to +62 dB, assuming an output of 1 V rms and a 1 MHz
bandwidth; Figure 36, Figure 37, and Figure 38 show the general
connections to accomplish this. Here, both the positive gain
control inputs (GPOS) are driven in parallel by a positive-only,
ground-referenced source with a range of 0 V to +2 V, while the
negative gain control inputs (GNEG) are biased by stable
voltages to provide the needed gain offsets. These voltages may
Gain (dB) = 40 VG + GO
A2
31.07dB
–42.14dB
GPOS
GNEG
VG2
VO1 = 0.473V
31.07dB
OUTPUT
–20dB
VO2 = 1.526V
00539-036
VG1
VC = 0V
Figure 36. AD603 Gain Control Input Calculations for Sequential Control Operation VC = 0 V
31.07dB
0dB
GPOS
GNEG
VG1
VC = 1.0V
–11.07dB
31.07dB
VO1 = 0.473V
–42.14dB
GPOS
GNEG
VG2
31.07dB
OUTPUT
20dB
VO2 = 1.526V
Figure 37. AD603 Gain Control Calculations for Sequential Control Operation VC = 1.0 V
Rev. G | Page 14 of 20
00539-037
0dB
INPUT
0dB
1.8
2.2
(3)
–51.07dB
–8.93dB
GNEG
1.4
where VG is the applied control voltage and GO is determined by
the gain range chosen. In the explanatory notes that follow, it is
assumed the maximum bandwidth connections are used, for
which GO is −20 dB.
A1
–42.14dB
1.0
VC (V)
The gains are offset (Figure 39) such that A2’s gain is increased
only after A1’s gain has reached its maximum value. Note that
for a differential input of –600 mV or less, the gain of a single
amplifier (A1 or A2) will be at its minimum value of −11.07 dB;
for a differential input of +600 mV or more, the gain will be at
its maximum value of 31.07 dB. Control inputs beyond these
limits will not affect the gain and can be tolerated without
damage or foldover in the response. This is an important aspect
of the AD603’s gain control response. (See the Specifications
section for more details on the allowable voltage range.) The
gain is now
–40.00dB
GPOS
0.6
Figure 35. SNR vs. Control Voltage–Sequential Control (1 MHz Bandwidth)
SEQUENTIAL MODE (OPTIMAL S/N RATIO)
INPUT
0dB
0.2
00539-035
There are several ways of connecting the gain control inputs in
cascaded operation. The choice depends on whether it is
important to achieve the highest possible instantaneous signalto-noise ratio (ISNR), or, alternatively, to minimize the ripple in
the gain error. The following examples feature the AD603
programmed for maximum bandwidth; the explanations apply
to other gain/bandwidth combinations with appropriate
changes to the arrangements for setting the maximum gain.
75
AD603
–28.93dB
31.07dB
0dB
INPUT
0dB
GPOS
GNEG
VG1
VC = 2.0V
31.07dB
–2.14dB
GPOS
GNEG
VG2
VO1 = 0.473V
OUTPUT
60dB
31.07dB
VO2 = 1.526V
00539-038
0dB
Figure 38. AD603 Gain Control Input Calculations for Sequential Operation VC = 2.0 V
70
+31.07dB
60
+31.07dB
COMBINED
50
A2
–11.07dB
GAIN
(dB) –22.14
0
–20
1GAIN
1.526
0.5
0
1.0
20
1.50
40
2.0
60
VC (V)
62.14
OFFSET OF 1.07dB, OR 26.75mV.
00539-039
0.473
OVERALL GAIN (dB)
1
–11.07dB
–8.93dB
40
A1
30
20
10
0
A2
–10
Figure 39. Explanation of Offset Calibration for Sequential Control
–20
With reference to Figure 36, Figure 37, and Figure 38, note that
VG1 refers to the differential gain control input to A1, and VG2
refers to the differential gain control input to A2. When VG is 0,
VG1 = −473 mV and thus the gain of A1 is −8.93 dB (recall that
the gain of each individual amplifier in the maximum
bandwidth mode is –10 dB for VG = −500 mV and 10 dB for VG
= 0 V); meanwhile, VG2 = −1.908 V so the gain of A2 is pinned at
−11.07 dB. The overall gain is thus –20 dB. See Figure 36.
0.2
0.6
1.0
VC
1.4
1.8
2.0
Figure 40. Plot of Separate and Overall Gains in Sequential Control
90
80
70
S/N RATIO (dB)
When VG = +1.00 V, VG1 = 1.00 V − 0.473 V = +0.526 V, which
sets the gain of A1 to at nearly its maximum value of 31.07 dB,
while VG2 = 1.00 V − 1.526 V = 0.526 V, which sets A2’s gain at
nearly its minimum value of −11.07 dB. Close analysis shows
that the degree to which neither AD603 is completely pushed to
its maximum nor minimum gain exactly cancels in the overall
gain, which is now +20 dB. See Figure 37.
–30
–0.2
00539-040
1
A1
When VG = 2.0 V, the gain of A1 is pinned at 31.07 dB and that
of A2 is near its maximum value of 28.93 dB, resulting in an
overall gain of 60 dB (see Figure 38). This mode of operation is
further clarified by Figure 40, which is a plot of the separate
gains of A1 and A2 and the overall gain vs. the control voltage.
Figure 41 is a plot of the SNR of the cascaded amplifiers vs. the
control voltage. Figure 42 is a plot of the gain error of the
cascaded stages vs. the control voltages.
Rev. G | Page 15 of 20
60
50
40
30
20
10
–0.2
0.2
0.6
1.0
VC
1.4
1.8
Figure 41. SNR for Cascaded Stages—Sequential Control
2.0
00539-041
+10dB
+28.96dB
90
1.5
85
1.0
80
0.5
75
0
–0.5
70
65
–1.0
60
–1.5
55
–2.0
–0.2
0
0.2
0.4
0.6
0.8
1.0
VC
1.2
1.4
1.6
1.8
2.0
2.2
50
–0.2
0.2
0.4
0.6
0.8
1.0
1.2
VC
Figure 42. Gain Error for Cascaded Stages–Sequential Control
Figure 44. ISNR for Cascaded Stages—Parallel Control
PARALLEL MODE (SIMPLEST GAIN CONTROL
INTERFACE)
LOW GAIN RIPPLE MODE (MINIMUM GAIN ERROR)
In this mode, the gain control of voltage is applied to both
inputs in parallel—the GPOS pins of both A1 and A2 are
connected to the control voltage and the GNEW inputs are
grounded. The gain scaling is then doubled to 80 dB/V,
requiring only a 1.00 V change for an 80 dB change of gain:
Gain = (dB) = 80 VG + GO
0
00539-044
IS/N RATIO (dB)
2.0
00539-042
GAIN ERROR (dB)
AD603
(4)
where, as before, GO depends on the range selected; for example,
in the maximum bandwidth mode, GO is +20 dB. Alternatively,
the GNEG pins may be connected to an offset voltage of
0.500 V, in which case GO is −20 dB.
As can be seen in Figure 42 and Figure 43, the error in the gain
is periodic, that is, it shows a small ripple. (Note that there is
also a variation in the output offset voltage, which is due to the
gain interpolation, but this is not exact in amplitude.) By
offsetting the gains of A1 and A2 by half the period of the
ripple, that is, by 3 dB, the residual gain errors of the two
amplifiers can be made to cancel. Figure 45 shows much lower
gain ripple when configured in this manner. Figure 46 plots the
ISNR as a function of gain; it is very similar to that in the
parallel mode.
3.0
2.5
2.0
2.0
1.5
1.5
GAIN ERROR (dB)
The amplitude of the gain ripple in this case is also doubled, as
shown in Figure 43, while the instantaneous signal-to-noise
ratio at the output of A2 now decreases linearly as the gain
increases, as shown in Figure 44.
0.5
0
–0.5
–1.0
–1.5
–2.0
1.0
–3.0
–0.1
0
–0.5
0.1
0.2
0.3
0.4
0.5
VC
0.6
0.7
0.8
0.9
1.0
1.1
Figure 45. Gain Error for Cascaded Stages—Low Ripple Mode
–1.0
–1.5
–2.0
–0.2
0
0
0.2
0.4
0.6
0.8
1.0
VC
1.2
1.4
1.6
1.8
2.0
2.2
Figure 43. Gain Error for Cascaded Stages—Parallel Control
Rev. G | Page 16 of 20
00539-045
–2.5
0.5
00539-043
GAIN ERROR (dB)
1.0
AD603
90
85
75
70
65
60
55
50
–0.2
0
0.2
0.4
0.6
0.8
1.0
VC
1.2
00539-046
IS/N RATIO (dB)
80
Figure 46. ISNR vs. Control Voltage—Low Ripple Mode
Rev. G | Page 17 of 20
AD603
APPLICATIONS
A LOW NOISE AGC AMPLIFIER
The circuit operates as follows. A1 and A2 are cascaded.
Capacitor C1 and the 100 Ω of resistance at the input of A1
form a time constant of 10 µs. C2 blocks the small dc offset
voltage at the output of A1 (which might otherwise saturate A2
at its maximum gain) and introduces a high-pass corner at
about 16 kHz, eliminating low frequency noise.
Figure 47 shows the ease with which the AD603 can be
connected as an AGC amplifier. The circuit illustrates many of
the points previously discussed: It uses few parts, has linear-indB gain, operates from a single supply, uses two cascaded
amplifiers in sequential gain mode for maximum S/N ratio, and
an external resistor programs each amplifier’s gain. It also uses a
simple temperature-compensated detector.
A half-wave detector is used, based on Q1 and R8. The current
into capacitor CAV is just the difference between the collector
current of Q2 (biased to be 300 µA at 300 K, 27°C) and the
collector current of Q1, which increases with the amplitude of
the output signal.
The circuit operates from a single 10 V supply. Resistors R1, R2,
R3, and R4 bias the common pins of A1 and A2 at 5 V. This pin
is a low impedance point and must have a low impedance path
to ground, provided here by the 100 µF tantalum capacitors and
the 0.1 µF ceramic capacitors.
The automatic gain control voltage, VAGC, is the time integral of
this error current. In order for VAGC (and thus the gain) to
remain insensitive to short-term amplitude fluctuations in the
output signal, the rectified current in Q1 must, on average,
exactly balance the current in Q2. If the output of A2 is too
small to do this, VAGC will increase, causing the gain to increase,
until Q1 conducts sufficiently.
The cascaded amplifiers operate in sequential gain. Here, the
offset voltage between the Pin 2 (GNEG) of A1 and A2 is 1.05 V
(42.14 dB × 25 mV/dB), provided by a voltage divider
consisting of resistors R5, R6, and R7. Using standard values, the
offset is not exact, but it is not critical for this application.
Consider the case where R8 is zero and the output voltage VOUT
is a square wave at, say, 455 kHz, which is well above the corner
frequency of the control loop.
The gain of both A1 and A2 is programmed by resistors R13
and R14, respectively, to be about 42 dB; thus the maximum
gain of the circuit is twice that, or 84 dB. The gain control range
can be shifted up by as much as 20 dB by appropriate choices of
R13 and R14.
10V
C7
0.1µF
+
C4
0.1µF
5
7
2
A2
AD603
10V
1
C 52
100µF
+
C6
0.1µF
Q1
2N3904
R8
806Ω
5
R1 1
3.83kΩ
5V
R1 2
4.99kΩ
C9
0.1µF
J2
7
2
C10
0.1µF
4
R3
2.49kΩ
R2
2.49kΩ
CAV
0.1µF
6
3
4
R1 4
2.49kΩ
8
C11
0.1µF
1
R4
2.49kΩ
AGC LINE
1V OFFSET FOR
SEQUENTIAL GAIN
R5
5.49kΩ
R7
3.48kΩ
10V
5.5V
1 RT
2C3
R6
1.05kΩ
6.5V
00539-047
C 32
100µF
10V
C2
0.1µF
6
A1
AD603
10V
R1
2.49kΩ
R1 3
2.49kΩ
8
3
R T1
100Ω
C8
0.1µF
R1 0
1.24kΩ
Q2
2N3906
VAGC
10V
C1
0.1µF
J1
R9
1.54kΩ
THIS CAPACITOR SETS
AGC TIME CONSTANT
PR OVI D ES A 5 0Ω IN PU T IMPED A N C E.
A N D C 5 A R E TA N TA LU M.
Figure 47. A Low Noise AGC Amplifier
Rev. G | Page 18 of 20
AD603
During the time VOUT is negative with respect to the base
voltage of Q1, Q1 conducts; when VOUT is positive, it is cut off.
Since the average collector current of Q1 is forced to be 300 µA,
and the square wave has a duty cycle of 1:1, Q1’s collector
current when conducting must be 600 µA. With R8 omitted, the
peak amplitude of VOUT is forced to be just the VBE of Q1 at
600 µA, typically about 700 mV, or 2 VBE peak-to-peak. This
voltage, the amplitude at which the output stabilizes, has a
strong negative temperature coefficient (TC), typically
−1.7 mV/°C. Although this may not be troublesome in some
applications, the correct value of R8 will render the output
stable with temperature.
To understand this, note that the current in Q2 is made to be
proportional to absolute temperature (PTAT). For the moment,
continue to assume that the signal is a square wave.
When Q1 is conducting, VOUT is now the sum of VBE and a
voltage that is PTAT and that can be chosen to have an equal
but opposite TC to that of the VBE. This is actually nothing more
than an application of the band gap voltage reference principle.
When R8 is chosen such that the sum of the voltage across it
and the VBE of Q1 is close to the band gap voltage of about 1.2 V,
VOUT will be stable over a wide range of temperatures, provided,
of course, that Q1 and Q2 share the same thermal environment.
Since the average emitter current is 600 µA during each half
cycle of the square wave, a resistor of 833 Ω would add a PTAT
voltage of 500 mV at 300 K, increasing by 1.66 mV/°C. In
practice, the optimum value will depend on the type of
transistor used and, to a lesser extent, on the waveform for
which the temperature stability is to be optimized; for the
inexpensive 2N3904/2N3906 pair and sine wave signals, the
recommended value is 806 Ω.
This resistor also serves to lower the peak current in Q1 when
more typical signals (usually sinusoidal) are involved, and the
1.8 kHz LP filter it forms with CAV helps to minimize distortion
due to ripple in VAGC. Note that the output amplitude under sine
wave conditions will be higher than for a square wave, since the
average value of the current for an ideal rectifier would be 0.637
times as large, causing the output amplitude to be 1.88
(= 1.2/0.637) V, or 1.33 V rms. In practice, the somewhat
nonideal rectifier results in the sine wave output being regulated
to about 1.4 V rms, or 3.6 V p-p.
The bandwidth of the circuit exceeds 40 MHz. At 10.7 MHz, the
AGC threshold is 100 µV (−67 dBm) and its maximum gain is
83 dB (20 log 1.4 V/100 µV). The circuit holds its output at
1.4 V rms for inputs as low as −67 dBm to +15 dBm (82 dB),
where the input signal exceeds the AD603’s maximum input
rating. For a 30 dBm input at 10.7 MHz, the second harmonic is
34 dB down from the fundamental and the third harmonic is
35 dB down.
CAUTION
Careful component selection, circuit layout, power supply
decoupling, and shielding are needed to minimize the AD603’s
susceptibility to interference from signals such as those from
radio and TV stations. In bench evaluation, it is recommended
to place all of the components into a shielded box and using
feedthrough decoupling networks for the supply voltage. Circuit
layout and construction are also critical, since stray capacitances
and lead inductances can form resonant circuits and are a
potential source of circuit peaking, oscillation, or both.
Rev. G | Page 19 of 20
AD603
OUTLINE DIMENSIONS
0.005 (0.13)
MIN
0.055 (1.40)
MAX
8
5.00 (0.1968)
4.80 (0.1890)
5
0.310 (7.87)
0.220 (5.59)
1
PIN 1
4
0.100 (2.54) BSC
0.060 (1.52)
0.015 (0.38)
0.023 (0.58)
0.014 (0.36)
4
SEATING
0.070 (1.78) PLANE
0.030 (0.76)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
5
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.200 (5.08)
MAX
8
4.00 (0.1574)
3.80 (0.1497) 1
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
0.50 (0.0196)
× 45°
0.25 (0.0099)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 48. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
Figure 49. 8-Lead Standard Small Outline Package [SOIC-N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Part Number
AD603AR
AD603AR-REEL
AD603AR-REEL7
AD603ARZ1
AD603ARZ-REEL1
AD603ARZ-REEL71
AD603AQ
AD603SQ/883B2
AD603-EB
AD603ACHIPS
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
Package Description
8-Lead SOIC
8-Lead SOIC, 13" Reel
8-Lead SOIC, 7" Reel
8-Lead SOIC
8-Lead SOIC, 13" Reel
8-Lead SOIC, 7" Reel
8-Lead CERDIP
8-Lead CERDIP
Evaluation Board
DIE
Z = Pb-free part.
Refer to AD603 Military data sheet. Also available as 5962-9457203MPA.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00539–0–3/05(G)
Rev. G | Page 20 of 20
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
Q-8
Q-8