Features • EE Programmable 65,536 x 1, 131,072 x 1 and 262,144 x 1 bit Serial Memories Designed to Store Configuration Programs for Programmable Gate Arrays • Simple Interface to SRAM FPGAs Requires Only One User I/O Pin • Able to Configure with EPF6000 and EPF8000, Flex 10K FPGAs • Cascadable To Support Additional Configurations or Future Higher-Density Arrays • • • • • • (17C128/256 only) Low-Power CMOS EEPROM Process Programmable Reset Polarity Available in Industry-Standard Pin-Compatible PLCC Package In-System Programmable via 2-Wire Bus Emulation of 24CXX Serial EEPROMs Available in 3.3V and 5V Versions Description The AT17C65/128/256A and AT17LV65/128/256A (AT17A Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17A Series is packaged in the popular 20-pin PLCC. The AT17A Series family uses a simple serial-access provides to configure one or more FPGA devices. The AT17A Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user can select the polarity of the reset function by programming a special EEPROM bit. The AT17A Series is pin compatible with the industry standard configurator, and can be programmed with industry standard programmers. FPGA Configuration EEPROM 65K, 128K and 256K AT17CxxxA AT17LVxxxA Pin Configurations 18 17 16 15 14 9 10 11 12 13 4 5 6 7 8 SER_EN NC NC NC NC CE (nCS) GND NC CEO (nCASC) NC CLK (DCLK) NC NC NC RESET/OE (RESET/OE) 3 2 1 20 19 NC DATA NC VCC NC 20-Pin PLCC Rev. 0996A–07/98 1 Controlling The AT17A Series Serial EEPROMs Most connections between the FPGA device and the serial EEPROM are simple and self-explanatory. • The DATA output of the AT17A Series drives DIN of the FPGA devices. • The master FPGA CCLK output drives the CLK input of the AT17A Series. • The CEO output of any AT17C/LV128/256A drives the CE input of the next AT17C/LV65/128/256 in a cascade chain of PROMs. • SER_EN must be connected to VCC. There are, however, two different ways to use the inputs CE and OE, as shown in the AC Characteristics waveforms. Condition 1 The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configura- Block Diagram 2 AT17A Series tion cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17A Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle. Condition 2 The FPGA D/P output drives only the CE input of the AT17A Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts a configuration before D/P has gone high. A high level on the RESET/OE input to the AT17C/LVxxxA – during FPGA reset – clears the Configurator's internal address pointer, so that the reconfiguration starts at the beginning. The AT17A Series does not require an inverter since the RESET polarity is programmable. AT17A Series Pin Configurations PLCC/S OIC DIP Pin Pin Name I/O Description 2 1 DATA I/O Three-state DATA output for reading. Input/Output pin for programming. 4 2 CLK I 8 3 RESET/OE 9 4 CE 10 5 GND 12 6 CEO O Chip Enable Out output. This signal is asserted low on the clock cycle following the last bit read from the memory. It will stay low as long as CE and OE are both low. It will then follow CE until OE goes high. Thereafter, CEO will stay high until the entire PROM is read again and senses the status of RESET polarity. A2 I Device selection input, A2. This is used to enable (or select) the device during programming and when SER_EN is low (see Programming Guide for more details). I Serial enable is normally high during FPGA loading operations. Bringing SER_EN low, enables the 2-wire serial interface for programming. 18 7 SER_EN 20 8 VCC Clock input. Used to increment the internal address and bit counter for reading and programming. RESET/Output Enable input (when SER_EN is High). A low level on both the CE and RESET/OE inputs enables the data output driver. A high level on RESET/OE resets both the address and bit counters. A logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE. I Chip Enable input. Used for device selection. A low level on both CE and OE enables the data output driver. A high level on CE disables both the address and bit counters and forces te device into a low-power mode. Note this pin will not enable/disable the device in 2-wire serial mode (ie; when SER_EN is low). Ground pin +3.3V/+5V power supply pin. Absolute Maximum Ratings* Operating Temperature .................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ............................. -0.1V to VCC + 0.5V Supply Voltage (VCC) .......................................-0.5 V to + 7.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Soldering Temp. (10 sec. @ 1/16 in.) .............260°C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V 3 FPGA Master Serial Mode Summary The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode. Cascading Serial Configuration EEPROMs (AT17C/LV256A) For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded Configurators provide additional memory (17C/LV128/256A only). After the last bit from the first Configurator is read, the next clock signal to the Configurator asserts its CEO output Low and disables its DATA line. The second Configurator recognizes the low level on its CE input and enables its DATA output. Figure 1. Condition 1 Connection M2 M1 M0 SERIAL EEPROM CE AT17C/LVxxx Reset Polarity The AT17C/LVxxxA lets the user choose the reset polarity as either RESET/OE or RESET/OE. VCC DATA CLK CCLK The programming mode is entered by bringing SER_EN low. In this mode the chip can be programmed by the 2wire interface. The programming is done at V CC supply only. Programming super voltages are generated inside the chip. See the Programming Specification for Atmel’s Configuration Memories Application Note for further information. The AT17C Series parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.0V nominal. The AT17C/LVxxxA enters a low-power standby mode whenever CE is asserted high. In this mode, the Configurator consumes less than 1.0 mA of current. The output remains in a high-impedance state regardless of the state of the OE input. FLEX 10K, FLEX 16K (CLK REQUIRED) D0 Programming Mode Standby Mode REBOOT FPGA After configuration is complete, the address counters of all cascaded Configurators are reset if the reset signal drives the RESET/OE on each Configurator Active. If the address counters are not to be reset upon completion, then the RESET/OE inputs can be tied to ground. For more details, please reference the AT17C Series Programming Guide SER_EN CS RESET/OE CON FLEX DEVICE AT17CXX Operating Conditions AT17Cxxx AT17LVxxx Min/Max Min/Max Units Symbol Description VCC Commercial Supply voltage relative to GND -0°C to +70°C 4.75/5.25 3.0/3.6 V Industrial Supply voltage relative to GND -40°C to +85C° 4.5/5.5 3.0/3.6 V Military Supply voltage relative to GND -55°C to +125C 4.5/5.5 3.0/3.6 V 4 AT17A Series AT17A Series . DC Characteristics VCC = 5V ± 5% Commercial / 5V ± 10% Ind./Mil. Symbol Description Min Max Units VIH High-level input voltage 2.0 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) VOH High-level output voltage (IOH = -4 mA) VOL Low-level output voltage (IOL = +4 mA) 0.4 V ICCA Supply current, active mode 10 mA IL Input or output leakage current (VIN = VCC or GND) 10 µA Commercial 75 µA Industrial/Military 150 µA Commercial 1 mA Industrial/Military 2 mA 3.7 V Commercial 0.32 3.6 V Industrial 0.37 3.5 V V Military -10 Supply current, standby mode AT17C256 ICCS V Supply current, standby mode AT17C128/65 DC Characteristics VCC = 3.3V ± 10% Symbol Description Min Max Units VIH High-level input voltage 2.0 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = -2.5 mA) VOL Low-level output voltage (IOL = +3 mA) VOH High-level output voltage (IOH = -2 mA) VOL Low-level output voltage (IOL = +3 mA) VOH High-level output voltage (IOH = -2 mA) VOL Low-level output voltage (IOL = +2.5 mA) ICCA Supply current, active mode IL Input or output leakage current (VIN = VCC or GND) ICCS Supply current, standby mode 2.4 V Commercial 0.4 2.4 V V Industrial 0.4 2.4 V V Military 0.4 V 5 mA 10 µA Commercial 50 µA Industrial/Military 100 µA -10 5 AC Characteristics AC Characteristics When Cascading 6 AT17A Series AT17A Series . AC Characteristics for AT17C256A VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil Commercial Symbol Description Max Units 25 25 ns CE to Data Delay 45 45 ns CLK to Data Delay 50 55 ns (2) OE to Data Delay tCE(2) tCAC(2) tOE (2) Data Hold From CE, OE, or CLK (3) CE or OE to Data Float Delay tOH tDF Min Max Industrial/Military 0 Min 0 50 ns 50 ns tLC CLK Low Time 20 20 ns tHC CLK High Time 20 20 ns tSCE CE Setup Time to CLK (to guarantee proper counting) 35 40 ns tHCE CE Hold Time to CLk (to guarantee proper counting) 0 0 ns tHOE OE High Time (guarantees counter is reset) 20 20 ns FMAX MAX Input Clock Frequency 12.5 12.5 MHz . AC Characteristics for AT17C256A When Cascading VCC = 5V± 5% Commercial / VCC = 5V ± 10% Ind./Mil Commercial Symbol (3) Description Min Max Industrial/Military Min Max Units CLK to Data Float Delay 50 50 ns tOCK(2) CLK to CEO Delay 35 40 ns tOCE(2) CE to CEO Delay 35 35 ns RESET/OE to CEO Delay 30 35 ns tCDF tOOE (2) Notes: 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pf. 3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady-state active levels. 7 . AC Characteristics for AT17C65/128A VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil. Commercial Symbol Description Max Units 110 150 ns CE to Data Delay 50 50 ns CLK to Data Delay 50 55 ns (2) OE to Data Delay tCE(2) tCAC(2) tOE (2) Data Hold From CE, OE, or CLK (3) CE or OE to Data Float Delay tOH tDF Min Max Industrial/Military 0 Min 0 50 ns 50 ns tLC CLK Low Time 30 35 ns tHC CLK High Time 30 35 ns tSCE CE Setup Time to CLK (to guarantee proper counting) 45 50 ns tHCE CE Hold Time to CLk (to guarantee proper counting) 0 5 ns tHOE OE High Time (guarantees counter is reset) 50 60 ns FMAX(4) MAX Input Clock Frequency 10 10 MHz . AC Characteristics for AT17C128/256A When Cascading VCC = 5V ± 5% Commercial / VCC = 5V ± 10% Ind./Mil. Commercial Symbol (3) Description Min Max Industrial/Military Min Max Units CLK to Data Float Delay 50 50 ns tOCK(2) CLK to CEO Delay 65 75 ns tOCE(2) CE to CEO Delay 55 60 ns RESET/OE to CEO Delay 55 55 ns tCDF tOE (2) Notes: 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pf. 3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady-state active levels. 4. During cascade FMAX = 8 MHz. 8 AT17A Series AT17A Series AC Characteristics VCC = 3.3V ± 10% Commercial Symbol Description Max Units 40 45 ns CE to Data Delay 60 60 ns CLK to Data Delay 75 80 ns (2) OE to Data Delay tCE(2) tCAC(2) tOE (2) Data Hold From CE, OE, or CLK (3) CE or OE to Data Float Delay tOH tDF Min Max Industrial/Military 0 Min 0 55 ns 55 ns tLC CLK Low Time 25 25 ns tHC CLK High Time 25 25 ns tSCE CE Setup Time to CLK (to guarantee proper counting) 35 60 ns tHCE CE Hold Time to CLk (to guarantee proper counting) 0 0 ns tHOE OE High Time (guarantees counter is reset) 25 25 ns FMAX(4) Notes: MAX Input Clock Frequency 10 8 10 MHz 1. Preliminary specifications for military operating range only. 2. AC test lead = 50 pf. 3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady-state active levels. 4. During cascade FMAX = 8 MHz. AC Characteristics When Cascading VCC = 3.3V ± 10% Commercial Symbol Description tCDF(3) Min Max Industrial/Military Min Max Units CLK to Data Float Delay 60 60 ns tOCK (2) CLK to CEO Delay 55 60 ns tOCE (2) CE to CEO Delay 55 60 ns (2) RESET/OE to CEO Delay 40 45 ns tOOE 9 Ordering Information - 5V Devices Memory Size (K) Ordering Code Package 64K AT17C65A-10JC 20J Commercial (0°C to 70°C) AT17C65A-10JI 20J Industrial (-40°C to 85°C) AT17C128A-10JC 20J Commercial (0°C to 70°C) AT17C128A-10JI 20J Industrial (-40°C to 85°C) AT17C256A-10JC 20J Commercial (0°C to 70°C) AT17C256A-10JI 20J Industrial (-40°C to 85°C) 128K 256K Operation Range Ordering Information - 3.3V Devices Memory Size (K) 64K 128K 256K Ordering Code Package AT17LV65A-10JC 20J Commercial (0°C to 70°C) AT17LV65A-10JI 20J Industrial (-40°C to 85°C) AT17LV128A-10JC 20J Commercial (0°C to 70°C) AT17LV128A-10JI 20J Industrial (-40°C to 85°C) AT17LV256A-10JC 20J Commercial (0°C to 70°C) AT17LV256A-10JI 20J Industrial (-40°C to 85°C) Package Type 20J 10 20-Lead, Plastic J-Leaded Chip Carrier (PLCC) AT17A Series Operation Range AT17A Series Packaging Information 20J, 20-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AA 11