CD74HC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS512A − JULY 2003 − REVISED FEBRUARY 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D D 2-V to 6-V VCC Operation D High Noise Immunity NIL or NIH = 30% of MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Buffered Inputs Typical Propagation Delay 7 ns at VCC = 5 V, CL = 15 pF, TA = 25°C Fanout (Over Temperature Range) − Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . . 15 LSTTL Loads Extended Temperature Performance of −40°C to 125°C Balanced Propagation Delay and Transition Times Significant Power Reduction, Compared to LSTTL Logic ICs VCC at VCC = 5 V CMOS Input Compatibility, Il ≤ 1 µA at VOL, VOH D M PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y description/ordering information The CD74HC08 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates, with the low power consumption of standard CMOS integrated circuits. The device can drive 10 LSTTL loads. ORDERING INFORMATION† −40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA SOIC − M Tape and reel TOP-SIDE MARKING CD74HC08QM96Q1 HC08Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H H L X L X L L logic diagram (positive logic) A Y B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74HC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS512A − JULY 2003 − REVISED FEBRUARY 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < −0.5 V or VI > VCC + 0.5 V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < −0.5 V or VO > VCC + 0.5 V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO > −0.5 or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180°C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC Supply voltage VCC = 2 V VIH VCC = 4.5 V High-level High level input voltage VCC = 6 V MIN NOM MAX 2 5 6 3.15 V 4.2 0.5 VCC = 4.5 V Low-level Low level input voltage V 1.5 VCC = 2 V VIL UNIT 1.35 VCC = 6 V V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V ∆t/∆v Input transition rise/fall time TA Operating free-air temperature VCC = 2 V 1000 VCC = 4.5 V 500 VCC = 6 V ns 400 −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74HC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS512A − JULY 2003 − REVISED FEBRUARY 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IO (mA) TEST CONDITIONS CMOS loads VOH VI = VIH or VIL TTL loads CMOS loads VOL VI = VIH or VIL TTL loads II VI = VCC or GND ICC VI = VCC or GND VCC TA = 25°C MIN TYP CD74HC08-Q1 MAX MIN −0.02 2V 1.9 1.9 −0.02 4.5 V 4.4 4.4 −0.02 6V 5.9 5.9 3.7 MAX UNIT V −4 4.5 V 3.98 −5.2 6V 5.48 0.02 2V 0.1 0.1 0.02 4.5 V 0.1 0.1 0.02 6V 0.1 0.1 4 4.5 V 0.26 0.4 5.2 6V 0.26 0.4 6V ±0.1 ±1 µA 2 40 µA 10 10 pF 0 5.2 6V Ci V switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) A or B TO (OUTPUT) CONDITIONS CL = 50 pF Y CL = 15 pF tt Y VCC TA = 25°C MIN CD74HC08-Q1 MAX MIN MAX 2V 90 135 4.5 V 18 27 6V 15 23 2V 75 110 4.5 V 15 22 6V 13 19 5V CL = 50 pF p TYP UNIT ns 7 ns operating characteristics, TA = 25°C, VCC = 5V PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate (see Note 4) No load TYP 37 UNIT pF NOTE 4: Cpd is used to determine the dynamic power consumption, per gate. PD = VCC2 fI (Cpd + CL) fI = input frequency CL = output load capacitance VCC = supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD74HC08-Q1 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCLS512A − JULY 2003 − REVISED FEBRUARY 2008 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC Test Point Input 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr tPHL VCC 50% 10% 0 V Out-of-Phase Output 90% tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 15-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HC08QM96G4Q1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC08QM96Q1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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