Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD23381F4 SLPS450E – OCTOBER 2013 – REVISED MAY 2015 CSD23381F4 12 V P-Channel FemtoFET™ MOSFET 1 Features • • • • 1 • • • • Product Summary Ultra-Low On-Resistance Ultra-Low Qg and Qgd High Operating Drain Current Ultra-Small Footprint (0402 Case Size) – 1.0 mm × 0.6 mm Ultra-Low Profile – 0.35 mm Max Height Integrated ESD Protection Diode – Rated >4 kV HBM – Rated >2 kV CDM Lead and Halogen Free RoHS Compliant TA = 25°C • • UNIT Drain-to-Source Voltage –12 V Qg Gate Charge Total (–4.5 V) 1140 pC Qgd Gate Charge Gate-to-Drain RDS(on) VGS(th) 190 Drain-to-Source OnResistance pC VGS = –1.8 V 480 mΩ VGS = –2.5 V 250 mΩ VGS = –4.5 V 150 mΩ Threshold Voltage –0.95 V . Ordering Information(1) 2 Applications • • TYPICAL VALUE VDS Device Qty CSD23381F4 3000 CSD23381F4T 250 Media Package Ship 7-Inch Reel Femto(0402) 1.0 mm x 0.6 mm Land Grid Array (LGA) Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. Optimized for Load Switch Applications Optimized for General Purpose Switching Applications Battery Applications Handheld and Mobile Applications . Absolute Maximum Ratings TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage –12 V VGS Gate-to-Source Voltage –8 V 3 Description ID Continuous Drain Current(1) –2.3 A This 150 mΩ, 12 V P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing at least a 60% reduction in footprint size. IDM Pulsed Drain Current(2) –9 A Continuous Gate Clamp Current –35 Pulsed Gate Clamp Current(2) –350 Power Dissipation(1) 500 mW Human Body Model (HBM) 4 kV Charged Device Model (CDM) 2 kV . TJ, Tstg –55 to 150 °C Typical Part Dimensions 5m 0.3 m IG PD V(ESD) Operating Junction and Storage Temperature Range mA (1) Typical RθJA = 85°C/W on 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 0.06 inch (1.52 mm) thick FR4 PCB. (2) Pulse duration ≤300 μs, duty cycle ≤2% Top View 60 1. 0. 00 m m D m m . . . G S . 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD23381F4 SLPS450E – OCTOBER 2013 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 7 Mechanical Data..................................................... 8 7.1 7.2 7.3 7.4 Mechanical Dimensions ............................................ 8 Recommended Minimum PCB Layout...................... 9 Recommended Stencil Pattern ................................. 9 CSD23381F4 Embossed Carrier Tape Dimensions .............................................................. 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (September 2014) to Revision E Page • Corrected typo for IDSS Test Condition .................................................................................................................................. 3 • Corrected typo for IGSS Test Condition .................................................................................................................................. 3 Changes from Revision C (July 2014) to Revision D • Corrected timing VDS to read –6 V ......................................................................................................................................... 3 Changes from Revision B (February 2014) to Revision C • Page Page Corrected capacitance units to read pF in Figure 5 ............................................................................................................... 5 Changes from Revision A (January 2014) to Revision B Page • Updated lead and halogen free in features ........................................................................................................................... 1 • Added IG parameter ................................................................................................................................................................ 1 • Lowered IDSS limit.................................................................................................................................................................... 3 • Lowered IGSS limit ................................................................................................................................................................... 3 Changes from Original (October 2013) to Revision A • 2 Page Added small reel info .............................................................................................................................................................. 1 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: CSD23381F4 CSD23381F4 www.ti.com SLPS450E – OCTOBER 2013 – REVISED MAY 2015 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –100 nA –50 nA STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = –250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = –9.6 V IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = –8 V VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = –250 μA RDS(on) Drain-to-Source On-Resistance gƒs Transconductance –12 –0.7 V –0.95 –1.20 VGS = –1.8 V, IDS = –0.1 A 480 970 mΩ VGS = –2.5 V, IDS = –0.5 A 250 300 mΩ VGS = –4.5 V, IDS = –0.5 A 150 175 mΩ VDS = –6 V, IDS = –0.5 A V 2 S 236 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance VGS = 0 V, VDS = –6 V, ƒ = 1 MHz Coss Output Capacitance 98 pF Crss Reverse Transfer Capacitance 6.9 pF RG Series Gate Resistance 20 Ω Qg Gate Charge Total (4.5 V) 1140 pC Qgd Gate Charge Gate-to-Drain 190 pC Qgs Gate Charge Gate-to-Source 300 pC Qg(th) Gate Charge at Vth Qoss Output Charge td(on) VDS = –6 V, IDS = –0.5 A 145 pC 1290 pC Turn On Delay Time 4.5 ns tr Rise Time 3.9 ns td(off) Turn Off Delay Time 18 ns tƒ Fall Time 7 ns VDS = –6 V, VGS = 0 V VDS = –6 V, VGS = –4.5 V, IDS = –0.5 A, RG = 2 Ω DIODE CHARACTERISTICS VSD Diode Forward Voltage Qrr Reverse Recovery Charge ISD = –0.5 A, VGS = 0 V trr Reverse Recovery Time VDS= –10 V, IF = –0.5 A, di/dt = 100 A/μs –0.75 V 1260 pC 7.9 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC RθJA (1) (2) TYPICAL VALUES Junction-to-Ambient Thermal Resistance (1) 85 Junction-to-Ambient Thermal Resistance (2) 245 UNIT °C/W Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Device mounted on FR4 material with minimum Cu mounting area. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: CSD23381F4 3 CSD23381F4 SLPS450E – OCTOBER 2013 – REVISED MAY 2015 www.ti.com 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 5.5 VGS = −4.5V VGS = −2.5V VGS = −1.8V 5 4.5 − IDS - Drain-to-Source Current (A) − IDS - Drain-to-Source Current (A) 5.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 − VDS - Drain-to-Source Voltage (V) 1.8 2 VDS = −5V 5 4.5 4 3.5 3 2.5 2 1.5 TC = 125°C TC = 25°C TC = −55°C 1 0.5 0 0 G001 Figure 2. Saturation Characteristics 4 Submit Documentation Feedback 0.5 1 1.5 2 2.5 3 − VGS - Gate-to-Source Voltage (V) 3.5 4 G001 Figure 3. Transfer Characteristics Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: CSD23381F4 CSD23381F4 www.ti.com SLPS450E – OCTOBER 2013 – REVISED MAY 2015 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 300 ID = −0.5A VDS = −6V 4 270 240 3.5 C − Capacitance (pF) − VGS - Gate-to-Source Voltage (V) 4.5 3 2.5 2 1.5 1 210 150 120 90 60 0.5 0 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 180 30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Qg - Gate Charge (nC) 1 0 1.1 1.2 0 1 2 G001 Figure 4. Gate Charge 12 G001 600 RDS(on) - On-State Resistance (mΩ) ID = −250uA − VGS(th) - Threshold Voltage (V) 11 Figure 5. Capacitance 1.25 1.15 1.05 0.95 0.85 0.75 0.65 0.55 0.45 −75 −25 25 75 125 TC - Case Temperature (ºC) 480 420 360 300 240 180 120 60 0 1 G001 Figure 6. Threshold Voltage vs Temperature 2 3 4 5 6 − VGS - Gate-to- Source Voltage (V) 7 8 G001 Figure 7. On-State Resistance vs Gate-to-Source Voltage 10 − ISD − Source-to-Drain Current (A) VGS = −4.5V, ID = −0.5A 1.3 1.2 1.1 1 0.9 0.8 0.7 −75 TC = 25°C, I D = −0.5A TC = 125°C, I D = −0.5A 540 0 175 1.4 Normalized On-State Resistance 3 4 5 6 7 8 9 10 − VDS - Drain-to-Source Voltage (V) −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 − VSD − Source-to-Drain Voltage (V) G001 Figure 8. Normalized On-State Resistance vs Temperature 1 G001 Figure 9. Typical Diode Forward Voltage Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: CSD23381F4 5 CSD23381F4 SLPS450E – OCTOBER 2013 – REVISED MAY 2015 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 3.0 1ms 10ms 100ms 1s DC − IDS - Drain- to- Source Current (A) − IDS - Drain-to-Source Current (A) 100 10 1 0.1 Single Pulse Typical RthetaJA =245ºC/W(min Cu) 0.01 0.01 0.1 1 10 − VDS - Drain-to-Source Voltage (V) Figure 10. Maximum Safe Operating Area 6 50 2.5 2.0 1.5 1.0 0.5 Typical RthetaJA = 85ºC/W(max Cu) 0.0 −50 G001 −25 0 25 50 75 100 125 TA - AmbientTemperature (ºC) 150 175 G001 Figure 11. Maximum Drain Current vs Temperature Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: CSD23381F4 CSD23381F4 www.ti.com SLPS450E – OCTOBER 2013 – REVISED MAY 2015 6 Device and Documentation Support 6.1 Trademarks FemtoFET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: CSD23381F4 7 CSD23381F4 SLPS450E – OCTOBER 2013 – REVISED MAY 2015 www.ti.com 7 Mechanical Data The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Mechanical Dimensions (1) All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994). (2) This drawing is subject to change without notice. (3) This package is a PB free solder land design. Pin Configuration Position 8 Designation Pin 1 Gate Pin 2 Source Pin 3 Drain Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: CSD23381F4 CSD23381F4 www.ti.com SLPS450E – OCTOBER 2013 – REVISED MAY 2015 7.2 Recommended Minimum PCB Layout (1) All dimensions are in millimeters. 7.3 Recommended Stencil Pattern (1) All dimensions are in millimeters. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: CSD23381F4 9 CSD23381F4 SLPS450E – OCTOBER 2013 – REVISED MAY 2015 www.ti.com 7.4 CSD23381F4 Embossed Carrier Tape Dimensions (1) 10 Pin 1 is oriented in the top-right quadrant of the tape enclosure (quadrant 2), closest to the carrier tape sprocket holes. Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: CSD23381F4 PACKAGE OPTION ADDENDUM www.ti.com 22-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD23381F4 ACTIVE PICOSTAR YJC 3 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 150 DS CSD23381F4T ACTIVE PICOSTAR YJC 3 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 150 DS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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