IDT IDTCSPT857APA 2.5v phase locked loop differential 1:10 sdram clock driver Datasheet

IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
IDTCSPT857/A
DESCRIPTION:
FEATURES:
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK, CLK ) to 10 differential output
pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT,
FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the output frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption device of less than 200µA.
The CSPT857 requires no external components and has been optimised
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycle over the operating voltage and temperature range. The CSPT857,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPT857 is only available in Industrial Temperature Range (-40°C to
+85°C), and CSPT857A is only available in Commercial Temperature Range
(0°C to +70°C). See Ordering Information for details.
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AVDD and 2.5V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packages
FUNCTIONAL BLOCK DIAGRAM
PWRDWN
37/E6
AVDD
16/G2
TEST
MODE
LOGIC
3/A1
Y0
2/A2
Y0
5/B2
6/B1
10/D1
Y1
Y1
Y2
9/D2
Y2
20/J2
Y3
19/J1
Y3
22/K1
Y4
23/K2
CLK
CLK
Y5
14/F2
47/A5
PLL
FBIN
36/F6
FBIN
35/F5
Y4
46/A6
13/F1
44/B5
43/B6
39/D6
40/D5
29/J5
30/J6
27/K6
26/K5
32/H6
33/H5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
OCTOBER 2002
1
c
2002
Integrated Device Technology, Inc.
DSC-5172/8
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
6
Y5
Y6
GND
Y7
PWR
DWN
5
Y5
Y6
GND
Y7
VDDQ FBIN FBOUT GND
FBIN
VDDQ FBOUT
Y8
Y9
Y8
Y9
4
GND VDDQ
NC
NC
NC
NC
VDDQ GND
3
GND VDDQ
NC
NC
NC
NC
VDDQ GND
2
Y0
Y1
GND
Y2
VDDQ
CLK
AVDD GND
Y3
Y4
1
Y0
Y1
GND
Y2
VDDQ
CLK
VDDQ AGND
Y3
Y4
A
B
C
D
E
F
J
K
H
G
VFBGA
TOP VIEW
56 BALL VFBGA PACKAGE LAYOUT
0.65mm
6
5
TOP VIEW
4
3
2
1
A
B
C
D
E
F
G
H
J
K
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
2
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VDDQ, AVDD
Supply Voltage Range
Max
VI(2)
VO(2)
Unit
–0.5 to +3.6
V
Input Voltage Range
Voltage range applied to any
–0.5 to VDDQ + 0.5
–0.5 to VDDQ + 0.5
V
V
GND
1
48
GND
Y0
2
47
Y5
Y0
3
46
Y5
IIK
output in the high or low state
Input Clamp Current
–50
mA
VDDQ
4
45
VDDQ
Y1
5
44
Y6
(VI <0)
IOK
Output Clamp Current
±50
mA
Y1
6
43
Y6
GND
7
42
GND
±50
mA
GND
8
41
GND
Y2
9
40
Y7
Y2
10
39
Y7
±100
– 65 to +150
mA
°C
VDDQ
11
38
VDDQ
VDDQ
12
37
PWRDWN
CLK
13
36
FBIN
CLK
14
35
FBIN
VDDQ
15
34
VDDQ
AVDD
16
33
FBOUT
AGND
17
32
FBOUT
GND
18
31
GND
Y3
19
30
Y8
Parameter
Description
Min.
Typ.
Max.
Unit
CIN
Input Capacitance
2.5
—
3.5
pF
-0.25
—
0.25
pF
—
14
—
pF
Y3
20
29
Y8
VDDQ
21
28
VDDQ
Y4
22
27
Y9
Y4
23
26
Y9
GND
24
25
(VO <0 or
VO > VDDQ)
Continuous Output Current
IO
(VO =0 to VDDQ)
VDDQ or GND
TSTG
Continuous Current
Storage Temperature Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
CAPACITANCE(1)
VI = VDDQ or GND
CI(∆)
Delta Input Capacitance
VI = VDDQ or GND
CL
Load Capacitance
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
GND
TSSOP
TOP VIEW
RECOMMENDED OPERATING CONDITIONS
CSPT857
Symbol
Parameter
Min.
Typ.
CSPT857A
Max.
Min.
Typ.
Max.
Unit
AVDD
Supply Voltage

VDDQ

VDDQ – 0.12
VDDQ
2.7
V
VDDQ
I/O Supply Voltage
2.3
2.5
2.7
2.3
2.5
2.7
V
Operating Free-Air Temperature
-40

+85
0

+70
°C
TA
3
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (TSSOP)
Pin Name
Pin Number
AGND
17
Description
Ground for 2.5V analog supply
AVDD
16
CLK, CLK
13, 14
Differential clock input
2.5V analog supply
FBIN, FBIN
35, 36
Feedback differential clock input
FBOUT, FBOUT
32, 33
Feedback differential clock output
GND
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
Ground
PWRDWN
37
VDDQ
4, 11, 12, 15, 21, 28, 34, 38, 45
Output enable for Y and Y
Y[0:9]
3, 5, 10, 20, 22, 27, 29, 39, 44, 46
Buffered output of input clock, CLK
Y[0:9]
2, 6, 9, 19, 23, 26, 30, 40, 43, 47
Buffered output of input clock, CLK
2.5V supply
PIN DESCRIPTION (VFBGA)
Pin Name
Pin Number
Description
AGND
H1
Ground for 2.5V analog supply
AVDD
G2
2.5V analog supply
CLK, CLK
F1, F2
Differential clock input
FBIN, FBIN
F5, F6
Feedback differential clock input
FBOUT, FBOUT
H6, G5
Feedback differential clock output
GND
A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
Ground
PWRDWN
E6
VDDQ
B3, B4, E1, E2, E5, G1, G6, J3, J4
Output enable for Y and Y
Y[0:9]
A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
Buffered output of input clock, CLK
Y[0:9]
A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
Buffered output of input clock, CLK
2.5V supply
FUNCTION TABLE(1)
INPUTS
AVDD
PWRDWN
GND
GND
X
OUTPUTS
CLK
CLK
Y
Y
H
L
H
H
L
L
FBOUT
FBOUT
PLL
H
L
L
H
H
L
H
Bypassed/OFF
L
H
L
Bypassed/OFF
H
Z
Z
Z
Z
OFF
X
L
H
L
Z
Z
Z
Z
OFF
2.5V (nom)
H
L
H
L
H
L
H
ON
2.5V (nom)
H
H
L
H
L
H
L
ON
2.5V (nom)(2)
X
<20MHz
<20MHz
Z
Z
Z
Z
OFF
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Z = High-Impedance OFF-State
X = Don't Care
2. Additional feature that senses when the clock input is less than approximately 20MHz and places the part in sleep mode. Reciever inputs and PLL are turned off and outputs
= tristate.
4
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C; Industrial: TA = –40°C to +85°C
Symbol
Parameter
Conditions
Input Clamp Voltage (All Inputs)
VDDQ = 2.3V, II = -18mA
VIL (dc)
Static Input LOW Voltage
VIH (dc)
VIL (ac)
VIH (ac)
VIK
VOL
VOH
VIX
Min.
Typ.
Max.
Unit


– 1.2
V
PWRDWN
– 0.3

0.7
V
Static Input HIGH Voltage
PWRDWN
1.7

VDDQ + 0.3
Dynamic Input LOW Voltage
CLK, CLK, FBIN, FBIN


0.7
Dynamic Input HIGH Voltage
CLK, CLK, FBIN, FBIN
1.7
VDDQ
Output LOW Voltage
AVDD/VDDQ = Min., IOL = 100µA

0.1
AVDD/VDDQ = Min., IOL = 12mA

0.6
Output HIGH Voltage
AVDD/VDDQ = Min., IOH = -100µA
VDDQ – 0.1
AVDD/VDDQ = Min., IOH = -12mA
1.7
Input Differential Cross Voltage
V
V
V
VDDQ/2 – 0.2
VDDQ/2 + 0.2
V
VID(DC) (1)
DC Input Differential Voltage
0.36
VDDQ + 0.6
V
VID(AC) (1)
AC Input Differential Voltage
0.7
VDDQ + 0.6
V
Input Current
VDDQ = 2.7V, VI = 0V to 2.7V
±10
µA
IDDPD
Power-Down Current on VDDQ and AVDD
AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L

100
200
µA
IDDQ
Dynamic Power Supply Current on VDDQ
AVDD/VDDQ = Max., CLK = 200MHz, 120Ω/14pF

320
360
mA
AVDD/VDDQ = Max., CLK = 170MHz, 120Ω/14pF

250
300
AVDD/VDDQ = Max., CLK = 170MHz

IIN
IADD
Dynamic Power Supply Current on AVDD
NOTE:
1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
5
12
mA
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING REQUIREMENTS
Symbol
fCLK
Parameter
Min.
Max.
Unit
Operating Clock Frequency(1,2)
60
200
MHz
Application Clock Frequency(1,3)
60
200
MHz
tDC
Input Clock Duty Cycle
40
60
%
tL
Stabilization Time(4)

100
µs
NOTES:
1. The PLL will track a spread spectrum clock input.
2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.
3. Application clock frequency is the range over which timing specifications apply.
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
SWITCHING CHARACTERISTICS
CSPT857
Symbol
CSPT857A
Min. Typ.(1) Max.
Min. Typ.(1)
Description
Test Conditions
tPLH(1)
LOW to HIGH Level Propagation Delay Time
Test mode, CLK to any output
4.5
4.5
ns
tPHL(1)
HIGH to LOW Level Propagation Delay Time
Test mode, CLK to any output
4.5
4.5
ns
tJIT(PER)
Jitter (period), see figure 6
66MHz
tJIT(CC)
Jitter (cycle-to-cycle), see figure 3
tJIT(HPER)
Half-Period Jitter, see figure 7
– 90
– 90
90
100/ 133/ 167/ 200 MHz
– 75
75
– 75
75
66MHz
– 180
180
– 180
180
100/ 133/ 167/ 200 MHz
– 75
75
– 75
75
66MHz
– 160
160
– 160
160
100/ 133/ 167/ 200 MHz
– 100
100
– 100
100
tSLR(O)
Output Clock Slew Rate (Single-Ended)
tSLR(I)
Input Clock Slew Rate
t(∅)
Static Phase Offset, see figure 4(2,3)
tSK(O)
Output Skew, see figure 5
tR, tF
Output Rise and Fall Times (20% to 80%)
Load: 120Ω / 14pF
Output Differential Voltage
Differential outputs are terminated
VOX(5)
90
Max.
100/ 133/ 167/ 200 MHz (20% to 80%)
66/ 100/ 133/ 167/ 200 MHz
ps
ps
ps
1
2
1
2
V/ns
1
4
1
4
V/ns
– 100
100
– 50
50
ps
75
ps
900
ps
VDDQ/2
V
75
with 120Ω
Unit
650
900
VDDQ/2
650
VDDQ/2 VDDQ/2
– 0.2
+ 0.2
– 0.15
+ 0.15
The PLL on the CSPT857 will meet all the above test parameters while supporting SSC synthesizers(4) with the following parameters:
SSC
Modulation Frequency

30

50
30

50
KHz
SSC
Clock Input Frequency Deviation

0

-0.5
0

-0.5
%
f3dB
PLL Loop Bandwidth


5


5

MHz
NOTES:
1. Refers to transition of non-inverting output.
2. Static phase offset does not include jitter.
3. t(φ) is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V.
4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
5. VOX is specified at the SDRAM clock input or test load.
6
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
VDD
Z = 60Ω
C = 14pF
R = 120Ω
Z = 60Ω
VSS
C = 14pF
VSS
CSPT857/A
VSS
Figure 1. Output Load
VDDQ/2
R = 10Ω
Z = 60Ω
Z = 50Ω
C = 14pF
R = 50Ω
VDDQ/2
0V
R = 10Ω
Z = 60Ω
Z = 50Ω
C = 14pF
R = 50Ω
0V
VDDQ/2
CSPT857/A
SCOPE
VDDQ/2
Figure 2. Output Load Test Circuit
7
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
Yx, FBOUT
Yx, FBOUT
tcycle n
tcycle n+1
tjit(cc) = tcycle n
tcycle n+1
Figure 3. Cycle-to-Cycle jitter
CLK
CLK
FBIN
FBIN
t(Ø)n + 1
t(Ø)n
∑
t(Ø)
n=N
1
t(Ø)n
=
N
Figure 4. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure 5. Output Skew
8
(N is a large number of samples)
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
Yx, FBOUT
Yx, FBOUT
tcycle n
Yx, FBOUT
Yx, FBOUT
1
fo
tjit(per)
=
tcycle n
1
fo
Figure 6. Period jitter
Yx, FBOUT
Yx, FBOUT
thalf period n+1
thalf period n
Yx, FBOUT
Yx, FBOUT
1
fo
tjit(hper) = thalf period n
Figure 7. Half-Period jitter
9
1
2*f o
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
80%
80%
Clock Inputs
and Outputs
VID, VOD
20%
20%
tF
tR
Figure 8. Input and Output Slew Rates
APPLICATION INFORMATION
Clock Loading on the PLL outputs (pF)
Clock Structure
# of SDRAM Loads per Clock
Min.
#1
2
4
7
#2
4
8
14
10
Max.
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APPLICATION INFORMATION
~0.6" (split to terminator)
~2.5"
SDRAM
CSPT857/A
Z = 60Ω
CLK
C = 14pF
R = 120Ω
R = 120Ω
Z = 60Ω
CLK
FBIN
(1)
C = 14pF
8 more
SDRAM
~0.3"
R = 120Ω
FBIN
Feedback path
Figure 9. Clock Structure 1
~0.6" (split to terminator)
~2.5"
SDRAM
Stacked
SDRAM
CSPT857/A
Z = 60Ω
CLK
C = 14pF
R = 120Ω
R = 120Ω
Z = 60Ω
CLK
FBIN
(1)
C = 14pF
SDRAM
8 more
~0.3"
R = 120Ω
SDRAM
FBIN
Feedback path
Figure 10. Clock Structure 2
NOTE:
1. Memory module vendors may need to adjust the feedback capacitive load in order to meet DDR SDRAM registered DIMM timing requirements.
11
Stacked
IDTCSPT857/A
2.5V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTCSPT XXXXX
Device Type
X
XX
Package Process
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
Blank
I
0°C to +70°C (Commercial, A speed only)
-40°C to +85°C (Industrial, Std. speed only)
PA
BV
Thin Shrink Small Outline Package
Very Fine Pitch Ball Grid Array
857
857A
2.5V PLL Differential 1:10 SDRAM Clock Driver
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
12
for Tech Support:
[email protected]
(408) 654-6459
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