LINER LTC1665 Micropower octal 8-bit and 10-bit dac Datasheet

LTC1665/LTC1660
Micropower Octal
8-Bit and 10-Bit DACs
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
Tiny: 8 DACs in the Board Space of an SO-8
Micropower: 56μA per DAC Plus
1μA Sleep Mode for Extended Battery Life
Pin Compatible 8-Bit LTC1665 and 10-Bit LTC1660
Wide 2.7V to 5.5V Supply Range
Rail-to-Rail Voltage Outputs Drive 1000pF
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
Reference Input Impedance is Constant—
Eliminates External Buffer
The 8-bit LTC®1665 and 10-bit LTC1660 integrate eight
accurate, serially addressable digital-to-analog converters (DACs) in tiny 16-pin narrow SSOP packages. Each
buffered DAC draws just 56μA total supply current, yet
is capable of supplying DC output currents in excess
of 5mA and reliably driving capacitive loads to 1000pF.
Sleep mode further reduces total supply current to 1μA.
Linear Technology’s proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity
while allowing for an exceptionally small external form factor.
APPLICATIONS
n
n
n
n
n
Ultralow supply current, power-saving Sleep mode and
extremely compact size make the LTC1665 and LTC1660
ideal for battery-powered applications, while their ease
of use, high performance and wide supply range make
them excellent choices as general purpose converters.
Mobile Communications
Remote Industrial Devices
Automatic Calibration for Manufacturing
Portable Battery-Powered Instruments
Trim/Adjust Applications
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
BLOCK DIAGRAM
LTC1665 Differential Nonlinearity (DNL)
0.5
GND
VCC = 5V
VREF = 4.096V
0.4
16 VCC
1
0.3
0.2
2
DAC A
DAC H
15 VOUT H
0.1
LSB
VOUT A
0
–0.1
–0.2
VOUT B
3
DAC B
DAC G
14 VOUT G
–0.3
–0.4
–0.5
0
VOUT C
4
DAC C
DAC F
64
13 VOUT F
128
CODE
192
255
166560 G09
LTC1660 Differential Nonlinearity (DNL)
1
VOUT D
5
DAC D
DAC E
VCC = 5V
VREF = 4.096V
0.8
12 VOUT E
0.6
0.4
6
CS/LD
7
SCK
8
CONTROL
LOGIC
ADDRESS
DECODER
11
CLR
10
DOUT
9
DIN
0.2
LSB
REF
0
–0.2
–0.4
SHIFT REGISTER
166560 BD
–0.6
–0.8
–1
0
256
512
CODE
768
1023
166560 G13
166560fa
1
LTC1665/LTC1660
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
VCC to GND ............................................... –0.2V to 7.5V
Logic Inputs to GND ................................. –0.2V to 7.5V
VOUT A, VOUT B, VOUT H,
REF to GND .................................–0.2V to (VCC + 0.2V)
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC1665C/LTC1660C .............................. 0°C to 70°C
LTC1665I/LTC1660I ............................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
GND
1
16 VCC
VOUT A
2
15 VOUT H
VOUT B
3
14 VOUT G
VOUT C
4
13 VOUT F
VOUT D
5
12 VOUT E
REF
6
11 CLR
CS/LD
7
10 DOUT
SCK
8
9
DIN
GN PACKAGE
N PACKAGE
16-LEAD PLASTIC SSOP
16-LEAD PDIP
TJMAX = 125°C, θJA = 150°C/W (GN)
TJMAX = 125°C, θJA = 100°C/W (N)
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1665CGN#PBF
LTC1665CGN#PBF
1665
16-Lead Plastic SSOP
0°C to 70°C
LTC1665IGN#PBF
LTC1665IGN#PBF
1665I
16-Lead Plastic SSOP
–40°C to 85°C
LTC1660CGN#PBF
LTC1660CGN#PBF
1660
16-Lead Plastic SSOP
0°C to 70°C
LTC1660IGN#PBF
LTC1660IGN#PBF
1660I
16-Lead Plastic SSOP
–40°C to 85°C
LTC1665CN#PBF
LTC1665CN#PBF
LTC1665CN
16-Lead Plastic PDIP
0°C to 70°C
LTC1665IN#PBF
LTC1665IN#PBF
LTC1665IN
16-Lead Plastic PDIP
–40°C to 85°C
LTC1660CN#PBF
LTC1660CN#PBF
LTC1660CN
16-Lead Plastic PDIP
0°C to 70°C
LTC1660IN#PBF
LTC1660IN#PBF
LTC1660IN
16-Lead Plastic PDIP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
166560fa
2
LTC1665/LTC1660
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
LTC1665
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
LTC1660
MAX
MIN
TYP
MAX
UNITS
Accuracy
Resolution
l
8
8
10
Bits
Monotonicity
VREF ≤ VCC – 0.1V (Note 2)
l
DNL
Differential Nonlinearity
VREF ≤ VCC – 0.1V (Note 2)
l
± 0.1
±0.5
±0.2
±0.75
LSB
INL
Integral Nonlinearity
VREF ≤ VCC – 0.1V (Note 2)
l
±0.2
±1.0
±0.6
±2.5
LSB
VOS
Offset Error
(Note 7)
l
±10
±30
±10
±30
mV
l
±15
FSE
Full-Scale Error
l
±1
l
±30
±30
μV/°C
0.045
0.18
LSB/V
VOS Temperature Coefficient
VCC = 5V, VREF = 4.096V
Full-Scale Error Temperature Coefficient
PSR
Power Supply Rejection
VREF = 2.5V
10
Bits
±15
±4
±3
μV/°C
±15
LSB
The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
V
Reference Input
Input Voltage Range
IREF
l
0
l
35
Resistance
Not in Sleep Mode
Capacitance
(Note 6)
Reference Current
Sleep Mode
l
65
kΩ
15
pF
0.001
1
μA
5.5
V
450
340
1
730
530
3
μA
μA
μA
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current
VCC = 5V (Note 3)
VCC = 3V (Note 3)
Sleep Mode (Note 3)
l
l
l
Short-Circuit Current Low
VOUT = 0V, VCC = 5.5V, VREF = 5.1V, Code = Full
Scale
l
10
30
100
mA
Short-Circuit Current High
VOUT = VCC = 5.5V, VREF = 5.1V, Code = 0
l
10
27
120
mA
2.7
DC Performance
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
Voltage Output Settling Time
To ±0.5LSB (Notes 4, 5)
0.60
0.25
Capacitive Load Driving
V/μs
V/μs
30
μs
1000
pF
Digital I/O
VIH
Digital Input High Voltage
VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
l
l
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
l
l
VOH
Digital Output High Voltage
IOUT = –1mA, DOUT Only
l
VOL
Digital Output Low Voltage
IOUT = 1mA, DOUT Only
l
0.4
V
ILK
Digital Input Leakage
VIN = GND to VCC
l
±10
μA
CIN
Digital Input Capacitance
(Note 6)
l
10
pF
2.4
2.0
V
V
0.8
0.6
VCC – 1
V
V
V
166560fa
3
LTC1665/LTC1660
TIMING CHARACTERISTICS
The l denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 4.5V to 5.5V
t1
DIN Valid to SCK Setup
l
40
ns
l
t2
DIN Valid to SCK Hold
0
ns
t3
SCK High Time
(Note 6)
l
30
ns
t4
SCK Low Time
(Note 6)
l
30
ns
t5
CS/LD Pulse Width
(Note 6)
l
80
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
30
ns
t7
CS/LD Low to SCK High
(Note 6)
l
80
t8
DOUT Propagation Delay
CLOAD = 15pF (Note 6)
l
5
t9
SCK Low to CS/LD Low
(Note 6)
l
20
ns
t10
CLR Pulse Width
(Note 6)
l
100
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
ns
SCK Frequency
Continuous Square Wave (Note 6)
Continuous 23% Duty Cycle Pulse (Note 6)
Gated Square Wave (Note 6)
l
l
l
(Note 6)
l
60
ns
0
ns
50
ns
ns
80
ns
5.00
7.69
16.7
MHz
MHz
MHz
VCC = 2.7V to 5.5V
t1
DIN Valid to SCK Setup
t2
DIN Valid to SCK Hold
(Note 6)
l
t3
SCK High Time
(Note 6)
l
t4
SCK Low Time
(Note 6)
l
50
ns
t5
CS/LD Pulse Width
(Note 6)
l
100
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
50
ns
t7
CS/LD Low to SCK High
(Note 6)
l
100
t8
DOUT Propagation Delay
CLOAD = 15pF (Note 6)
l
5
t9
SCK Low to CS/LD Low
(Note 6)
l
30
ns
t10
CLR Pulse Width
(Note 6)
l
120
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
ns
SCK Frequency
Continuous Square Wave (Note 6)
Continuous 28% Duty Cycle Pulse
Gated Square Wave
l
l
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined from code 4 to code
255 for the LTC1665 and from code 20 to code 1023 for the LTC1660.
See Applications Information.
Note 3: Digital inputs at 0V or VCC.
ns
150
ns
3.85
5.55
10
MHz
MHz
MHz
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS,
i.e., codes 26 and 230 for the LTC1665 or codes 102 and 922 for the
LTC1660.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured at code 4 for the LTC1665 and code 20 for the
LTC1660.
166560fa
4
LTC1665/LTC1660
TYPICAL PERFORMANCE CHARACTERISTICS
Midscale Output Voltage
vs Load Current
2
VREF = VCC
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
1.9
VOUT (V)
2.6
VCC = 5V
2.5
2.4
2.3
VCC = 3.6V
1.7
VCC = 5.5V
2.2
1000
1.6
VCC = 3V
1.5
1.4
VCC = 2.7V
1.3
VCC = 4.5V
125°C
800
25°C
600
–55°C
400
1.2
2.1
200
1.1
SOURCE
–20
–10
SINK
SOURCE
1
0
10
IOUT (mA)
20
30
SINK
0
–15 –12
–8
–4
0
4
IOUT (mA)
8
166560 G01
12 15
1400
2
4
6
|IOUT| (mA) (SOURCING)
8
10
166560 G03
Large-Signal Step Response
5
VCC = 5V
CODE = 0
1200
0
166560 G02
Minimum VOUT
vs Load Current (Output Sinking)
125°C
VCC = VREF = 5V
10% TO
90% STEP
4
1000
VOUT (mV)
2
800
25°C
600
–55°C
3
2
400
1
200
0
0
0
2
|
4
6
8
IOUT (mA) (SINKING)
10
|
0
20
40
60
TIME (μs)
80
166560 G04
Supply Current
vs Logic Input Voltage
500
2
ALL DIGITAL INPUTS
SHORTED TOGETHER
480
460
VCC = 5.5V
440
VCC = 4.5V
420
400
1.6
VCC = 3.6V
380
360
100
166560 G05
Supply Current vs Temperature
SUPPLY CURRENT (μA)
VOUT (V)
VREF = 4.096V
ΔVOUT < 1LSB
CODE = 255 (LTC1665)
CODE = 1023 (LTC1660)
1200
1.8
2.7
–30
1400
VCC – VOUT (mV)
2.8
Minimum Supply Headroom
vs Load Current (Output Sourcing)
VREF = VCC
CODE = 128 (LTC1665)
CODE = 512 (LTC1660)
VOUT (V)
2.9
Midscale Output Voltage
vs Load Current
SUPPLY CURRENT (mA)
3
(LTC1665/LTC1660)
VCC = 2.7V
340
1.2
0.8
0.4
320
300
–55 –35 –15
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
166560 G06
0
1
2
3
4
LOGIC INPUT VOLTAGE (V)
5
166560 G07
166560fa
5
LTC1665/LTC1660
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1665)
Integral Nonlinearity (INL)
1
VCC = 5V
VREF = 4.096V
0.8
VCC = 5V
VREF = 4.096V
0.4
0.6
0.3
0.4
0.2
0.2
0.1
LSB
LSB
Differential Nonlinearity (DNL)
0.5
0
0
–0.2
–0.1
–0.4
–0.2
–0.6
–0.3
–0.8
–0.4
–1
–0.5
0
64
128
CODE
192
255
0
64
128
CODE
192
166560 G09
1665/60 G08
Load Regulation vs Output Current
Load Regulation vs Output Current
VCC = VREF = 5V
CODE = 128
0.5
0.5
VCC = VREF = 3V
CODE = 128
0.25
ΔVOUT (LSB)
0.25
ΔVOUT (LSB)
255
0
0
–0.25
–0.25
SOURCE
–0.5
–2
–1
0
IOUT (mA)
SINK
–0.5
1
2
166560 G10
–500
SOURCE
0
IOUT (μA)
SINK
500
166560 G11
166560fa
6
LTC1665/LTC1660
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1660)
Integral Nonlinearity (INL)
2.5
VCC = 5V
VREF = 4.096V
2.0
VCC = 5V
VREF = 4.096V
0.8
1.5
0.6
1.0
0.4
0.5
0.2
LSB
LSB
Differential Nonlinearity (DNL)
1
0
0
– 0.5
–0.2
–1.0
–0.4
–1.5
–0.6
– 2.0
–0.8
– 2.5
–1
0
256
512
CODE
768
1023
0
256
512
CODE
768
1023
166560 G13
166560 G12
Load Regulation vs Output Current
2
Load Regulation vs Output Current
VCC = VREF = 5V
CODE = 512
2
1.5
1.5
1
ΔVOUT (LSB)
1
ΔVOUT (LSB)
VCC = VREF = 3V
CODE = 512
0.5
0
–0.5
0.5
0
–0.5
–1
–1
–1.5
–1.5
SOURCE
–2
–2
–1
0
IOUT (mA)
SINK
–2
1
2
166560 G14
–500
SOURCE
0
IOUT (μA)
SINK
500
166560 G15
166560fa
7
LTC1665/LTC1660
PIN FUNCTIONS
(LTC1665/LTC1660)
GND (Pin 1): System Ground.
VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Voltage Outputs. The output range is
⎛ 255 ⎞
0 to ⎜
V for the LTC1665
⎝ 256 ⎟⎠ REF
⎛ 1023 ⎞
0 to ⎜
V for the LTC1660
⎝ 1024 ⎟⎠ REF
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
DIN into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
DIN (Pin 9): Serial Interface Data Input. Data on the DIN
pin is shifted into the 16-bit register on the rising edge of
SCK. CMOS and TTL compatible.
DOUT (Pin 10): Serial Interface Data Output. Data appears
on DOUT 16 positive SCK edges after being applied to DIN.
May be tied to DIN of another LTC1665/LTC1660 for daisychain operation. CMOS and TTL compatible.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
BLOCK DIAGRAM
16 VCC
GND
1
VOUT A
2
DAC A
DAC H
15 VOUT H
VOUT B
3
DAC B
DAC G
14 VOUT G
VOUT C
4
DAC C
DAC F
13 VOUT F
VOUT D
5
DAC D
DAC E
12 VOUT E
REF
6
CS/LD
7
SCK
8
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
11
CLR
10
DOUT
9
DIN
166560 BD
166560fa
8
LTC1665/LTC1660
TIMING DIAGRAM
t1
t2
t3
t6
t4
SCK
t9
t11
DIN
A3
t5
A1
A2
X1
X0
t7
CS/LD
t8
DOUT
A3
A2
A1
X1
X0
A3
166560 F01
Figure 1
OPERATION
Transfer Function
Serial Interface
The transfer function is:
Referring to Figure 2a (2b): With CS/LD held low, data
on the DIN input is shifted into the 16-bit shift register on
the positive edge of SCK. The 4-bit DAC address, A3-A0,
is loaded first (see Table 2), then the 8-bit (10-bit) input
code, D7-D0 (D9-D0), ordered MSB-to-LSB in each case.
Four (two) don’t-care bits, X3-X0 (X1-X0), are loaded last.
When the full 16-bit input word has been shifted in, CS/LD
is pulled high, loading the DAC register with the word
and causing the addressed DAC output(s) to update. The
clock is disabled internally when CS/LD is high. Note: SCK
must be low before CS/LD is pulled low.
⎛ k ⎞
VOUT(IDEAL) = ⎜
V for the LTC1665
⎝ 256 ⎟⎠ REF
⎛ k ⎞
VOUT(IDEAL) = ⎜
V for the LTC1660
⎝ 1024 ⎟⎠ REF
where k is the decimal equivalent of the binary DAC input
code and VREF is the voltage at REF (Pin 6).
Power-On Reset
The LTC1665 clears the outputs to zero scale when power
is first applied, making system initialization consistent
and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.2V ≤ VREF ≤ VCC + 0.2V (see Absolute Maximum Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 16) is in transition.
The buffered serial output of the shift register is available
on the DOUT pin, which swings from GND to VCC. Data
appears on DOUT 16 positive SCK edges after being applied to DIN.
Multiple LTC1665/LTC1660’s can be controlled from a
single 3-wire serial port (i.e., SCK, DIN and CS/LD) by
using the included “daisy-chain” facility. A series of m
chips is configured by connecting each DOUT (except the
last) to DIN of the next chip, forming a single 16m-bit
shift register. The SCK and CS/LD signals are common
to all chips in the chain. In use, CS/LD is held low while m
16-bit words are clocked to DIN of the first chip; CS/LD
is then pulled high, updating all of them simultaneously.
166560fa
9
LTC1665/LTC1660
OPERATION
SCK
1
A3
DIN
2
A2
3
4
A1
A0
5
D7
6
D6
7
8
D5
D4
ADDRESS/CONTROL
9
10
D3
D2
11
D1
12
D0
13
X3
INPUT CODE
14
X2
15
X1
16
X0
DON’T CARE
INPUT WORD W0
CS/LD
(ENABLE CLK)
DOUT
(UPDATE OUTPUT)
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X3
X2
X1
X0
A3
INPUT WORD W–1
INPUT WORD W0
166560 F02a
Figure 2a. LTC1665 Register Loading Sequence
SCK
1
A3
DIN
2
A2
3
4
A1
A0
5
D9
6
D8
7
8
D7
D6
ADDRESS/CONTROL
9
10
D5
D4
11
D3
12
D2
13
D1
14
D0
INPUT CODE
15
X1
16
X0
DON’T CARE
INPUT WORD W0
CS/LD
(ENABLE CLK)
DOUT
(UPDATE OUTPUT)
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
INPUT WORD W–1
D1
D0
X1
X0
A3
INPUT WORD W0
166560 F02b
Figure 2b. LTC1660 Register Loading Sequence
Table 1a. LTC1665 Input Word
Sleep Mode
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X3 X2 X1 X0
ADDRESS/CONTROL
INPUT CODE
DON’T CARE
Table 1b. LTC1660 Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
ADDRESS/CONTROL
INPUT CODE
DON’T
CARE
DAC address 1110b is reserved for the special Sleep instruction (see Table 2). In this mode, the digital interface stays
active while the analog circuits are disabled; static power
consumption is thus virtually eliminated. The reference
input and analog outputs are set in a high impedance state
and all DAC settings are retained in memory so that when
Sleep mode is exited, the outputs of DACs not updated by
the Wake command are restored to their last active state.
166560fa
10
LTC1665/LTC1660
OPERATION
Voltage Outputs
Table 2. DAC Address/Control Functions
ADDRESS/CONTROL
Each of the eight rail-to-rail output amplifiers contained
in these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloaded and have an equivalent output resistance of 85Ω
when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.
A3
A2
A1
A0
DAC STATUS
SLEEP STATUS
0
0
0
0
No Change
Wake
0
0
0
1
Load DAC A
Wake
0
0
1
0
Load DAC B
Wake
0
0
1
1
Load DAC C
Wake
0
1
0
0
Load DAC D
Wake
0
1
0
1
Load DAC E
Wake
0
1
1
0
Load DAC F
Wake
0
1
1
1
Load DAC G
Wake
1
0
0
0
Load DAC H
Wake
1
0
0
1
No Change
Wake
1
0
1
0
No Change
Wake
1
0
1
1
No Change
Wake
Rail-to-Rail Output Considerations
1
1
0
0
No Change
Wake
1
1
0
1
No Change
Wake
1
1
1
0
No Change
Sleep
In any rail-to-rail output voltage DAC, the output is limited
to voltages within the supply range.
1
1
1
1
Load ALL DACs
with Same
8/10-Bit Code
Wake
Sleep mode is initiated by performing a load sequence
to address 1110b (the DAC input word D7-D0 [D9-D0]
is ignored). Once in Sleep mode, a load sequence to any
other address (including “No Change” addresses 0000b
and 1001-1101b) causes the LTC1665/LTC1660 to Wake.
It is possible to keep one or more chips of a daisy chain
in continuous Sleep mode by giving the Sleep instruction
to these chips each time the active chips in the chain are
updated.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1μF
load can be successfully driven by inserting a 20Ω resistor; a 2.2μF load needs only a 10Ω resistor. In either case,
larger values of resistance, capacitance or both may be
safely substituted for the values given.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at VCC as shown in Figure 3c. No full-scale limiting can
occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
166560fa
11
LTC1665/LTC1660
OPERATION
POSITIVE
FSE
VREF = VCC
OUTPUT
VOLTAGE
INPUT CODE
(c)
VREF = VCC
OUTPUT
VOLTAGE
0
128
INPUT CODE
(a)
255
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
166560 F03
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
166560fa
12
LTC1665/LTC1660
TYPICAL APPLICATIONS
A Low Power Quad Trim Circuit with Coarse/Fine Adjustment
3.3V
3.3V
R1
R2
0.1μF
0.1μF
R2
4
–
VOUT1
U2A
LT®1491
+
1
GND
2
R1
COARSE V
OUT A
3
U1
LTC1665
1
2
DAC A
16
DAC H
15
VCC
VOUT H
R1
COARSE
VOUT G
R2
FINE
VOUT F
R1
COARSE
VOUT E
R2
FINE
R1
13
–
12
+LT1491
14
U2D
VOUT4
11
0.1μF
0.1μF
R1
R2
–
VOUT2
U2B
LT1491
+
7
R2
FINE
VOUT B
3
DAC B
DAC G
14
R1
9
6
R1
COARSE VOUT C
5
4
DAC C
DAC F
13
0.1μF
3.3V
R2
0.1μF
–
U2C
10
+LT1491
8
VOUT3
0.1μF
R2
FINE
VOUT D
5
DAC D
DAC E
12
2
LTC1258-2.5
1
4
REF
CS/LD
3-WIRE
SERIAL
INTERFACE
SCK
6
7
8
11
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
10
9
CLR
DOUT
TO OTHER
LTC1665s
DIN
166560 TA01
R2 >> R1
VOUT 1 = VOUT A + R1 VOUT B
R2
Similarly VOUT 2, VOUT 3, VOUT 4
Example: For R1 = 110Ω and R2 = 11k,
VOUT 1 = VOUT A + 0.01 VOUT B
166560fa
13
LTC1665/LTC1660
TYPICAL APPLICATIONS
An 8-Channel Bipolar Output Voltage Circuit Configuration
5V
R
R
R
R
0.1μF
0.1μF
VS+
1
U2A
LT1491
+
VOUT A ´
±5V
–
4
0.1μF 11
+
DAC A
DAC H
15
VOUT H
3
+LT1491
R
VOUT H ´
±5V
1
11 0.1μF
U2C
LT1491
3
DAC B
DAC G
14
VOUT G
6
–
5
+LT1491
R
4
DAC C
DAC F
13
VOUT F
10
VOUT D
+
–
+
REF
CS/LD
3-WIRE
SERIAL
INTERFACE
CLK
5
DAC D
DAC E
6
7
8
12
11
CONTROL
LOGIC
ADDRESS
DECODER
SHIFT REGISTER
10
9
VOUT E
VOUT F ´
±5V
14
VOUT E ´
±5V
R
13
–
12
+LT1491
U3D
12
8
+LT1491
R
13
VOUT G ´
±5V
–
U3C
VOUT C
10
7
R
9
9
R
U2D
LT1491
R
U3B
VOUT B
5
R
–
14
2
6
R
VOUT D ´
±5V
–
VS–
U2B
LT1491
8
4
2
U3A
VOUT A
3
R
VOUT C ´
±5V
16
VCC
R
–
7
1
2
VS–
R
VOUT B ´
±5V
0.1μF
VS+
U1
LTC1660
GND
CLR
DOUT
DIN
CODE VOUT X
– 5V
0
0V
512
1023 +4.99V
166560 TA04
166560fa
14
LTC1665/LTC1660
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG #05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
w 45s
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
166560fa
15
LTC1665/LTC1660
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
N Package
16-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
.770*
(19.558)
MAX
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
+.035
.325 –.015
+0.889
8.255
–0.381
.130 ± .005
(3.302 ± 0.127)
.045 – .065
(1.143 – 1.651)
.020
(0.508)
MIN
.065
(1.651)
TYP
.120
(3.048)
MIN
.100
(2.54)
BSC
.018 ± .003
(0.457 ± 0.076)
N16 REV I 0711
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
166560fa
16
LTC1665/LTC1660
REVISION HISTORY
REV
DATE
DESCRIPTION
A
1/12
Removed Typical values in Timing Characteristics
PAGE NUMBER
3, 4
166560fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC1665/LTC1660
TYPICAL APPLICATION
A Pin Driver VH and VL Adjustment Circuit for ATE Applications
5V
11
16
6
CLR
VCC
REF
0.1μF
VH
(FROM MAIN DAC)
U1 LTC1660
DAC A
DAC H
2
RG
VA 50k
10V
RF
5k
3
2
DAC B
DAC G
3
+ U2A
LT1369
QUAD
– 5V
VL
(FROM MAIN DAC)
DAC F
DAC C
4
CS/LD
7
DIN
9
SCK
8
DAC D
5
VH´
VH´ = VH + ΔVH
VL´
0.1μF
0.1μF
RF
5k
VH
VL
RF
5k
5
6
DAC E
1
–
RG
VB 50k
RG
VC 50k
0.1μF
+ U2B
LT1369
QUAD
7
VL´ = VL + VL
VOUT
0.1μF
–
RG
VD 50k
PIN DRIVER
(1 OF 2)
LOGIC
DRIVE
RF
5k
166560 TA03
VA = VC = 2.5V
GND
1
Note: DACs E Through H Can Be
Configured for a Second Pin Driver
With U2C and U2D of the LT1369
CODE A CODE B ΔVH, ΔVL
512
1023 – 250mV
0
512
512
+ 250mV
512
0
VH´ = VH + RF (V – V )
B
RG A
VL´ = VL + RF (V – V )
D
RG C
For Resistor Values Shown:
Adjustment Range = 250mV
Adjustment Step Size = 500μV
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1661
Dual 10-Bit VOUT DAC in 8-Lead MSOP Package
VCC = 2.7V to 5.5V Micropower Rail-to-Rail Output
LTC1663
Single 10-Bit VOUT DAC in SOT-23 Package
VCC = 2.7V to 5.5V, Internal Reference, 60μA
LTC1446/
LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit VOUT DAC in SO-8 Package
VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC
LTC1454/
LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1458/
LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1590
Dual 12-Bit IOUT DAC in SO-16 Package
VCC = 4.5V to 5.5V, 4-Quadrant Multiplication
LTC1659
Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package
VCC: 2.7V to 5.5V
Low Power Multiplying VOUT DAC. Output Swings from GND to
REF. REF Input Can Be Tied to VCC
LT1460
Micropower Precision Series Reference, 2.5V, 5V, 10V Versions
0.075% Max, 10ppm/°C Max, Only 130μA Supply Current
166560fa
18 Linear Technology Corporation
LT 0112 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1999