TI1 LM10506 Triple buck ldo power management unit Datasheet

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LM10506
SNVS729F – SEPTEMBER 2011 – REVISED AUGUST 2014
LM10506 Triple Buck + LDO Power Management Unit
1 Features
3 Description
•
The LM10506 is an advanced PMU containing three
configurable, high-efficiency buck regulators for
supplying variable voltages. The device is ideal for
supporting ASIC and SOC designs for Solid-State
and Flash drives.
Device Information(1)
PART NUMBER
PACKAGE
LM10506
space
space
space
Simplified Schematic
IO input
`
supply
C9
2.2 F
LM10506
Reset
VIN_IO
STANDBY
CS
SPI
DI
System
DO
Control
CLK
C8
2.2 F
VIN_B1
C5
4.7 F
VCOMP
COMP
LDO
IRQ
3.2V
LDO
SW_B1
BUCK1
C4
4.7 F
L1
2.2 H
FB_B1
L2
SW_B2
BUCK2
2.2 H
L3
SW_B3
VIN_B3
H/L B3
BUCK3
GND
C7
4.7 F
1.1V to 3.6V
C1
22 F
1.1V to 3.6V
C2
22 F
FB_B2
H/L B2
Power Supply
3.3/5.0V
VIN
C6
4.7 F
Solid-State Drives
2.84 mm x 2.84 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
VIN_B2
2 Applications
BODY SIZE (MAX)
DSBGA (34)
CONTROL LOGIC and REGISTERS
•
•
The LM10506 operates cooperatively with ASIC to
optimize the supply voltage for low-power conditions
and Power Saving modes via the SPI interface. It
also supports a 100-mA LDO and a programmable
Interrupt Comparator.
GND
•
•
Three Highly Efficient Programmable Buck
Regulators
– Buck Regulator Outputs:
– Buck 1: 1.1 V to 3.6 V; 1.3 A
– Buck 2: 1.1 V to 3.6 V; 400 mA
– Buck 3: 0.7 V to 1.335 V; 600 mA
– ±3% Feedback Voltage Accuracy
– Up to 95% Efficient Buck Regulators
– 2MHz Switching Frequency for Smaller
Inductor Size
– Integrated FETs with Low RDSON
– Bucks Operate With Their Phases Shifted to
Reduce the Input Current Ripple and Capacitor
Size
– Programmable Output Voltage via the SPI™
Interface
– Overvoltage and Undervoltage Lockout
– Automatic Internal Soft Start With Power-On
Reset
– Current Overload and Thermal Shutdown
Protection
– Bypass Mode Available on Bucks 1 and 2
– PFM Mode for Low-Load, High-Efficiency
Operation
Low-Dropout LDO 3.2 V, 100 mA
SPI-Programmable Interrupt Comparator (2 V to 4
V)
Alternate Buck VOUT Selectable via H/L Logic Pins
RESET, STANDBY Pins
GND
1
FB_B3
2.2 H
Host
Controller
VHOST
100 mA
Host 1
Domain
VCC
1.3A
Host 2
Domain
VCCQ
400 mA
0.7V to1.335V
C3
22 F
Host 3
Domain
VCORE
600 mA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM10506
SNVS729F – SEPTEMBER 2011 – REVISED AUGUST 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
Handling Ratings....................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
General Electrical Characteristics............................. 6
Buck 1 Electrical Characteristics............................... 7
Buck 2 Electrical Characteristics............................... 7
Buck 3 Electrical Characteristics............................... 8
LDO Electrical Characteristics .................................. 9
Comparators Electrical Characteristics .................. 9
Typical Characteristics .......................................... 10
8
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
13
13
18
22
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Application ................................................. 28
10 Power Supply Recommendations ..................... 35
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 36
12 Device and Documentation Support ................. 37
12.1
12.2
12.3
12.4
Device Support ....................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F
•
2
Page
Changed format to meet new TI standards; added Device Information and Handling Ratings tables; replace
SUPPLY SPECIFICATION table with Device Comparison table, rename Functional Description and Applications
sections, reformat and add new information, add Devices and Documentation section ....................................................... 1
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SNVS729F – SEPTEMBER 2011 – REVISED AUGUST 2014
5 Device Comparison Table
Table 1. Available Device Options
PART NUMBER
BUCK 2 VOUT
SOFT-START IN BYPASS
BUCK 2 BYPASS
LM10506TME
3.0 V
NO
YES
LM10506TME-A
2.0 V
NO
YES
6 Pin Configuration and Functions
DSBGA
34
Top View
TOP VIEW
7
GND_B1
GND_B1
6
SW_B1
5
VCOMP
GND
RESET
GND_B3
SW_B1
SW_B3
SW_B3
VIN_B1
VIN_B1
FB_B3
VIN_B3
4
FB_B1
FB_B1
HL_B3
HL_B2
3
VIN
GND
FB_B2
VIN_B2
2
LDO
GND
SW_B2
SW_B2
1
IRQ
VIN_IO
SPI_
CLK
SPI_DI
SPI_DO
SPI_CS
GND_B2
A
B
C
D
E
STANDBY
F
G
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SNVS729F – SEPTEMBER 2011 – REVISED AUGUST 2014
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Pin Functions
PIN
I/O (1)
TYPE (1)
VIN_B1
I
P
Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET.
SW_B1
I/O
P
Buck Switcher Regulator 1 - Power Switching node, connect to inductor
A/B4
FB_B1
I/O
A
Buck Switcher Regulator 1 - Voltage output feedback plus Bypass Power
A/B7
GND_B1
G
P
Buck Switcher Regulator 1 - Power ground for Buck Regulator
G3
VIN_B2
I
P
Buck Switcher Regulator 2 - Power supply voltage input for power stage PFET.
F/G2
SW_B2
I/O
P
Buck Switcher Regulator 2 - Power Switching node, connect to inductor
NUMBER
NAME
A/B5
A/B6
DESCRIPTION
F3
FB_B2
I
A
Buck Switcher Regulator 2 - Voltage output feedback
G1
GND_B2
G
P
Buck Switcher Regulator 2 - Power ground for Buck Regulator
G5
VIN_B3
I
P
Buck Switcher Regulator 3 - Power supply voltage input for power stage PFET.
F/G6
SW_B3
I/O
P
Buck Switcher Regulator 3 - Power Switching node, connect to inductor
F5
FB_B3
I
A
Buck Switcher Regulator 3 - Voltage output feedback
G7
GND_B3
G
P
Buck Switcher Regulator 3 - Power ground for Buck Regulator
A3
VIN
I
P
Power supply Input Voltage, must be present for device to work
A2
LDO
O
P
LDO Regulator - LDO regulator output voltage
G4
HL_B2
I
D
Digital Input Startup Control Signal to change predefined output Voltage of Buck 2,
internally pulled down as a default
F4
HL_B3
I
D
Digital Input Startup Control Signal to change predefined output Voltage of Buck 3,
internally pulled up as a default
E7
STANDBY
I
D
Digital Input Control Signal for entering Standby Mode. This is an active High pin with
an internal pulldown resistor.
F7
RESET
I
D
Digital Input Control Signal to abort SPI transactions; resets the PMIC to default
voltages. This is an active Low pin with an internal pullup.
C7
VCOMP
I
A
Analog Input for Comparator
A1
IRQ
O
D
Digital Output of Comparator to signal interrupt condition
F1
SPI_CS
I
D
SPI Interface - chip select
D1
SPI_DI
I
D
SPI Interface - serial data input
E1
SPI_DO
O
D
SPI Interface - serial data output
C1
SPI_CLK
I
D
SPI Interface - serial clock input
B1
VIN_IO
I
A
Supply Voltage for Digital Interface
B2
GND
G
G
Ground. Connect to system Ground.
B3
GND
G
G
Ground. Connect to system Ground.
D7
GND
G
G
Ground. Connect to system Ground.
(1)
Type
I/O
A
Analog Pin
I
Input Pin
D
Digital Pin
O
Output Pin
P
Power Connection
G
Ground
4
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
MAX
VIN, VCOMP
−0.3
6
VIN_IO, VIN_B1, VIN_B2, VIN_B3, SPI_CS, SPI_DI, SPI_CLK, SPI_DO, IRQ, HL_B2, HL_B3,
STANDBY, RESET, SW_B1, SW_B2, SW_B3, FB_B1, FB_B2, FB_B3, LDO
−0.3
6
V
150
°C
Junction Temperature (TJ-MAX)
(1)
(2)
(3)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Internal thermal shutdown protects device from permanent damage. Thermal shutdown engages at TJ = 140°C and disengages at TJ =
120°C (typ.). Thermal shutdown is ensured by design.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
MIN
MAX
UNIT
–65
150
°C
–2000
2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN_B1, VIN_B2_VIN_B3, VIN
VIN_IO (< VIN)
All pins except VIN_IO
MIN
MAX
3
5.5
1.72
3.63 (but < VIN)
0
VIN
Junction temperature (TJ)
−40
125
Ambient temperature (TA)
−40
85
Maximum continuous power dissipation (PD-MAX)
(1)
(1)
0.9
UNIT
V
°C
W
In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C),
the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
7.4 Thermal Information
LM10506
THERMAL METRIC
(1)
DSBGA
UNIT
34 PINS
RθJA
(1)
Junction-to-ambient thermal resistance
44.5
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 General Electrical Characteristics (1) (2)
Unless otherwise noted, VIN = 5 V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C, unless otherwise noted.
SYMBOL
IQ(STANDBY)
PARAMETER
TEST CONDITIONS
Quiescent supply current
MIN
STANDBY = HIGH, no load
TYP
MAX
100
(3)
200
UNIT
µA
UNDER/OVERVOLTAGE LOCK OUT
VUVLO_RISING
2.90
VUVLO_FALLING
2.60
VOVLO_RISING
5.82
VOVLO_FALLING
5.70
V
DIGITAL INTERFACE
VIL
Logic input low
VIH
Logic input high
VIL
Logic input low
VIH
Logic input high
VOL
Logic output low
VOH
Input current, pin driven high
fSPI_MAX
tRESET
tSTANDBY
(2)
(3)
(4)
6
SPI_DO, IRQ
Input current, pin driven low
IIH
0.3*VIN_IO (3)
0.7*VIN_IO
(3)
0.3*VIN (3)
HL_B2, HL_B3
Logic output high
IIL
(1)
SPI_CS, SPI_DI, SPI_CLK,
RESET, STANDBY
0.7*VIN (3)
0.2*VIN_IO (3)
0.8*VIN_IO
(3)
SPI_CS, SPI_DI, SPI_CLK,
HL_B2, STANDBY
−2
HL_B3, RESET
−5
µA
SPI_CS, SPI_DI, SPI_CLK,
HL_B3, RESET
2
HL_B2, STANDBY
5
10 (3)
SPI max frequency
Minimum high-pulse width
V
2 (3)
(4)
2 (3)
µA
MHz
µs
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Limits apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ 85°C.
Specification ensured by design. Not tested during production.
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7.6 Buck 1 Electrical Characteristics (1) (2) (3)
Unless otherwise noted, VIN = 5 V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C, unless otherwise noted.
SYMBOL
IQ
PARAMETER
TEST CONDITIONS
DC bias current in VIN
No Load, PFM Mode
IPEAK
Peak switching current limit
Buck 1 enabled, switching in
PWM
η
Efficiency peak, Buck 1
ƒSW
(5)
Input capacitor
COUT
L
Output filter capacitor
(5)
Output capacitor ESR
(5)
DC line regulation
DC load regulation
MAX
15
50
(4)
µA
2.1
(4)
A
0 mA ≤ IOUT ≤ 1.3 A
2
10
10
2.3 (4)
(5)
Feedback pin input bias
current
RDS-ON-HS
High side switch on resistance
RDS-ON-LS
Low side switch on resistance
Bypass FET on resistance
100
20
(5)
(5)
UNIT
90%
4.7
IFB
RDS-ON_BYPASS
1.75
(4)
TYP
1.8
(5)
Output filter inductance
ΔVOUT
1.6
(4)
IOUT = 0.3 A
Switching frequency
CIN
MIN
MHz
µF
mΩ
2.2
µH
3.3 V ≤ VIN ≤ 5 V, IOUT = 1.3 A
0.5
%/V
0.13 A ≤ IOUT ≤ 1.3 A
0.3
%/A
VFB = 3 V
2.1
5 (4)
135
VIN = 2.6 V
mΩ
215
85
µA
190 (4)
mΩ
Used in parallel with the high
side FET while in Bypass
mode. Resistance (DCR) of
inductor = 100 mΩ
VIN = 3.3 V
85
VIN = 2.6 V
120
Start-up from shutdown, VOUT
= 0V, no load, LC =
recommended circuit, using
software enable, to VOUT =
95% of final value
0.1
mΩ
STARTUP
TSTART
(1)
Internal soft-start (turn on
time) (5)
ms
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
BUCK normal operation is ensured if VIN ≥ VOUT+1 V.
Limits apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ 85°C.
Specification ensured by design. Not tested during production.
(2)
(3)
(4)
(5)
7.7 Buck 2 Electrical Characteristics (1) (2) (3)
Unless otherwise noted, VIN = 5 V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C, unless otherwise noted.
SYMBOL
IQ
PARAMETER
TEST CONDITIONS
DC bias current in VIN
No Load, PFM Mode
IPEAK
Peak switching current limit
Buck 2 enabled, switching in
PWM
η
Efficiency peak, Buck 2
ƒSW
Switching frequency
(1)
(2)
(3)
(4)
(5)
(5)
MIN
0.65
(4)
IOUT = 0.3 A
TYP
MAX
15
50
(4)
µA
1.55
(4)
A
1.1
UNIT
90%
1.75 (4)
2
2.3 (4)
MHz
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
BUCK normal operation is ensured if VIN ≥ VOUT+1 V.
Limits apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ 85°C.
Specification ensured by design. Not tested during production.
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Buck 2 Electrical Characteristics(1)(2)(3) (continued)
Unless otherwise noted, VIN = 5 V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C, unless otherwise noted.
SYMBOL
CIN
PARAMETER
Input capacitor
TEST CONDITIONS
(5)
0 mA ≤ IOUT ≤ 400 mA
Output capacitor ESR
L
DC line regulation
DC load regulation
IFB
10
10
(5)
Output filter inductance
ΔVOUT
TYP
MAX
UNIT
4.7
Output filter capacitor
COUT
MIN
(5)
100
20
(5)
(5)
(5)
Feedback pin input bias current
RDS-ON-HS
High side switch on resistance
RDS-ON-LS
Low side switch on resistance
µF
mΩ
2.2
µH
3.3 V ≤ VIN ≤ 5 V, IOUT = 400
mA
0.5
%/V
100 mA ≤ IOUT ≤ 400 mA
0.3
VFB = 1.8 V
1.8
%/A
5 (4)
µA
135
VIN = 2.6 V
260
85
mΩ
190 (4)
STARTUP
Internal soft-start (turn on time)
TSTART
(5)
Startup from shutdown, VOUT
= 0V, no load, LC =
recommended circuit, using
software enable, to VOUT =
95% of final value
0.1
ms
7.8 Buck 3 Electrical Characteristics (1) (2) (3)
Unless otherwise noted, VIN = 5 V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C, unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
IQ
DC bias current in VIN
No Load, PFM Mode
IPEAK
Peak switching current limit
Buck 3 enabled, switching in
PWM
η
Efficiency peak, Buck 3
ƒSW
Switching frequency
CIN
Input Capacitor
COUT
L
(5)
0.9 (4)
IOUT = 0.3 A
(5)
MAX
UNIT
15
50 (4)
µA
1.2
1.7 (4)
A
2.3 (4)
MHz
2
4.7
Output Filter Capacitor
(5)
Output Capacitor ESR
(5)
DC Line regulation
TYP
90%
1.75 (4)
Output Filter Inductance
ΔVOUT
MIN
(5)
(5)
DC Load regulation
0 mA ≤ IOUT ≤ 600 mA
(5)
10
10
100
20
µF
mΩ
2.2
µH
3.3 V ≤ VIN ≤ 5 V, IOUT = 600 mA
0.5
%/V
150 mA ≤ IOUT ≤ 600 mA
0.3
%/A
0.9
IFB
Feedback pin input bias
current
VFB = 1.2 V
RDS-ON-HS
High Side Switch On
Resistance
VIN = 2.6 V
RDS-ON-LS
Low Side Switch On
Resistance
5 (4)
µA
135
260
85
mΩ
190 (4)
STARTUP
TSTART
(1)
(2)
(3)
(4)
(5)
8
Internal soft-start (turn on
time) (5)
Startup from shutdown, VOUT = 0
V, no load, LC = recommended
circuit, using software enable, to
VOUT = 95% of final value
0.1
ms
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
BUCK normal operation is ensured if VIN ≥ VOUT+1 V.
Limits apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ 85°C.
Specification ensured by design. Not tested during production.
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7.9 LDO Electrical Characteristics (1) (2)
Unless otherwise noted, VIN = 5 V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C, unless otherwise noted.
PARAMETER
VOUT
Output voltage accurancy
TEST CONDITIONS
MIN
IOUT = 1 mA
–3%
TYP
(3)
3%
VOUT = 0 V
Short-circuit current limit
VDO
Dropout voltage
IOUT = 100 mA
Line regulation
3.3 V ≤ VIN ≤ 5.5 V, IOUT = 1 mA
5
Load regulation
1 mA ≤ IOUT ≤ 100 mA, VIN = 3.3 V, 5 V
5
eN
Output noise voltage (4)
10 Hz ≤ ƒ ≤ 100 kHz
PSSR
Power supply rejection
ratio (4)
tSTARTUP
Start-up time from
shutdown (4)
tTRANSIENT
Start-up transient
overshoot (4)
(1)
(2)
(3)
(4)
UNIT
(3)
0.3
ISC
ΔVOUT
MAX
VIN = 3.3 V, VOUT = 0 V
(4)
0.5
60
VIN = 5 V
10
VIN = 3.3 V
35
F = 10 kHz, COUT = 4.7
µF,
IOUT = 20 mA
VIN = 5 V
65
VIN = 3.3 V
40
COUT = 4.7 µF, IOUT =
100 mA
VIN = 5 V
45
VIN = 3.3 V
60
100 (3)
mV
µVRMS
dB
µs
30 (3)
mV
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Limits apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ 85°C.
Specification ensured by design. Not tested during production.
7.10 Comparators Electrical Characteristics (1)
(2)
Unless otherwise noted, VIN = 5 V where: VIN = VIN_B1 = VIN_B2 = VIN_B3. Limits apply for TJ = 25°C, unless otherwise noted.
SYMBOL
PARAMETER
TYP
MAX
VCOMP = 0 V
TEST CONDITIONS
MIN
0.1
2 (3)
VCOMP = 5 V
0.1
2 (3)
IVCOMP
VCOMP pin bias current
VCOMP_RISE
Comparator rising edge
trigger level
2.826
VCOMP_FALL
Comparator falling edge
trigger level
2.768
30 (3)
Output voltage high
IRQVOL
Output voltage low
tCOMP
Transition time of IRQ
output
(1)
(2)
(3)
µA
V
Hysteresis
IRQVOH
UNIT
60
80 (3)
0.8*VIN_IO (3)
0.2*VIN_IO (3)
6
15 (3)
mV
V
µsec
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Limits apply over the entire operating junction temperature range of −40°C ≤ TA = TJ ≤ 85°C.
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7.11 Typical Characteristics
200 µs/
1 1.00V/
VIN = 3.3V
1A load
1
VIN = 5V
1A load
BUCK1
1
VIN = 3.3 V
VOUT = 3 V
IOUT = 1 A
BUCK1
VIN = 5 V
Figure 1. Start-Up Of Buck 1
3.210
VIN = 5.0V
VIN = 3.3V
IOUT = 1 A
IOUT = 1mA
IOUT = 100mA
3.208
3206
3.206
3204
3.204
VOUT(V)
VOUT(mV)
3208
3202
3.202
3200
3.200
3198
3.198
3196
3.196
3194
3.194
3192
3.192
3190
3.190
0
20
40
60
80
IOUT(mA)
100
120
3.0
Figure 3. LDO VOUT vs. IOUT
3000
1810
2998
1808
2996
1806
2994
1804
2992
2990
2988
4.5 5.0
VIN(V)
5.5
6.0
1800
1798
1796
2984
1794
2982
1792
2980
VIN = 5 V
4.0
1802
2986
100
3.5
Figure 4. LDO VIN vs. VOUT
VOUT(mV)
VOUT(mV)
VOUT = 3 V
Figure 2. Start-Up Of Buck 1
3210
1790
300
500 700 900 1100 1300
IOUT(mA)
VOUT = 3 V
100
VIN = 5 V
Figure 5. Buck 1 VOUT vs. IOUT
10
200 µs/
1 1.00V/
150
200 250 300
IOUT(mA)
350
400
VOUT = 1.8 V
Figure 6. Buck 2 VOUT vs. IOUT
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3010
1015
3008
1013
3006
1011
3004
1009
VOUT(mV)
VOUT(mV)
Typical Characteristics (continued)
3002
3000
2998
1007
1005
1003
2996
1001
2994
999
2992
997
2990
100
150
200 250 300
IOUT(mA)
VIN = 5 V
350
995
150 200 250 300 350 400 450 500 550 600
IOUT(mA)
400
VOUT = 3 V
VIN = 5 V
Figure 7. Buck 2 VOUT vs. IOUT
VOUT = 1 V
Figure 8. Buck 3 VOUT vs. IOUT
1213
1.805
1211
1.800
1209
1.795
VOUT(V)
VOUT(mV)
1207
1205
1.790
1203
1201
1.785
1199
1197
1.780
1195
1.775
1193
150 200 250 300 350 400 450 500 550 600
IOUT(mA)
VIN = 5 V
VOUT = 1.2 V
3.0
VOUT = 1.8 V
Figure 9. Buck 3 VOUT vs. IOUT
4.5
5.0
IOUT = 400 mA
1.010
2.990
1.005
VOUT(V)
2.995
VOUT(V)
1.015
2.985
1.000
2.980
0.995
2.975
0.990
2.970
0.985
4.0
4.5
5.0
3.0
VIN(V)
VOUT = 3 V
4.0
VIN(V)
Figure 10. Buck 2 VOUT vs. VIN
3.000
3.5
3.5
IOUT = 400 mA
VOUT = 1 V
Figure 11. Buck 2 VOUT vs. VIN
3.5
4.0
VIN(V)
4.5
5.0
IOUT = 600 mA
Figure 12. Buck 3 VOUT vs VIN
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Typical Characteristics (continued)
1 1.00V/ 2 1.00V/
1.215
5.00 ms/
1.210
VOUT(V)
1.205
1.200
1.195
1.190
1.185
3.0
VOUT = 1.2 V
3.5
4.0
VIN(V)
4.5
1
VIN
2
LDO
5.0
IOUT = 600 mA
Figure 14. LDO Start-Up Time From VIN Rise
Figure 13. Buck 3 VOUT vs VIN
1 1.00V/ 2 1.00V/
1.00 ms/
1 1.00V/ 2 1.00V/
1
LDO
1
BUCK1
2
BUCK1
2
BUCK2
Figure 15. From LDO Start-Up To Buck 1 Start-Up
1 1.00V/ 2 1.00V/
1
BUCK2
2
BUCK3
1.00 ms/
Figure 16. From Buck 1 Start-Up To Buck 2 Start-Up
1.00 ms/
Figure 17. From Buck 2 Start-Up To Buck 3 Start-Up
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8 Detailed Description
The LM10506 is a highly efficient and integrated Power Management Unit for Systems-on-a-Chip (SoCs), ASICs,
and processors. It operates cooperatively and communicates with processors over an SPI interface with output
Voltage programmability and Standby Mode.
The device incorporates three high-efficiency synchronous buck regulators and one LDO that deliver four output
voltages from a single power source. The device also includes a SPI-programmable Comparator Block that
provides an interrupt output signal.
GND
GND
GND
LDO
VIN
CLK
DI
DO
CS
VIN_IO
8.1 Functional Block Diagram
SPI
LDO
RESET
CONTROL REGISTERS
STANDBY LOGIC
EN
VIN_B2
SW2
BUCK2
SW_B2
GND_B2
FB_B2
EN
HL_B2
VIN_B1
SW_B1
GND_B1
SEQUENCER
TSD
EN
SW1
BUCK1
UVLO
FB_B1
EN
OVLO
VIN_B3
EN
VCOMP
SW3
COMPARATOR
BUCK3
IRQ
SW_B3
GND_B3
FB_B3
HL_B3
8.2 Feature Description
8.2.1 Buck Regulators Operation
A buck converter contains a control block, a switching PFET connected between input and output, a synchronous
rectifying NFET connected between the output and ground and a feedback path. The following figure shows the
block diagram of each of the three buck regulators integrated in the device.
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Feature Description (continued)
CONTROL
G
CIN
P
D
D
N
S
L
SW
VOUT
G
FB
S
VIN
PVIN
U1
LM10506
COUT
PGND
GND
Figure 18. Buck Functional Diagram
During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows
current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the
current to a ramp with a slope of (VIN – VOUT)/L by storing energy in a magnetic field. During the second portion
of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the
NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter
capacitor and load, which ramps the inductor current down with a slope of (–VOUT)/L.
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage
across the load. The output voltage is regulated by modulating the PFET switch on time to control the average
current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the
switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter
capacitor. The output voltage is equal to the average voltage at the SW pin.
8.2.1.1 Buck Regulators Description
The LM10506 incorporates three high-efficiency synchronous switching buck regulators that deliver various
voltages from a single DC input voltage. They include many advanced features to achieve excellent voltage
regulation, high efficiency and fast transient response time. The bucks feature voltage mode architecture with
synchronous rectification.
Each of the switching regulators is specially designed for high-efficiency operation throughout the load range.
With a 2MHz typical switching frequency, the external L- C filter can be small and still provide very low output
voltage ripple. The bucks are internally compensated to be stable with the recommended external inductors and
capacitors as detailed in the application diagram. Synchronous rectification yields high efficiency for low voltage
and high output currents.
All bucks can operate up to a 100% duty cycle allowing for the lowest possible input voltage that still maintains
the regulation of the output. The lowest input to output dropout voltage is achieved by keeping the PMOS switch
on.
Additional features include soft-start, undervoltage lockout, bypass, and current and thermal overload protection.
To reduce the input current ripple, the device employs a control circuit that operates the 3 bucks at 120° phase.
These bucks are nearly identical in performance and mode of operation. They can operate in FPWM (forced
PWM) or automatic mode (PWM/PFM).
8.2.1.2 PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, a feed forward voltage inversely proportional to the input
voltage is introduced.
In Forced PWM Mode the bucks always operate in PWM mode regardless of the output current.
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Feature Description (continued)
In Automatic Mode, if the output current is less than 70 mA (typ.), the bucks automatically transition into PFM
(Pulse Frequency Modulation) operation to reduce the current consumption. At higher than 100 mA (typ.) they
operate in PWM mode. This increases the efficiency at lower output currents. The 30 mA (typ.) hysteresis is
designed in for stable Mode transition.
While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating
the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned
on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The
current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. In this
case the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock
turning off the NFET and turning on the PFET.
PWM Mode at
Moderate to
Heavy Loads
VOUT
PFM Mode at Light Load
Load current
increases, draws
Vout towards Low 2
PFM Threshold
High PFM
Threshold
~1.016*VOUT
Low1 PFM
Threshold
~1.008*VOUT
PFET on
until
LPFM
limit
reached
NFET on
drains
inductor
current
until
I inductor=0
High PFM
Voltage
Threshold
reached,
go into
idle mode
Low PFM
Threshold,
turn on
PFET
Load
current
increases
Low 2 PFM
Threshold,
switch back to
PWM mode
Low2 PFM
Threshold
VOUT
Time
Figure 19. PFM vs PWM Operation
8.2.1.3 PFM Operation (Bucks 1, 2 & 3)
At very light loads, Bucks 1, 2, and Buck 3 enter PFM mode and operate with reduced switching frequency and
supply current to maintain high efficiency.
Bucks 1, 2, and 3 will automatically transition into PFM mode when either of two conditions occurs for a duration
of 32 or more clock cycles:
1. The inductor current becomes discontinuous, or
2. The peak PMOS switch current drops below the IMODE level.
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output
voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on.
It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level
set for PFM mode.
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Feature Description (continued)
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold (see Figure 19), the PMOS switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output
switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this
‘idle’ mode is less than 100 µA, which allows the part to achieve high efficiencies under extremely light load
conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage
to approximately 1.6% above the nominal PWM output voltage.
If the load current should increase during PFM mode causing the output voltage to fall below the ‘low2’ PFM
threshold, the part will automatically transition into fixed-frequency PWM mode.
8.2.1.4 Soft Start
Each of the buck converters has an internal soft-start circuit that limits the in-rush current during startup. This
allows the converters to gradually reach the steady-state operating point, thus reducing startup stresses and
surges. During startup, the switch current limit is increased in steps.
For Bucks 1, 2 and 3 the soft start is implemented by increasing the switch current limit in steps that are
gradually set higher. The startup time depends on the output capacitor size, load current and output voltage.
Typical startup time with the recommended output capacitor of 10 µF is 0.2 ms to 1 ms. It is expected that in the
final application the load current condition will be more likely in the lower load current range during the startup.
8.2.1.5 Current Limiting
A current limit feature protects the device and any external components during overload conditions. In PWM
mode the current limiting is implemented by using an internal comparator that trips at current levels according to
the buck capability. If the output is shorted to ground the device enters a timed current limit mode where the
NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor
current has more time to decay, thereby preventing runaway.
8.2.1.6 Internal Synchronous Rectification
While in PWM mode, the bucks use an internal NFET as a synchronous rectifier to reduce the rectifier forward
voltage drop and the associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
8.2.1.7 Bypass FET Operation On Bucks 1 And 2
There is an additional bypass FET used on Buck 1. The FET is connected in parallel to High Side FET and
inductor. Buck 2 has no extra bypass FET – it uses High Side FET (PFET) for bypass operation. If Buck 1 input
voltage is greater than 3.5 V (2.6 V for Buck 2), the bypass function is disabled. The determination of whether or
not the buck regulators are in bypass mode or standard switching regulation is constantly monitored while the
regulators are enabled. If at any time the input voltage goes above 3.5 V (2.6 V for Buck 2) while in bypass
mode, the regulators will transition to normal operation.
When the bypass mode is enabled, the output voltage of the buck that is in bypass mode is not regulated;
instead, the output voltage follows the input voltage minus the voltage drop seen across the FET and DCR of the
inductor. The voltage drop is a direct result of the current flowing across those resistive elements. When Buck 1
transitions into bypass mode, there is an extra FET used in parallel along with the high side FET for transmission
of the current to the load. This added FET will help reduce the resistance seen by the load and decrease the
voltage drop. For Buck 2, the bypass function uses the same high side FET.
16
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Feature Description (continued)
Equivalent Circuit of Bypass Operation of Buck 1
High Side FET
VIN_B1
DCR
100 m Max.
Ideal Inductor,
no resistance
VOUT Buck1
SW_B1
Model of Inductor
Load
Capacitance
Load
Resistance
FB_B1
Bypass FET
Equivalent Circuit of Bypass Operation of Buck 2
High Side FET
VIN_B2
DCR
100 m Max.
Ideal Inductor,
no resistance
VOUT Buck2
SW_B2
Model of Inductor
Load
Resistance
Load
Capacitance
Figure 20. Bucks 1 and 2 Bypass Operations
8.2.1.8 Low Dropout Operation
The device can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support.
In this way the output voltage will be controlled down to the lowest possible input voltage. When the device
operates near 100% duty cycle, output voltage ripple is approximately 25 mV.
The minimum input voltage needed to support the output voltage:
VIN_MIN=VOUT+ILOAD*(RDSON_PFET+RIND), where
• ILOAD = Load Current
• RDSON_PFET = Drain to source resistance of PFET (high side) switch in the triode region
• RIND = Inductor resistance
8.2.1.9 Out of Regulation
When any of the Buck outputs are taken out of regulation (below 85% of the output level) the device will start a
shutdown sequence and all other outputs will switch off normally. The device will restart when the forced out-ofregulation condition is removed.
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8.3 Device Functional Modes
8.3.1 Start-Up Sequence
The start-up mode of the LM10506 will depend on the input voltage. Once VIN reaches the UVLO threshold, there
is a 15-ms delay before the LM10506 determines how to set up the buck regulators. If VIN is below 3.6 V, then
Bucks 1 and 2 will be in bypass mode, see Bypass FET Operation On Bucks 1 And 2 for functionality
description. If the VIN voltage is greater than 3.6 V, the bucks will start up as the standard regulators. The 3 buck
regulators are staggered during start-up to avoid large inrush currents. There is a fixed delay of 2 ms between
the start-up of each regulator.
The Start-up Sequence will be:
1. 15 ms (±30%) delay after VIN above UVLO
2. LDO → 3.2 V → 3.2 V
3. 2 ms delay
4. Buck 1 → 3 V → 3 V
5. 2 ms delay
6. Buck 2 → 3 V or if H/L_B2 = Low → 1.8 V
– (For LM10506-A Buck 2 → 2 V or if H/L_B2 = Low → 1.8 V)
7. 2 ms delay
8. Buck 3 → 1.2 V or if H/L_B3 = Low → 1 V
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Device Functional Modes (continued)
5.7V
5.6V
3.5V
3.5V
2.9V
2.6V
~2.25V
VIN
BG/BIAS
UVLO
15 ms
15 ms
LDO
3.2V
3.5V
3.5V
2 ms
2 ms
2 ms 1.1V
Buck1
2.6V
2 ms
2 ms
Buck 2 (LM10506 /-A)
2 ms
2 ms
2 ms 1.1V
2 ms
Buck3
Comparator
OVLO
B1 en Bypass
B2 en Bypass
BYPASS OPERATION
Standby
UVLO
STARTUP
BYPASS
OPERATION
OVLO
STARTUP
STANDBY
UVLO
Figure 21. Operating Modes
8.3.2 Power-On Default And Device Enable
The device is always enabled and the LDO is always on, unless outside of operating voltage range. There is no
LM10506 ENABLE Pin. Once VIN reaches a minimum required input Voltage the power-up sequence will be
started automatically and the startup sequence will be initiated. Once the device is started, the output voltage of
the Bucks 1 and 2 can be individually disabled by accessing their corresponding BKEN register bits (BUCK
CONTROL).
8.3.3 RESET Pin Function
The RESET pin is internally pulled high. If the reset pin is pulled low, the device will perform a complete reset of
all the registers to their default states. This means that all of the voltage settings on the regulators will go back to
their default states.
8.3.4 Standby Function
The Device can be programmed into Standby mode. There are 2 ways for doing that:
1. STANDBY pin
2. Programming via SPI
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Device Functional Modes (continued)
8.3.4.1 STANDBY Pin
When the STANDBY pin is asserted high, the LM10506 will enter Standby Mode. While in Standby Mode, Buck 1
and Buck 2 are disabled. Buck 3’s output voltage is transitioned to the PSML (Programmable Standby Mode
Level) as set by register 0x09. The STANDBY pin is internally pulled down, and there is a 1 second delay during
powerup before the state of the STANDBY pin is checked.
NOTE
If Buck 1 and Buck 2 are already disabled, and the STANDBY pin is asserted high, then
Buck 3 will not go to PSML – for further instructions, see STANDBY Programming via SPI.
Bucks 1 and 2 will be ramped down when the disable signal is given. Buck 1 starts ramping 2 ms after Buck 2
has started ramping.
Entering Standby Sequence will be:
1. Buck 3 → PSML (Programmable Standby Mode Level)
2. 2 ms delay
3. Buck 2 → Disabled
4. 2 ms delay
5. Buck 1 → Disabled
An internal pulldown resistor 22 kΩ (±30%) is attached to the FB pin of Buck 1 and Buck 2. The outputs of Buck
1 and 2 are pulled to ground level when they are disabled to discharge any residual charge present in the output
circuitry. When STANDBY transitions to a low, Buck 1 is again enabled followed by Buck 2. Buck 3 will go back
to its previous state.
When waking up from Standby, the sequence will be:
1. Buck 1 → Previous State
2. 2 ms delay
3. Buck 2 and Buck 3 transition together → Previous State
8.3.4.2 Standby Programming Via SPI
There is no bit which has the same function as the STANDBY pin. There is only one requirement programming
LM10506 into Standby Mode via SPI. Setting LDO Sleep Mode bit high must be the last move when entering
Standby Mode and programming the bit low when waking from Standby Mode must be the first move. Disabling
or programming the Bucks to new level is the user’s decision based on power consumption and other
requirements.
The following section describes how to program the chip into Standby Mode corresponding to STANDBY PIN
function.
To program the LM10506 to Standby Mode via SPI Buck 1 and Buck 2 must be disabled by host device
(Register 0x0A bit 1 and 0). Buck 3 must be programmed to desired level using Register 0x00. After Buck 3 has
finished ramping LDO Sleep Mode bit must be set high (Register 0x0E bit 1). To wake LM10506 from Standby
Mode LDO Sleep Mode bit must be set low (Register 0x0E bit 1). Bucks 1 and 2 must be enabled. Buck 3
voltage must be programmed to previous output level. For LM10506 -C, -D,when Buck 1 is re-enabled upon
exiting STANDBY, soft start will engage.
8.3.4.3 Standby Mode, Operational Constraints
In Standby mode the device is in a low power mode. All internal clocks are turned off to conserve power and
Buck 3 will only operate in PFM mode. While limited to PFM mode the loading on Buck 3 should be kept below
80 mA typ. to remain below the PFM/PWM threshold and avoid device shutdown. It is recommended that the
device loading should be lowered accordingly prior to entering standby mode via STANDBY.
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Device Functional Modes (continued)
8.3.5 HL_B2, HL_B3 Function
The HL_B2/3 pins are digital pins which control alternate voltage selections of Buck 2 and Buck 3, respectively.
HL_B2 has an internal pulldown which defaults to a 1.8-V output voltage selection for Buck 2. Alternatively, if
HL_B2 is driven high, an output voltage of 3 V (or 2 V for LM10506-A) is selected. HL_B3 has an internal pull-up
which defaults to a 1.2-V output voltage selection for Buck 3. Alternatively, if HL_B3 is driven low, an output
voltage of 1 V is selected. The pull-up resistor is connected to the main input voltage. Transitions of the pins will
not affect the output voltage, the state is only checked during start-up.
8.3.6 Undervoltage Lockout (UVLO)
The VIN voltage is monitored for a supply under voltage condition, for which the operation of the device can not
be ensured. The part will automatically disable Buck 3. To prevent unstable operation, the undervoltage lockout
(UVLO) has a hysteresis window of about 300 mV. An UVLO will force the device into the reset state, all internal
registers are reset. Once the supply voltage is above the UVLO hysteresis, the device will initiate a power-up
sequence and then enter the active state.
Buck 1 and Buck 2 will remain in bypass mode after VIN passes the UVLO until VIN reaches approximately 1.9 V.
When Buck 2 is set to 1.8 V, the voltage will jump from 1.8 V to VUVLO_FALLING, and then follow VIN.
For LM10506 -C, -D,when Buck 1 is re-enabled upon exiting STANDBY, soft start will engage.
The LDO and the Comparator will remain functional past the UVLO threshold until VIN reaches approximately
2.25 V.
8.3.7 Overvoltage Lockout (OVLO)
The VIN voltage is monitored for a supply over voltage condition, for which the operation of the device cannot be
ensured. The purpose of overvoltage lockout (OVLO) is to protect the part and all other consumers connected to
the PMU outputs from any damage and malfunction. Once VIN rises over 5.7 V all the Bucks, and LDO will be
disabled automatically. To prevent unstable operation, the OVLO has a hysteresis window of about 100 mV. An
OVLO will force the device into the reset state; all internal registers are reset. Once the supply voltage is below
the OVLO hysteresis, the device will initiate a power-up sequence, and then enter the active state. Operating
maximum input voltage at which parameters are ensured is 5.5 V. Absolute maximum of the device is 6 V.
8.3.8 Interrupt Enable/Interrupt Status
The LM10506 has 2 interrupt registers, INTERRUPT ENABLE and INTERRUPT STATUS. These registers can
be read via the serial interface. The interrupts are not latched to the register and will always represent the current
state and will not be cleared on a read.
If interrupt condition is detected, then corresponding bit in the INTERRUPT STATUS register (0x0D) is set to '1',
and IRQ output is asserted. There are 5 interrupt generating conditions:
• Buck 3 output is over flag level (90% when rising, 85% when falling)
• Buck 2 output is over flag level (90% when rising, 85% when falling)
• Buck 1 output is over flag level (90% when rising, 85% when falling)
• LDO is over flag level (90% when rising, 85% when falling
• Comparator input voltage crosses over selected threshold
Reading the interrupt register will not release IRQ output. Interrupt generation conditions can be individually
enabled or disabled by writing respective bits in INTERRUPT ENABLE register (0x0C) to '1' or '0'.
8.3.9 Thermal Shutdown (TSD)
The temperature of the silicon die is monitored for an over-temperature condition, for which the operation of the
device can not be ensured. The part will automatically be disabled if the temperature is too high. The thermal
shutdown (TSD) will force the device into the reset state. In reset, all circuitry is disabled. To prevent unstable
operation, the TSD has a hysteresis window of about 20°C. Once the temperature has decreased below the TSD
hysteresis, the device will initiate a powerup sequence and then enter the active state. In the active state, the
part will start up as if for the first time, all registers will be in their default state.
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Device Functional Modes (continued)
8.3.10 Comparator
The comparator on the LM10506 takes its inputs from the VCOMP pin and an internal threshold level which is
programmed by the user. The threshold level is programmable between 2 V and 4 V with a step of 31 mV and a
default comp code of 0x19. The output of the comparator is the IRQ pin. Its polarity can be changed using
Register 0x0E bit 0. If IRQ_polarity = 0 → Active low (default) is selected, then the output is low if VCOMP value is
greater than the threshold level. The output is high if the VCOMP value is less than the threshold level. If
IRQ_polarity = 1 → Active high is selected then the output is high if VCOMP value is greater than the threshold
level. The output is low if the VCOMP value is less than the threshold level. There is some hysteresis when VCOMP
transitions from high to low, typically 60 mV. There is a control bit in register 0x0B, comparator control, that can
double the hysteresis value.
VTHRES
+
IRQ
-
VCOMP
IRQ
VCOMP
Delay due to
hysteresis
VTHRES
Figure 22.
8.4 Programming
8.4.1 SPI Data Interface
The device is programmable via 4-wire SPI Interface. The signals associated with this interface are CS, DI, DO
and CLK. Through this interface, the user can enable/disable the device, program the output voltages of the
individual bucks and of course read the status of Flag registers.
By accessing the registers in the device through this interface, the user can get access and control the operation
of the buck controllers and program the reference voltage of the comparator in the device.
CS
CLK
DI
1
1
2
0
3
A4
Write
Command
DO
7
A3
A2
A1
A0
9
0
D7
16
D6
D5
Register Address
D4
D3
D2
D1
D0
Write Data
0
Figure 23. SPI Interface Write
•
22
Data In (DI)
– 1 to 0 Write Command
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Programming (continued)
•
– A4to A0 Register address to be written
– D7 to D0 Data to be written
Data Out (DO)
– All Os
CS
CLK
DI
1
2
1
1
3
7
A4
Read
Command
A3
A2
A1
A0
9
16
0
Register Address
DO
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
Figure 24. SPI Interface Read
•
•
Data In (DI)
– 1 to 1 Read Command
– A4to A0 Register address to be read
Data Out (DO)
– D7 to D0 Data Read
8.4.1.1 Registers Configurable via the SPI Interface
ADDR
0x00
0x07
REG NAME
Buck 3 Voltage
Buck 1 Voltage
BIT
R/W
7
—
DEFAULT
DESCRIPTION
NOTES
6
R/W
Buck 3 Voltage Code[6]
HL_B3 = 1 → 0x64 (1.2 V)
5
R/W
Buck 3 Voltage Code[5]
HL_B3 = 0 → 0x3C (1 V)
4
R/W
Buck 3 Voltage Code[4]
3
R/W
2
R/W
Buck 3 Voltage Code[2]
1
R/W
Buck 3 Voltage Code[1]
0
R/W
Buck 3 Voltage Code[0]
7
—
6
—
5
R/W
4
R/W
3
R/W
2
R/W
Buck 1 Voltage Code[2]
1
R/W
Buck 1 Voltage Code[1]
0
R/W
Buck 1 Voltage Code[0]
Reset default:
See Notes
Buck 3 Voltage Code[3]
Range: 0.7 V to 1.335 V
Reset default:
0x26 (3 V)
Buck 1 Voltage Code[5]
See Notes
Buck 1 Voltage Code[4]
Range: 1.1 V to 3.6 V
Buck 1 Voltage Code[3]
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Programming (continued)
ADDR
0x08
0x09
0x0A
0x0B
0x0C
24
REG NAME
Buck 2 Voltage
Standby Mode
Voltage for
Buck 3
Buck Control
Comparator
Control
Interrupt Enable
BIT
R/W
7
—
DEFAULT
Reset default:
6
—
HL_B2 = 1 → 0x26 (3 V)/
0x12 (2 V for LM10506−A)
5
R/W
Buck 2 Voltage Code[5]
4
R/W
Buck 2 Voltage Code[4]
3
R/W
Buck 2 Voltage Code[3]
2
R/W
Buck 2 Voltage Code[2]
1
R/W
Buck 2 Voltage Code[1]
0
R/W
Buck 2 Voltage Code[0]
7
R/W
6
R/W
Buck 3 Voltage Code[6]
HL_B3 = 1 → 0x53 (1.115 V)
5
R/W
Buck 3 Voltage Code[5]
HL_B3 = 0 → 0x2E (0.93 V)
4
R/W
3
R/W
2
R/W
Buck 3 Voltage Code[2]
1
R/W
Buck 3 Voltage Code[1]
0
R/W
7
R
6
—
See Notes
DESCRIPTION
NOTES
HL_B2 = 0 → 0x0E (1.8 V)
Range: 1.1 V to 3.6 V
Reset default:
See Notes
Buck 3 Voltage Code[4]
Buck 3 Voltage Code[3]
Buck 3 Voltage Code[0]
1
BK3EN
Reads Buck 3 enable status
5
—
4
R/W
0
BK1FPWM
Buck 1 forced PWM mode when high
3
R/W
0
BK2FPWM
Buck 2 forced PWM mode when high
2
R/W
0
BK3FPWM
Buck 3 forced PWM mode when high
1
R/W
1
BK1EN
Enables Buck 1 0-disabled, 1-enabled
0
R/W
1
BK2EN
Enables Buck 2 0-disabled, 1-enabled
7
R/W
0
Comp_hyst[0]
Doubles Comparator hysteresis
6
R/W
0
Comp_thres[5]
Programmable range of 2 V to 4 V, step
size = 31.75 mV
5
R/W
1
Comp_thres[4]
4
R/W
1
Comp_thres[3]
Comparator Threshold reset default:
0x19
3
R/W
0
Comp_thres[2]
Comp_hyst = 1 → min 80 mV hysteresis
2
R/W
0
Comp_thres[1]
Comp_hyst = 0 → min 40 mV hysteresis
1
R/W
1
Comp_thres[0]
0
R/W
1
COMPEN
7
—
6
—
5
—
4
R/W
0
LDO OK
3
R/W
0
Buck 3 OK
2
R/W
0
Buck 2 OK
1
R/W
0
Buck 1 OK
0
R/W
1
Comparator
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Comparator enable
Interrupt comp event
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Programming (continued)
ADDR
0x0D
0x0E
REG NAME
Interrupt Status
MISC Control
BIT
R/W
7
—
DEFAULT
DESCRIPTION
NOTES
6
—
5
—
4
R
LDO OK
LDO is greater than 90% of target
3
R
Buck 3 OK
Buck 3 is greater than 90% of target
2
R
Buck 2 OK
Buck 2 is greater than 90% of target
1
R
Buck 1 OK
Buck 1 is greater than 90% of target
0
R
Comparator
Comparator output is high
7
—
6
—
5
—
4
—
3
—
2
—
1
R/W
0
LDO Sleep Mode
LDO goes into extra power save mode
0
R/W
0
IRQ Polarity
IRQ_polarity = 0→Active low IRQ
IRQ_polarity = 1→Active high IRQ
8.4.1.1.1 ADDR 0x07& 0x08: Buck 1 And Buck 2 Voltage Code And VOUT Level Mapping
VOLTAGE CODE
VOLTAGE (V)
VOLTAGE CODE
VOLTAGE (V)
0x00
1.10
0x20
2.70
0x01
1.15
0x21
2.75
0x02
1.20
0x22
2.80
0x03
1.25
0x23
2.85
0x04
1.30
0x24
2.90
0x05
1.35
0x25
2.95
0x06
1.40
0x26
3.00
0x07
1.45
0x27
3.05
0x08
1.50
0x28
3.10
0x09
1.55
0x29
3.15
0x0A
1.60
0x2A
3.20
0x0B
1.65
0x2B
3.25
0x0C
1.70
0x2C
3.30
0x0D
1.75
0x2D
3.35
0x0E
1.80
0x2E
3.40
0x0F
1.85
0x2F
3.45
0x10
1.90
0x30
3.50
0x11
1.95
0x31
3.55
0x12
2.00
0x32
3.60
0x13
2.05
0x33
3.60
0x14
2.10
0x34
3.60
0x15
2.15
0x35
3.60
0x16
2.20
0x36
3.60
0x17
2.25
0x37
3.60
0x18
2.30
0x38
3.60
0x19
2.35
0x39
3.60
0x1A
2.40
0x3A
3.60
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VOLTAGE CODE
VOLTAGE (V)
VOLTAGE CODE
VOLTAGE (V)
0x1B
2.45
0x3B
3.60
0x1C
2.50
0x3C
3.60
0x1D
2.55
0x3D
3.60
0x1E
2.60
0x3E
3.60
0x1F
2.65
0x3F
3.60
8.4.1.1.2 ADDR 0x00 & 0x09: Buck 3 Voltage Code And VOUT Level Mapping
26
VOLTAGE
CODE
VOLTAGE (V)
VOLTAGE
CODE (V)
VOLTAGE (V)
VOLTAGE
CODE
VOLTAGE
(V)
VOLTAGE
CODE
VOLTAGE (V)
0x00
0.700
0x20
0.860
0x40
1.020
0x60
1.180
0x01
0.705
0x21
0.865
0x41
1.025
0x61
1.185
0x02
0.710
0x22
0.870
0x42
1.030
0x62
1.190
0x03
0.715
0x23
0.875
0x43
1.035
0x63
1.195
0x04
0.720
0x24
0.880
0x44
1.040
0x64
1.200
0x05
0.725
0x25
0.885
0x45
1.045
0x65
1.205
0x06
0.730
0x26
0.890
0x46
1.050
0x66
1.210
0x07
0.735
0x27
0.895
0x47
1.055
0x67
1.215
0x08
0.740
0x28
0.900
0x48
1.060
0x68
1.220
0x09
0.745
0x29
0.905
0x49
1.065
0x69
1.225
0x0A
0.750
0x2A
0.910
0x4A
1.070
0x6A
1.230
0x0B
0.755
0x2B
0.915
0x4B
1.075
0x6B
1.235
0x0C
0.760
0x2C
0.920
0x4C
1.080
0x6C
1.240
0x0D
0.765
0x2D
0.925
0x4D
1.085
0x6D
1.245
0x0E
0.770
0x2E
0.930
0x4E
1.090
0x6E
1.250
0x0F
0.775
0x2F
0.935
0x4F
1.095
0x6F
1.255
0x10
0.780
0x30
0.940
0x50
1.100
0x70
1.260
0x11
0.785
0x31
0.945
0x51
1.105
0x71
1.265
0x12
0.790
0x32
0.950
0x52
1.110
0x72
1.270
0x13
0.795
0x33
0.955
0x53
1.115
0x73
1.275
0x14
0.800
0x34
0.960
0x54
1.120
0x74
1.280
0x15
0.805
0x35
0.965
0x55
1.125
0x75
1.285
0x16
0.810
0x36
0.970
0x56
1.130
0x76
1.290
0x17
0.815
0x37
0.975
0x57
1.135
0x77
1.295
0x18
0.820
0x38
0.980
0x58
1.140
0x78
1.300
0x19
0.825
0x39
0.985
0x59
1.145
0x79
1.305
0x1A
0.830
0x3A
0.990
0x5A
1.150
0x7A
1.310
0x1B
0.835
0x3B
0.995
0x5B
1.155
0x7B
1.315
0x1C
0.840
0x3C
1.000
0x5C
1.160
0x7C
1.320
0x1D
0.845
0x3D
1.005
0x5D
1.165
0x7D
1.325
0x1E
0.850
0x3E
1.010
0x5E
1.170
0x7E
1.330
0x1F
0.855
0x3F
1.015
0x5F
1.175
0x7F
1.335
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8.4.1.1.3 ADDR0x0B: Comparator Threshold Mapping
VOLTAGE CODE
VOLTAGE (V)
VOLTAGE CODE
VOLTAGE (V)
0x00
2.000
0x20
3.016
0x01
2.032
0x21
3.048
0x02
2.064
0x22
3.080
0x03
2.095
0x23
3.111
0x04
2.127
0x24
3.143
0x05
2.159
0x25
3.175
0x06
2.191
0x26
3.207
0x07
2.222
0x27
3.238
0x08
2.254
0x28
3.270
0x09
2.286
0x29
3.302
0x0A
2.318
0x2A
3.334
0x0B
2.349
0x2B
3.365
0x0C
2.381
0x2C
3.397
0x0D
2.413
0x2D
3.429
0x0E
2.445
0x2E
3.461
0x0F
2.476
0x2F
3.492
0x10
2.508
0x30
3.524
0x11
2.540
0x31
3.556
0x12
2.572
0x32
3.588
0x13
2.603
0x33
3.619
0x14
2.635
0x34
3.651
0x15
2.667
0x35
3.683
0x16
2.699
0x36
3.715
0x17
2.730
0x37
3.746
0x18
2.762
0x38
3.778
0x19
2.794
0x39
3.810
0x1A
2.826
0x3A
3.842
0x1B
2.857
0x3B
3.873
0x1C
2.889
0x3C
3.905
0x1D
2.921
0x3D
3.937
0x1E
2.953
0x3E
3.969
0x1F
2.984
0x3F
4.000
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9 Application and Implementation
9.1 Application Information
The LM10506 device provides 4 regulated outputs from 3 step-down switching regulators and one linear
regulator. The regulated outputs are achieved using a minimum of external components. To support low load
conditions within an application the device may be placed in a low power mode - STANDBY.
A 4-wire SPI interface may be used to reconfigure the device outputs and return an indication of output status. A
separate device output provides an Interrupt signal when the device status changes. All programmed settings
may be returned to default state via a RESET input.
9.2 Typical Application
IO input
`
supply
C9
2.2 F
LM10506
Reset
VIN_IO
STANDBY
CS
SPI
DI
System
DO
Control
C8
2.2 F
Power Supply
3.3/5.0V
CONTROL LOGIC and REGISTERS
CLK
VIN
VIN_B1
C5
4.7 F
VIN_B2
C6
4.7 F
VCOMP
COMP
LDO
IRQ
3.2V
LDO
SW_B1
BUCK1
C4
4.7 F
L1
2.2 H
FB_B1
L2
SW_B2
BUCK2
2.2 H
L3
VIN_B3
H/L B3
H/L B2
GND
GND
BUCK3
GND
C1
22 F
1.1V to 3.6V
C2
22 F
FB_B2
SW_B3
C7
4.7 F
1.1V to 3.6V
2.2 H
FB_B3
Host
Controller
VHOST
100 mA
Host 1
Domain
VCC
1.3A
Host 2
Domain
VCCQ
400 mA
0.7V to1.335V
C3
22 F
Host 3
Domain
VCORE
600 mA
Figure 25. LM10506 Typical Application
28
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Typical Application (continued)
9.2.1 Design Requirements
Table 2. Output Voltage Configurations for LM10506
REGULATOR
VOUT if
H/L=HIGH
(B2, B3)
VOUT if
H/L=LOW
(B2, B3)
VOUT if
STANDBY=HIGH
(STANDBY MODE)
VOUT
MAXIMUM
OUTPUT
CURRENT
TYPICAL
APPLICATIO
N
COMMENTS
Buck 1 (1)
3V
3V
Off
1.1 V to 3.6 V;
50-mV steps
1.3 A
VCC
Flash
Buck 2 (1)
3V
1.8 V
Off
1.1 V to 3.6 V;
50-mV steps
400 mA
VCCQ
Interface
Buck 3 (1)
1.2 V
1V
VNOM - 7%
0.7 V to 1.335 V;
5-mV steps
600 mA
VCORE
Core
LDO
3.2 V
3.2 V
3.2 V
N/A
100 mA
VHOST
controller
Reference for
Digital
(1)
Default voltage values are determined when working in PWM mode. Voltage may be 0.8-1.6% higher when in PFM mode.
Table 3. Output Voltage Configurations for LM10506-A
REGULATOR
VOUT if
H/L=HIGH
(B2, B3)
VOUT if
H/L=LOW
(B2, B3)
VOUT if
STANDBY=HIGH
(STANDBY MODE)
VOUT
MAXIMUM
OUTPUT
CURRENT
TYPICAL
APPLICATIO
N
COMMENTS
Buck 1 (1)
3V
3V
Off
1.1 V to 3.6 V;
50-mV steps
1.3 A
VCC
Flash
Buck 2 (1)
2V
1.8 V
Off
1.1 V to 3.6 V;
50-mV steps
400 mA
VCCQ
Interface
Buck 3 (1)
1.2 V
1V
VNOM - 7%
0.7 V to 1.335 V;
5-mV steps
600 mA
VCORE
Core
LDO
3.2 V
3.2 V
3.2 V
N/A
100 mA
VHOST
controller
Reference for
Digital
(1)
Default voltage values are determined when working in PWM mode. Voltage may be 0.8-1.6% higher when in PFM mode.
9.2.2 Detailed Design Procedure
9.2.2.1 Input Voltage
VIN, VIN_B1, VIN_B2, and VIN_B3 must all be connected to the same power source.
9.2.2.2 Standby Mode
Ensure that the device is in a low power mode before entering Standby and throughout the Standby phase. In
Standby mode the device is in a low power mode in which all internal clocks are turned off to conserve power
and Buck 3 will only operate in PFM mode. While limited to PFM mode the loading on Buck 3 should be kept
below 80 mA (typ.) to remain below the PFM/PWM threshold and avoid device shutdown.
9.2.2.3 External Components Selection
All three switchers require an input capacitor and an output inductor-capacitor filter. These components are
critical to the performance of the device. All three switchers are internally compensated and do not require
external components to achieve stable operation. The output voltages of the bucks can be programmed through
the SPI pins.
9.2.2.3.1 Output Inductors & Capacitors Selection
There are several design considerations related to the selection of output inductors and capacitors:
• Load transient response
• Stability
• Efficiency
• Output ripple voltage
• Overcurrent ruggedness
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The device has been optimized for use with nominal LC values as shown in the Typical Application Circuit.
9.2.2.3.2 Inductor Selection
The recommended inductor values are shown in Typical Application Diagram. It is important to ensure the
inductor core does not saturate during any foreseeable operational situation. The inductor should be rated to
handle the peak load current plus the ripple current:
Care should be taken when reviewing the different saturation current ratings that are specified by different
manufacturers. Saturation current ratings are typically specified at 25°C, so ratings at maximum ambient
temperature of the application should be requested from the manufacturer.
IL(MAX) = ILOAD(MAX) + û IRIPPLE
= ILOAD(MAX) +
D x (VIN - VOUT)
2 x L x FS
D x (VIN - VOUT)
~ ILOAD(MAX) +
(A typ.),
~
2 x 2.2 x 2.0
D = VOUT , FS = 2 MHz, L = 2.2 µH
VIN
(1)
There are two methods to choose the inductor saturation current rating:
9.2.2.3.2.1 Recommended Method For Inductor Selection:
The best way to ensure the inductor does not saturate is to choose an inductor that has saturation current rating
greater than the maximum device current limit, as specified in the Electrical Characteristics tables. In this case
the device will prevent inductor saturation by going into current limit before the saturation level is reached.
9.2.2.3.2.2 Alternate Method For Inductor Selection:
If the recommended approach cannot be used care must be taken to ensure that the saturation current is greater
than the peak inductor current:
ISAT > ILPEAK
IRIPPLE
2
D x (VIN ± VOUT)
IRIPPLE =
L x FS
VOUT
D=
VIN x EFF
ILPEAK = IOUTMAX +
•
•
•
•
•
•
•
•
•
•
ISAT: Inductor saturation current at operating temperature
ILPEAK: Peak inductor current during worst case conditions
IOUTMAX: Maximum average inductor current
IRIPPLE: Peak-to-Peak inductor current
VOUT: Output voltage
VIN: Input voltage
L: Inductor value in Henries at IOUTMAX
F: Switching frequency, Hertz
D: Estimated duty factor
EFF: Estimated power supply efficiency
(2)
ISAT may not be exceeded during any operation, including transients, startup, high temperature, worst-case
conditions, etc.
30
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9.2.2.3.2.2.1 Suggested Inductors and Their Suppliers
The designer should choose the inductors that best match the system requirements. A very wide range of
inductors are available as regarding physical size, height, maximum current (thermally limited, and inductance
loss limited), series resistance, maximum operating frequency, losses, etc. In general, smaller physical size
inductors will have higher series resistance (DCR) and implicitly lower overall efficiency is achieved. Very lowprofile inductors may have even higher series resistance. The designer should try to find the best compromise
between system performance and cost.
Table 4. Recommended Inductors
VALUE (µH)
MANUFACTURER
PART NUMBER
DCR (mΩ)
CURRENT (A)
PACKAGE
2.2
Murata
LQH55PN2R2NR0L
31
2.5
2220
2.2
TDK
NLC565050T-2R2K-PF
60
1.3
2220
2.2
Murata
LQM2MPN2R2NG0
110
1.2
806
2.2
Coilcraft
LPS3015-222MLB
110
2.0
3015
2.2
Vishay
IFSC-1008AB-ER-2R2
90
2.15
2520
9.2.2.3.2.3 Output And Input Capacitors Characteristics
CAP VALUE (% of NOMINAL 1 PF)
Special attention should be paid when selecting these components. As shown in Figure 26, the DC bias of these
capacitors can result in a capacitance value that falls below the minimum value given in the recommended
capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size
capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions, as some capacitor sizes (for example, 0402) may not
be suitable in the actual application.
0603, 10V, X5R
100
80
60
0402, 6.3V, X5R
40
20
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 26. Typical Variation In Capacitance vs.
DC Bias
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to 125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has
a similar tolerance over a reduced temperature range of −55°C to 85°C. Many large value ceramic capacitors,
larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by
more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and
Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 44 µF range. Another
important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it
would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the
same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the
temperature goes from 25°C down to −40°C, so some guard band must be allowed.
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9.2.2.3.2.3.1 Output Capacitor Selection
The output capacitor of a switching converter absorbs the AC ripple current from the inductor and provides the
initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple
current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor
can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on the frequency
of the ripple current. Ceramic capacitors have very low ESR and remain capacitive up to high frequencies. Their
inductive component can usually be neglected at the frequency ranges at which the switcher operates.
COUT
L
ESR
SW1/2/3
VOUT1/2/3
OUTPUT
CAPACITOR
The output-filter capacitor smooths out the current flow from the inductor to the load and helps maintain a steady
output voltage during transient load changes. It also reduces output voltage ripple. These capacitors must be
selected with sufficient capacitance and low enough ESR to perform these functions.
Note that the output voltage ripple increases with the inductor current ripple and the Equivalent Series
Resistance of the output capacitor (ESRCOUT). Also note that the actual value of the capacitor’s ESRCOUT is
frequency and temperature dependent, as specified by its manufacturer. The ESR should be calculated at the
applicable switching frequency and ambient temperature.
D x (VIN - VOUT)
V
üIRIPPLE
and D = OUT
where üIRIPPLE =
VOUT-RIPPLE-PP =
2 x L x FS
8 x FS x COUT
VIN
(3)
Output ripple can be estimated from the vector sum of the reactive (capacitance) voltage component and the real
(ESR) voltage component of the output capacitor where:
VOUT-RIPPLE-PP =
2
V
2
ROUT
+V
COUT
(4)
where:
VROUT = IRIPPLE x ESRCOUT and VCOUT =
•
•
•
IRIPPLE
8 x FS x COUT
VOUT-RIPPLE-PP: estimated output ripple,
VROUT: estimated real output ripple,
VCOUT: estimated reactive output ripple.
(5)
The device is designed to be used with ceramic capacitors on the outputs of the buck regulators. The
recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper
tolerances over voltage and temperature. The recommended value for the output capacitors is 22 μF, 6.3V with
an ESR of 2 mΩ or less. The output capacitors need to be mounted as close as possible to the output/ground
pins of the device.
Table 5. Recommended Output Capacitors
32
MODEL
TYPE
VENDOR
VOLTAGE RATING (V)
CASE SIZE
08056D226MAT2A
Ceramic, X5R
AVX Corporation
6.3
0805, (2012)
C0805L226M9PACTU
Ceramic, X5R
Kemet
6.3
0805, (2012)
ECJ-2FB0J226M
Ceramic, X5R
Panasonic - ECG
6.3
0805, (2012)
JMK212BJ226MG-T
Ceramic, X5R
Taiyo Yuden
6.3
0603, (1608)
C2012X5R0J226M
Ceramic, X5R
TDK Corporation
6.3
0603, (1608)
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9.2.2.3.2.3.2 Input Capacitor Selection
There are 3 buck regulators in the LM10506 device. Each of these buck regulators has its own input capacitor
which should be located as close as possible to their corresponding SWx_VIN and SWx_GND pins, where x
designates Buck 1, 2, or 3. The 3 buck regulators operate at 120° out of phase, which means that they switch on
at equally spaced intervals, in order to reduce the input power rail ripple. It is recommended to connect all the
supply/ground pins of the buck regulators, SWx_VIN to two solid internal planes located under the device. In this
way, the 3 input capacitors work together and further reduce the input current ripple. A larger tantalum capacitor
can also be located in the proximity of the device.
The input capacitor supplies the AC switching current drawn from the switching action of the internal power
FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor
is large. The input capacitor must be rated to handle both the RMS current and the dissipated power.
The input capacitor must be rated to handle this current:
IRMS_CIN = IOUT
VOUT (VIN - VOUT)
VIN
(6)
The power dissipated in the input capacitor is given by:
PD_CIN = I2RMS_CIN x RESR_CIN
(7)
The device is designed to be used with ceramic capacitors on the inputs of the buck regulators. The
recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper
tolerances over voltage and temperature. The minimum recommended value for the input capacitor is 10 µF with
an ESR of 10 mΩ or less. The input capacitors need to be mounted as close as possible to the power/ground
input pins of the device.
The input power source supplies the average current continuously. During the PFET switch on-time, however,
the demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by
the input capacitor.
A simplified “worst case” assumption is that all of the PFET current is supplied by the input capacitor. This will
result in conservative estimates of input ripple voltage and capacitor RMS current.
Input ripple voltage is estimated as follows:
VPPIN =
IOUT x D
+ IOUT x ESRCIN
CIN x FS
where
•
•
•
•
VPPIN: estimated peak-to-peak input ripple voltage,
IOUT: Output Current
CIN: Input capacitor value
ESRCIN: input capacitor ESR.
(8)
This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate
RMS current rating. Capacitor RMS current estimated as follows:
©
•
I2RIPPLE
12
§
©
IRMSCIN = D x §I2OUT +
IRMSCIN: estimated input capacitor RMS current.
(9)
9.2.2.4 Recommendations For Unused Functions And Pins
If any function is not used in the end application then the following recommendations for tying-off the associated
pins on the circuit boards should be used.
FUNCTION
PIN
IF UNUSED
BUCK1
VIN_B1
Connect to VIN
SW_B1
Connect to VIN
FB_B1
Connect to GND
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FUNCTION
PIN
IF UNUSED
BUCK2
VIN_B2
Connect to VIN
BUCK3
SPI
SW_B2
Connect to VIN
FB_B2
Connect to GND
VIN_B3
Connect to VIN
SW_B3
Connect to VIN
FB_B3
Connect to GND
SPI_CS
Connect to VIN_IO
SPI_DI
Connect to GND
SPI_DO
Connect to GND
SPI_CK
Connect to GND
HL_B2
Connect to GND
HL_B3
Connect to VIN
STANDBY
Connect to GND
RESET
Connect to VIN_IO
COMPARATOR
VCOMP
Connect to VIN
IRQ
Leave open
100
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
9.2.3 Application Curves
70
60
50
60
50
40
40
30
30
20
VOUT = 1.8V
VOUT = 3.0V
20
1
VIN = 5 V
10
100
IOUT(mA)
1k
10k
VOUT = 3 V
1
VIN = 5 V
Figure 27. Efficiency Of Buck 1
34
70
10
100
IOUT(mA)
1000
VOUT = 1.8 V and 3 V
Figure 28. Efficiency Of Buck 2
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10 Power Supply Recommendations
The device is designed to operate from a fixed input voltage supply at 3.3 V or 5 V but will operate at input
voltages between 3 V to 5.5 V.
11 Layout
11.1 Layout Guidelines
11.1.1 PCB Layout Considerations
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
S
CIN
L
G
N
PGND
LOOP2
D
VIN
CONTROL
LOOP1
COUT
VOUT
P
D
SW VIN
G
S
LM10506
Schematic Of LM10506 Highlighting Layout Sensitive Nodes
1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched
rapidly. The first loop starts from the CIN input capacitor, to the regulator SWx_VIN pin, to the regulator SW
pin, to the inductor then out to the output capacitor COUT and load. The second loop starts from the output
capacitor ground, to the regulator SWx_GND pins, to the inductor and then out to COUT and the load (see
above). To minimize both loop areas the input capacitor should be placed as close as possible to the VIN
pin. Grounding for both the input and output capacitors should consist of a small localized top side plane that
connects to PGND. The inductor should be placed as close as possible to the SW pin and output capacitor.
2. Minimize the copper area of the switch node. The SW pins should be directly connected with a trace that
runs on top side directly to the inductor. To minimize IR losses this trace should be as short as possible and
with a sufficient width. However, a trace that is wider than 100 mils will increase the copper area and cause
too much capacitive loading on the SW pin. The inductors should be placed as close as possible to the SW
pins to further minimize the copper area of the switch node.
3. Have a single point ground for all device analog grounds. The ground connections for the feedback
components should be connected together then routed to the GND pin of the device. This prevents any
switched or load currents from flowing in the analog ground plane. If not properly handled, poor grounding
can result in degraded load regulation or erratic switching behavior.
4. Minimize trace length to the FB pin. The feedback trace should be routed away from the SW pin and inductor
to avoid contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure
feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide
the best output accuracy.
Outside 7x7 array 0.4 mm 34-bump DSBGA, with 24 peripheral and 6 inner vias = 30 individual signals
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Layout Guidelines (continued)
11.1.2 PCB Layout Thermal Dissipation For DSBGA Package
1. Position ground layer as close as possible to DSBGA package. Second PCB layer is usually good option.
LM10506 evaluation board is a good example.
2. Draw power traces as wide as possible. Bumps which carry high currents should be connected to wide
traces. This helps the silicon to cool down.
11.2 Layout Example
Figure 29. Possible PCB Layout Configuration
6x Through Hole Vias In The Middle
36
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Trademarks
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LM10506TME-A/NOPB
ACTIVE
DSBGA
YFR
34
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
V045
LM10506TME/NOPB
ACTIVE
DSBGA
YFR
34
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
V037
LM10506TMX-A/NOPB
ACTIVE
DSBGA
YFR
34
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
V045
LM10506TMX/NOPB
ACTIVE
DSBGA
YFR
34
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
V037
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM10506TME-A/NOPB
DSBGA
YFR
34
250
178.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.02
3.02
0.76
4.0
8.0
Q1
LM10506TME/NOPB
DSBGA
YFR
34
250
178.0
8.4
3.02
3.02
0.76
4.0
8.0
Q1
LM10506TMX-A/NOPB
DSBGA
YFR
34
3000
178.0
8.4
3.02
3.02
0.76
4.0
8.0
Q1
LM10506TMX/NOPB
DSBGA
YFR
34
3000
178.0
8.4
3.02
3.02
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM10506TME-A/NOPB
DSBGA
YFR
34
250
210.0
185.0
35.0
LM10506TME/NOPB
DSBGA
YFR
34
250
210.0
185.0
35.0
LM10506TMX-A/NOPB
DSBGA
YFR
34
3000
210.0
185.0
35.0
LM10506TMX/NOPB
DSBGA
YFR
34
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YFR0034xxx
D
0.600±0.075
E
TOP SIDE OF PACKAGE
BOTTOM SIDE OF PACKAGE
TME34XXX (Rev B)
D: Max = 2.84 mm, Min = 2.78 mm
E: Max = 2.84 mm, Min = 2.78 mm
4215092/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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12/12
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