NSC CLC114AJE Quad, low power video buffer Datasheet

CLC114
Quad, Low Power Video Buffer
General Description
The CLC114 is a high performance, close loop quad buffer
intended for power sensitive applications. Requiring only
30mW of quiescent power dissipation per channel ( ± 5V
supplies), the CLC114 offers a small signal bandwidth of
200MHz (0.5Vpp) and a slew rate of 450V/µs.
Designed specifically for high density crosspoint switch and
analog multiplexer applications, the CLC114 offers excellent
linearity and wide channel isolation (62dB @ 10MHz). Driving
a typical crosspoint switch load, the CLC114 offers differential gain and phase performance of 0.08% and 0.1% gain
flatness through 30MHz is typically 0.1dB.
With its patented closed loop topology , the CLC114 has
significant performance advantages over conventional open
loop designs. Applications requiring low output impedance
and true unity gain stability through very high frequencies
(active filters, dynamic load buffering, etc.) Will benefit from
the CLC114’s superior performance.
Constructed using an advanced, complementary bipolar process and National’s proven high speed architectures, the
CLC114 is available in several versions to meet a variety of
requirements.
Enhanced Solutions (Military/Aerospace)
SMD Number: 5962-92339
n
n
n
n
450V/us slew rate
Low power, 30mW per channel ( ± 5V sup.)
62dB channel isolation (10MHz)
Specified for crosspoint switch loads
Applications
n
n
n
n
n
n
Video crosspoint switch driver
Video distribution buffer
Video switching buffer
Video signaling multiplexing
Instrumentation amps
Active filters
Small Signal Pulse Response
*Space level versions also available.
*For more information, visit http://www.national/com/mil
Features
n Closed loop, quad buffer
n 200MHz small signal bandwidth
DS012738-10
Typical Application
DS012738-21
© 2001 National Semiconductor Corporation
DS012738
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CLC114 Quad, Low Power Video Buffer
February 2001
CLC114
Connection Diagram
DS012738-3
Pinout
Ordering Information
Package
Temperature Range
Industrial
Part Number
Package
Marking
NSC
Drawing
14-Pin Plastic DIP
−40˚C to +85˚C
CLC114AJP
CLC114AJP
N14A
14-Pin Plastic SOIC
−40˚C to +85˚C
CLC114AJE
CLC114AJE
M14A,B
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2
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
ESD Rating
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
± 7V
Supply Voltage (VCC)
IOUT
Output is short circuit protected to
ground, but maximum reliability will
be maintained if IOUT does not
exceed...
Input Voltage
Maximum Junction Temperature
−40˚C to +85˚C
−65˚C to +150˚C
+300˚C
500V
Operating Ratings
Thermal Resistance
Package
MDIP
SOIC
30mA
± VCC
+150˚C
(θJC)
65˚C/W
55˚C/W
(θJA)
115˚C/W
125˚C/W
Electrical Characteristics
(VCC = ± 5 V, RL = 100Ω; Unless Specified)
Symbol
Parameter
Ambient Temperature
Conditions
Typ
CLC114AI
Max/Min Ratings
(Note 2)
Units
+25˚C
−40˚C
+25˚C
+85˚
VOUT < 0.5VPP
200
95
> 135
> 70
> 120
> 70
MHz
VOUT < 2VPP
> 135
> 70
< 0.3
< 1.3
< 0.8
> 58
< 0.2
< 0.7
< 0.8
> 58
< 0.3
< 0.7
< 1.0
> 60
dB
< 2.8
<7
< 15
< 30
< 15
> 180
< 2.8
<7
< 15
< 30
< 10
> 200
< 3.0
<8
< 20
< 40
< 15
> 180
Frequency Domain Response
SSBW
-3dB Bandwidth
LSBW
Gain Flatness
GFPL
Peaking
DC to 30MHz
0.0
GFPH
Peaking
30MHz to 200MHz
0.0
GFR
Rolloff
DC to 60MHz
0.1
10MHz
62
0.5V Step
1.8
XT
Crosstalk (All Hostile)
MHz
VOUT < 0.5VPP
dB
dB
dB
Time Domain Response
TRS1
Rise and Fall Time
TRS2
TS1
TS01
Settling Time to 0.1%
to 0.01%
OS
Overshoot
SR
Slew Rate
2V Step
5
2V Step
10
2V Step
20
0.5V Step
3
450
ns
ns
ns
ns
%
V/µs
Distortion And Noise Response
HD2
2nd Harmonic Distortion
2VPP,20MHz
−50
3rd Harmonic Distortion
2VPP,20MHz
−58
< −34
< −50
< −38
< −50
< −38
< −45
dBc
HD3
> 1MHz
−155
< −153
< −153
< −153
dBm1Hz
0.97
> 0.95
< 1.0
< ± 8.2
< ± 40
< ± 10
< ± 62
> 48
< 17.0
> 0.96
< 0.6
< ± 5.0
V/V
> 48
< 16.5
> 0.96
< 0.5
< ± 8.0
< ± 30
< ±4
< ± 25
> 46
< 16.0
> 0.3
< 3.5
< 5.0
> ± 3.6
> 12
> 1.0
< 3.0
< 3.5
> ± 3.8
> 20
> 2.0
< 3.5
< 3.5
> ± 3.8
> 25
dBc
Equivalent Input Noise
SNF
Noise Floor
Static, DC Performance
GA
Small Signal Gain
100Ω Load
ILIN
Integral Endpoint Linearity
± 1V, Full Scale
VIO
Output Offset Voltage(Note 3)
DVIO
IBN
DIBN
Average Temperature Coefficient
Input Bias Current (Note 3)
Average Temperature Coefficient
PSRR
Power Supply Rejection Ratio
ICC
Supply Current, Total (Note 3)
0.4
± 0.5
± 9.0
± 1.0
± 6.0
56
No Load, Quiescent
12.0
–
< ±5
–
%
mV
µV/˚C
µA
nA/˚C
dB
mA
Miscellaneous Performance
RIN
Input Resistance
1.5
CIN
Input Capacitance
1.8
RO
Output Impedance
DC
VO
Output Voltage Range
No Load
IO
Output Current
2.5
± 4.0
25
3
MΩ
pF
Ω
V
mA
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CLC114
Absolute Maximum Ratings (Note 1)
CLC114
Electrical Characteristics
(Continued)
(VCC = ± 5 V, RL = 100Ω; Unless Specified)
Symbol
Parameter
Conditions
Typ
Max/Min Ratings
(Note 2)
Units
Performance Driving a Crosspoint Switch
Gain Flatness
VOUT < 2VPP
Gain Flatness
VOUT < 2VPP
DC to 5MHz
DC to 30MHZ
± 0.02
± 0.1
dB
dB
Differential Gain
3.58 & 4.43MHz
0.08
%
Differential Phase
3.58 & 4.43MHz
0.1
deg
5MHz,2V
2nd Harmonic Distortion
3rd Harmonic Distortion
Crosstalk (All Hostile)
−60
dBc
30MHz,2VPP
−43
dBc
5MHz,2VPP
−58
dBc
30MHz,2V
−43
dBc
PP
PP
5MHz
58
dB
10MHz
54
dB
30MHz
42
dB
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: AJ-level: spec. is 100% tested at +25˚C.
Test Load
DS012738-22
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CLC114
Typical Performance Characteristics
Gain and Phase vs. Load
Output Impedance
DS012738-4
DS012738-5
Input Impedance
PSRR
DS012738-6
Recommended RS vs. Load Capacitance
DS012738-7
| S21| vs. CL with Recommended RS
DS012738-9
DS012738-8
5
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CLC114
Typical Performance Characteristics
(Continued)
Small Signal Pulse Response
Large Signal Pulse Response
DS012738-10
DS012738-11
Short-Term Settling Time
Integral Linearity Error
DS012738-12
DS012738-13
Output Current vs. Temperature
Typical D.C. Errors vs. Temperature
DS012738-14
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DS012738-15
6
(Continued)
Equivalent Input Noise
2nd and 3rd Harmonic Distortion
DS012738-16
CLC114
Typical Performance Characteristics
DS012738-17
2-Tone, 3rd Order Intermodulation Intercept
DS012738-18
Application Division
to interface capacitance. For this reason it is recommended
that unused package pins (2, 4, 6, 11) be connected to the
ground plane for better channel isolation at the device pins.
Similarly, crosstalk can be improved by using a grounded
guard trace between signal traces. This will reduce the distributed capacitance between signal lines.
Following are two graphs depicting the effects of crosstalk.
All-hostile crosstalk is measured by driving three of the four
buffers simultaneously while observing the fourth, undriven,
channel. Figure 2, “All-hostile Crosstalk Isolation”, shows
this effect as a function of input signal frequency. RL is the
resistive load for each driven channel. Figure 3, “Most Susceptible Channel-to-Channel Pulse Coupling”, describes one
effect of crosstalk when one channel is driven with a 2VPP
step (tr = 5ns) while the output of the undriven channel is
measured. FromFigure 2 it can be observed that crosstalk
decreases as the signal frequency is reduced. Similarly, the
pulse coupling crosstalk will decrease as the rise time increases.
Evaluation Board
An evaluation board for the CLC114 is available. This board
maybe ordered as part CLC730023.
Operation
The CLC114 is a quad, low power, high speed, unity gain
buffer. The closed loop topology provides accuracy not found
in open loop designs. The input stage incorporates a slew
enhancement circuit which allows low quiescent power without sacrificing AC performance.
PC Board Layout and Crosstalk
High frequency devices demand a good printed circuit board
layout for optimum performance. The CLC114, with power
gain to 200 MHz, is no exception. A ground plane and power
supply bypassing with good high frequency ceramic capacitors in close proximity to the supply pins is essential. Second
harmonic distortion can be improved by ensuring equal current return paths for both the positive and negative supplies.
This can be accomplished by grounding the bypass capacitors at the same point in the ground plane while keeping the
power supply side of the bypass capacitors within 0.1” of the
CLC114 supply pins.
Crosstalk (undesired signal coupling between buffer channels) is strongly dependent on board layout. Closely spaced
signal traces on the circuit board will degrade crosstalk due
7
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CLC114
Application Division
Differential Gain and Phase
(Continued)
The CLC114 was designed to minimize deferential gain and
phase errors when driving the distributed capacitance of a
video cross point switch. Refer to the section “Performance
Driving a Crosspoint Switch” for typical values.
Unused Buffer
It is recommended that the inputs of any unused buffers be
tied to ground through 50Ω resistors.
DS012738-19
FIGURE 1. Recommended Circuit
DS012738-21
FIGURE 2. All- Hostile Crosstalk Isolation
DS012738-23
FIGURE 3. Most susceptible Channel-to-Channel Pulse Coupling
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CLC114
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Pin SOIC
NS Package Number M14A
14-Pin SOIC
NS Package Number M14B
9
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CLC114 Quad, Low Power Video Buffer
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Pin MDIP
NS Package Number N14A
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