ATMEL ATTINY461-ESSZ 8-bit microcontroller with 2/4/8k bytes in-system programmable flash Datasheet

Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
– 123 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash
(ATtiny261/461/861)
Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny261/461/861)
Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny261/461/861)
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
Peripheral Features
– 8/16-bit Timer/Counter with Prescaler
– 8/10-bit High Speed Timer/Counter with Separate Prescaler
3 High Frequency PWM Outputs with Separate Output Compare Registers
Programmable Dead Time Generator
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
11 Single Ended Channels
16 Differential ADC Channel Pairs
15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– 16 Programmable I/O Lines
– 20-pin SOIC, 32-pad MLF and 20-lead TSSOP
Operating Voltage:
– 2.7 - 5.5V for ATtiny261/461/861
Speed Grade:
– ATtiny261/461/861: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
– Operating temperature: Automotive (-40°C to +125°C)
Low Power Consumption
– Active Mode: 1 MHz, 2.7V: 380μA
– Power-down Mode: 0.1μA at 2.7V
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny261
ATtiny461
ATtiny861
Automotive
Preliminary
Summary
7753BS–AVR–08/08
1. Pin Configurations
Figure 1-1.
Pinout ATtiny261/461/861
SOIC / TSSOP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
AGND
AVCC
PA4 (ADC3/ICP0/PCINT4)
PA5 (ADC4/AIN2/PCINT5)
PA6 (ADC5/AIN0/PCINT6)
PA7 (ADC6/AIN1/PCINT7)
32
31
30
29
28
27
26
25
PB2 (SCK/USCK/SCL/OC1B/PCINT10)
PB1 (MISO/DO/OC1A/PCINT9)
PB0 (MOSI/DI/SDA/OC1A/PCINT8)
NC
NC
NC
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
(MOSI/DI/SDA/OC1A/PCINT8) PB0
(MISO/DO/OC1A/PCINT9) PB1
(SCK/USCK/SCL/OC1B/PCINT10) PB2
(OC1B/PCINT11) PB3
VCC
GND
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
1
2
3
4
5
6
7
8
QFN/MLF
24
23
22
21
20
19
18
17
NC
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
AGND
NC
NC
AVCC
PA4 (ADC3/ICP0/PCINT4)
NC
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
NC
(ADC6/AIN1/PCINT7) PA7
(ADC5/AIN0/PCINT6) PA6
(ADC4/AIN2/PCINT5) PA5
NC
9
10
11
12
13
14
15
16
NC
(OC1B/PCINT11) PB3
NC
VCC
GND
NC
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
Note:
2
The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical
stability.
ATtiny261/461/861
7753BS–AVR–08/08
ATtiny261/461/861
1.1
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers
manufactured on the same process technology. Min and Max values will be available after the device is characterized.
1.2
Automotive Quality Grade
The ATtiny261/461/861 have been developed and manufactured according to the most stringent
requirements of the international standard ISO-TS 16949. This data sheet contains limit values
extracted from the results of extensive characterization (Temperature and Voltage). The quality
and reliability of the ATtiny261/461/861 have been verified during regular product qualification
as per AEC-Q100 grade 1.
As indicated in the ordering information paragraph, the product is available in only one temper
ture grade, Table 1-2.
Table 1-1.
Temperature Grade Identification for Automotive Products
Temperature
-40; +125
Temperature
Identifier
Z
Comments
Full Automotive Temperature Range
3
7753BS–AVR–08/08
2. Overview
The ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Block Diagram
Block Diagram
GND
Figure 2-1.
VCC
2.1
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
Power
Supervision
POR / BOD &
RESET
debugWIRE
Flash
SRAM
PROGRAM
LOGIC
CPU
EEPROM
AVCC
AGND
AREF
Timer/Counter1
USI
Analog Comp.
A/D Conv.
DATABUS
Timer/Counter0
Internal
Bandgap
3
PORT B (8)
11
PORT A (8)
RESET
XTAL[1..2]
PB[0..7]
4
PA[0..7]
ATtiny261/461/861
7753BS–AVR–08/08
ATtiny261/461/861
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny261/461/861 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
5
7753BS–AVR–08/08
3. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
1
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
Relative Jump
PC ← PC + k + 1
None
2
Indirect Jump to (Z)
PC ← Z
None
2
Relative Subroutine Call
PC ← PC + k + 1
None
3
ICALL
Indirect Call to (Z)
PC ← Z
None
3
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
4
BRANCH INSTRUCTIONS
RJMP
k
IJMP
RCALL
k
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1/2/3
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
1
1
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
6
ATtiny261/461/861
7753BS–AVR–08/08
ATtiny261/461/861
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
None
1
None
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
LDI
Rd, K
Load Immediate
Rd ← K
None
1
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
2
2
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program Memory
(z) ← R1:R0
None
SPM
IN
Rd, P
In Port
Rd ← P
None
OUT
P, Rr
Out Port
P ← Rr
None
1
1
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/Timer)
For On-chip Debug Only
None
None
1
N/A
7
7753BS–AVR–08/08
4. Ordering Information
Table 4-1.
Ordering Code(2)
Speed (MHz)(3)
Power Supply (V)
Package(1)
Operation Range
ATtiny261-ESSZ
16
2.7 - 5.5
TG
Automotive (-40° to +125°C)
ATtiny261-ESMZ
16
2.7 - 5.5
PN
Automotive (-40° to +125°C)
ATtiny261-ESXZ
16
2.7 - 5.5
6G
Automotive (-40° to +125°C)
ATtiny461-ESSZ
16
2.7 - 5.5
TG
Automotive (-40° to +125°C)
ATtiny461-ESMZ
16
2.7 - 5.5
PN
Automotive (-40° to +125°C)
ATtiny461-ESXZ
16
2.7 - 5.5
6G
Automotive (-40° to +125°C)
ATtiny861-ESSZ
16
2.7 - 5.5
TG
Automotive (-40° to +125°C)
ATtiny861-ESMZ
16
2.7 - 5.5
PN
Automotive (-40° to +125°C)
ATtiny861-ESXZ
16
2.7 - 5.5
6G
Automotive (-40° to +125°C)
Table 4-2.
Available Product Offering
Ordering Code(2)
Speed (MHz)(3)
Power Supply (V)
Package(1)
Operation Range
ATtiny261-15SZ
16
2.7 - 5.5
TG
Automotive (-40° to +125°C)
ATtiny261-15MZ
16
2.7 - 5.5
PN
Automotive (-40° to +125°C)
ATtiny261-15XZ
16
2.7 - 5.5
6G
Automotive (-40° to +125°C)
ATtiny461-15SZ
16
2.7 - 5.5
TG
Automotive (-40° to +125°C)
ATtiny461-15MZ
16
2.7 - 5.5
PN
Automotive (-40° to +125°C)
ATtiny461-15XZ
16
2.7 - 5.5
6G
Automotive (-40° to +125°C)
ATtiny861-15SZ
16
2.7 - 5.5
TG
Automotive (-40° to +125°C)
ATtiny861-15MZ
16
2.7 - 5.5
PN
Automotive (-40° to +125°C)
ATtiny861-15XZ
16
2.7 - 5.5
6G
Automotive (-40° to +125°C)
Notes:
8
Engineering Samples Delivery only
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 189
ATtiny261/461/861
7753BS–AVR–08/08
ATtiny261/461/861
Package Type
PN
32-pad, 5.0 x 5.0 mm Body, Lead Pitch 0.50 mm, Quad Flat No Lead Package (QFN)
TG
20-lead, 0.300" Wide Body Lead, Plastic Gull Wing Small Outline Package (SOIC)
6G
20-leads, 4.4x6.5mm body - 0.65mm Pitch - Lead Length: 0.6mm
Thin Shrink Small Outline Package (TSSOP)
9
7753BS–AVR–08/08
5. Packaging Information
5.1
10
PN
ATtiny261/461/861
7753BS–AVR–08/08
ATtiny261/461/861
5.2
TG
11
7753BS–AVR–08/08
12
ATtiny261/461/861
7753BS–AVR–08/08
ATtiny261/461/861
5.3
6G
13
7753BS–AVR–08/08
6. Errata
6.1
Errata ATtiny261
The revision letter in this section refers to the revision of the ATtiny261 device.
6.1.1
Rev A
No known errata.
6.2
Errata ATtiny461
The revision letter in this section refers to the revision of the ATtiny461 device.
6.2.1
Rev B
No known errata.
6.3
Errata ATtiny861
The revision letter in this section refers to the revision of the ATtiny861 device.
6.3.1
Rev B
No known errata.
14
ATtiny261/461/861
7753BS–AVR–08/08
ATtiny261/461/861
7. Datasheet Revision History
7.1
Rev. 7753A – 11/07
1.
7.2
First Datasheet Draft - Initial Automotive Version. Started from Industrial Datasheet
doc2588 rev.B - 01/07
Rev. 7753B – 08/08
1.
Added 6G product offering to Ordering Information.
15
7753BS–AVR–08/08
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7753BS–AVR–08/08
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