PHILIPS HEF4527BN Bcd rate multiplier Datasheet

INTEGRATED CIRCUITS
DATA SHEET
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HEF4527B
MSI
BCD rate multiplier
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
A HIGH on CL resets the counter, independent of all other
input conditions and a rate of 10 pulses is available at O1
and O1 when SD is HIGH. When CE is HIGH, the counter
is disabled, the state of the outputs (O1, O1) depend on the
content of the counter.
DESCRIPTION
The HEF4527B is a BCD rate multiplier with two buffered
rate outputs (O1 and O1), two buffered terminal count
outputs (TC and TC), four BCD rate select inputs (SA, SB,
SC, SD), a common clock input (CP), a preset input (PL),
an overriding asynchronous clear input (CL), a strobe input
(STR), a cascade input (CAS) and an active LOW count
enable input (CE).
A HIGH on PL sets the counter in the ‘9’ state and TC
becomes HIGH.
A HIGH on STR inhibits the outputs O1 and O1. A HIGH on
CAS forces the output O1 to HIGH, while the state of
O1 depends on the inputs SA to SD (see lines 1 to 16 of
function table).
The BCD rate multiplier provides an output pulse rate
based upon the BCD input number. For example, if 6 is the
BCD number, there will be six output pulses for every ten
clock input pulses. The output is clocked on the
negative-going transition of the clock.
This device may be used to perform arithmetic operations.
For the add mode and multiply mode see Figs 5 and 6.
When CE, STR, CAS, CL and PL are LOW, the rate pulses
are available at the outputs O1 and O1, the terminal count
pulses at TC and TC.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
HEF4527BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4527BD(F):
16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4527BT(D):
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
CP
clock input
PL
preset to ‘9’ input
CL
counter clear input
CE
count enable input (active LOW)
STR
strobe input
CAS
cascade input
SA to SD
rate select inputs
O1 to O1
rate outputs
TC
terminal count output (active HIGH)
TC
terminal count output (active LOW)
January 1995
3
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Philips Semiconductors
BCD rate multiplier
January 1995
4
Product specification
HEF4527B
MSI
Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
FUNCTION TABLE
INPUTS
OUTPUTS
NUMBER OF PULSES OR LOGIC LEVEL
NUMBER OF PULSES
OR LOGIC LEVEL
SD
SC
SB
L
L
L
L
L
CE STR CAS
CL
PL
O1
O1
TC
TC
L
L
L
L
H
1
1
L
L
L
1
1
1
1
L
L
L
2
2
1
1
MODE OF OPERATION
SA
CP
L
L
10
L
L
L
H
10
L
L
L
H
L
10
L
L
L
L
H
H
10
L
L
L
L
L
3
3
1
1
L
H
L
L
10
L
L
L
L
L
4
4
1
1
L
H
L
H
10
L
L
L
L
L
5
5
1
1
L
H
H
L
10
L
L
L
L
L
6
6
1
1
L
H
H
H
10
L
L
L
L
L
7
7
1
1
H
L
L
L
10
L
L
L
L
L
8
8
1
1
H
L
L
H
10
L
L
L
L
L
9
9
1
1
H
L
H
L
10
L
L
L
L
L
8
8
1
1
H
L
H
H
10
L
L
L
L
L
9
9
1
1
H
H
L
L
10
L
L
L
L
L
8
8
1
1
H
H
L
H
10
L
L
L
L
L
9
9
1
1
H
H
H
L
10
L
L
L
L
L
8
8
1
1
H
H
H
H
10
L
L
L
L
L
9
9
1
1
(5)
CE = H; counter disabled
rate pulses at the outputs
depend on the BCD input
number at SA to SD
X
X
X
X
X
H
L
L
L
L
(5)
H
(5)
X
X
X
X
10
L
H
L
L
L
L
H
1
1
outputs O1 and O2 disabled
X
X
X
X
10
L
L
H
L
L
H
(4)
1
1
output O1 disabled
H
X
X
X
10
L
L
L
H
X
10
10
H
L
CL = H
L
X
X
X
X
L
L
L
H
X
L
H
H
L
counter reset
X
X
X
X
X
L
L
L
L
H
L
H
L
H
PL = H; preset to ‘9’
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4. Same output as the first 16 lines of this function table (depends on the values of SA to SD).
5. Depends on internal state of the counter.
January 1995
5
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns.
PARAMETER
VDD
V
SYMBOL
MIN.
TYP.
MAX.
UNIT
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP → O1, O1
HIGH to LOW
130
260 ns
103 ns + (0,55 ns/pF) CL
50
100 ns
39 ns + (0,23 ns/pF) CL
35
70 ns
27 ns + (0,16 ns/pF) CL
130
260 ns
103 ns + (0,55 ns/pF) CL
50
100 ns
39 ns + (0,23 ns/pF) CL
35
70 ns
27 ns + (0,16 ns/pF) CL
175
350 ns
148 ns + (0,55 ns/pF) CL
65
130 ns
54 ns + (0,23 ns/pF) CL
45
90 ns
37 ns + (0,16 ns/pF) CL
160
320 ns
133 ns + (0,55 ns/pF) CL
65
130 ns
54 ns + (0,23 ns/pF) CL
45
90 ns
37 ns + (0,16 ns/pF) CL
175
350 ns
148 ns + (0,55 ns/pF) CL
65
130 ns
54 ns + (0,23 ns/pF) CL
15
50
100 ns
42 ns + (0,16 ns/pF) CL
5
150
300 ns
123 ns + (0,55 ns/pF) CL
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
CP → TC
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
CP → TC
HIGH to LOW
LOW to HIGH
CAS → O1
HIGH to LOW
LOW to HIGH
STR → O1, O1
HIGH to LOW
LOW to HIGH
CE →TC
HIGH to LOW
LOW to HIGH
5
10
tPHL
60
120 ns
49 ns + (0,23 ns/pF) CL
15
45
90 ns
37 ns + (0,16 ns/pF) CL
5
90
180 ns
63 ns + (0,55 ns/pF) CL
10
tPLH
35
70 ns
24 ns + (0,23 ns/pF) CL
15
25
50 ns
17 ns + (0,16 ns/pF) CL
5
70
140 ns
43 ns + (0,55 ns/pF) CL
10
tPHL
30
60 ns
19 ns + (0,23 ns/pF) CL
15
25
50 ns
17 ns + (0,16 ns/pF) CL
5
100
200 ns
73 ns + (0,55 ns/pF) CL
10
tPLH
40
80 ns
29 ns + (0,23 ns/pF) CL
15
30
60 ns
22 ns + (0,16 ns/pF) CL
5
85
170 ns
58 ns + (0,55 ns/pF) CL
10
tPHL
35
70 ns
24 ns + (0,23 ns/pF) CL
15
25
50 ns
17 ns + (0,16 ns/pF) CL
5
95
190 ns
68 ns + (0,55 ns/pF) CL
35
70 ns
24 ns + (0,23 ns/pF) CL
10
10
tPLH
tPHL
15
25
50 ns
17 ns + (0,16 ns/pF) CL
5
65
130 ns
38 ns + (0,55 ns/pF) CL
30
60 ns
19 ns + (0,23 ns/pF) CL
20
40 ns
12 ns + (0,16 ns/pF) CL
10
tPLH
15
January 1995
6
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
PARAMETER
CL → O1
HIGH to LOW
CL → O1
LOW to HIGH
VDD
V
SYMBOL
MIN.
5
TYP.
MAX.
UNIT
TYPICAL EXTRAPOLATION
FORMULA
145
290 ns
118 ns + (0,55 ns/pF) CL
55
110 ns
44 ns + (0,23 ns/pF) CL
15
40
80 ns
32 ns + (0,16 ns/pF) CL
5
145
290 ns
118 ns + (0,55 ns/pF) CL
10
tPHL
55
110 ns
44 ns + (0,23 ns/pF) CL
15
40
80 ns
32 ns + (0,16 ns/pF) CL
5
260
520 ns
233 ns + (0,55 ns/pF) CL
10
tPLH
Propagation delays
PL → O1, O1
HIGH to LOW
100
200 ns
89 ns + (0,23 ns/pF) CL
15
70
140 ns
62 ns + (0,16 ns/pF) CL
5
235
470 ns
208 ns + (0,55 ns/pF) CL
10
tPHL
90
180 ns
79 ns + (0,23 ns/pF) CL
15
50
100 ns
42 ns + (0,16 ns/pF) CL
Minimum clock
5
45
90 ns
pulse width
10
18
36 ns
HIGH
15
12
24 ns
5
20
40 ns
LOW to HIGH
Minimum CL
pulse width; HIGH
Minimum PL
pulse width; HIGH
10
10
tPLH
tWCPH
tWCLH
12
24 ns
15
10
20 ns
5
50
100 ns
20
40 ns
15
30 ns
30
15
ns
20
10
ns
10
tWPLH
15
Set-up times
5
CE → CP
10
Recovery times
CL → CP
PL → CP
tsu
15
12
5
ns
5
20
10
ns
16
8
ns
10
tRCL
15
10
5
ns
5
80
40
ns
36
18
ns
25
10
10
tRPL
15
Maximum clock
pulse frequency
5
10
15
January 1995
4,5
fmax
ns
9
MHz
11
22
MHz
16
32
MHz
7
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1 050 fi + ∑ (foCL) × VDD2
where
dissipation per
10
4 500 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
package (P)
15
10 500 fi + ∑ (foCL) × VDD2
Dynamic power
2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
8
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
Fig.4 Timing diagram.
January 1995
9
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
APPLICATION INFORMATION
Add mode
Output rate = 10n (0,1 BCD1 + 0,01 BCD2 + 0,01 BCD3 + ........), in where n = number of cascaded RMs.
Example: RM1 preset to 9 and RM2 preset to 4, output rate is 102 (0,1 × 9 + 0,01 × 4) = 94.
Fig.5 Two HEF4527B cascaded in the add mode.
Multiply mode
Output rate = 10n (0,1 BCD1 × 0,1 BCD2 × 0,1 BCD3 × ........), in where n = number of cascaded RMs.
Example: RM1 preset to 9 and RM2 preset to 4, output rate is 102 (0,1 × 9 × 0,1 × 4) = 36.
Fig.6 Two HEF4527B cascaded in the multiply mode.
January 1995
10
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