Dallas DS1643-100 Nonvolatile timekeeping ram Datasheet

DS1643
DS1643
Nonvolatile Timekeeping RAM
FEATURES
PIN ASSIGNMENT
• Form, fit, and function compatible with the MK48T08
Timekeeping RAM
• Integrated NV SRAM, real time clock, crystal, power–
fail control circuit and lithium energy source
• Standard JEDEC bytewide 8K x 8 static RAM pinout
• Clock
registers are accessed identical to the static
RAM. These registers are resident in the eight top
RAM locations.
• Totally nonvolatile with over 10 years of operation in
the absence of power
• Access times of 120 ns and 150 ns
• Quartz accuracy ±1 minute a month @ 25°C, factory
calibrated
• BCD coded year, month, date, day, hours, minutes,
and seconds with leap year compensation valid up to
2100
NC
1
28
A12
2
27
VCC
WE
A7
3
26
CE2
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CE
A0
10
19
DQ7
DQ0
11
18
DQ6
DQ1
12
17
DQ5
DQ2
13
16
DQ4
GND
14
15
DQ3
28–PIN ENCAPSULATED PACKAGE
(700 MIL EXTENDED)
• Power–fail
write protection allows for ±10% VCC
power supply tolerance
ORDERING INFORMATION
DS1643–XXX
28–pin DIP module
–120 120 ns access
–150 150 ns access
DESCRIPTION
The DS1643 is an 8K x 8 nonvolatile static RAM with a
full function real time clock which are both accessible in
a bytewide format. The nonvolatile time keeping RAM is
pin and function equivalent to any JEDEC standard
8K x 8 SRAM. The device can also be easily substituted
in ROM, EPROM and EEPROM sockets providing read/
write nonvolatility and the addition of the real time clock
function. The real time clock information resides in the
eight uppermost RAM locations. The RTC registers
contain year, month, date, day, hours, minutes, and seconds data in 24 hour BCD format. Corrections for the
day of the month and leap year are made automatically.
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
The RTC clock registers are double buffered to avoid
access of incorrect data that can occur during clock update cycles. The double buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1643
also contains its own power–fail circuitry which deselects the device when the VCC supply is in an out of tolerance condition. This feature prevents loss of data from
unpredictable system operation brought on by low VCC
as errant access and update cycles are avoided.
041697 1/11
DS1643
PIN DESCRIPTION
A0–A12
CE
OE
WE
NC
VCC
GND
DQ0-DQ7
–
–
–
–
–
–
–
–
Address Input
Chip Enable
Output Enable
Write Enable
No Connection
+5 Volts
Ground
Data Input/Output
CLOCK OPERATIONS–READING THE
CLOCK
While the double buffered register structure reduces the
chance of reading incorrect data, internal updates to the
DS1643 clock registers should be halted before clock
data is read to prevent reading of data in transition.
However, halting the internal clock register updating
process does not affect clock accuracy. Updating is
halted when a one is written into the read bit, the seventh
most significant bit in the control register. As long as a
one remains in that position, updating is halted. After a
halt is issued, the registers reflect the count, that is day,
date, and time that was current at the moment the halt
command was issued. However, the internal clock registers of the double buffered system continue to update
so that the clock accuracy is not affected by the access
of data. All of the DS1643 registers are updated simultaneously after the clock status is reset. Updating is
within a second after the read bit is written to zero.
DS1643 BLOCK DIAGRAM Figure 1
CLOCK
REGISTERS
OSCILLATOR AND
CLOCK COUNTDOWN
CHAIN
32.768 KHz
CE
WE
8K X 8 NV SRAM
OE
+
VBAT
POWER MONITOR,
SWITCHING, AND
WRITE PROTECTION
A0–A12
DQ0–DQ7
VCC
041697 2/11
POWER GOOD
DS1643
DS1643 TRUTH TABLE Table 1
VCC
CE
CE2
OE
WE
MODE
DQ
POWER
VIH
X
X
X
DESELECT
HIGH Z
STANDBY
X
VIL
X
X
DESELECT
HIGH Z
STANDBY
VIL
VIH
X
VIL
WRITE
DATA IN
ACTIVE
VIL
VIH
VIL
VIH
READ
DATA OUT
ACTIVE
VIL
VIH
VIH
VIH
READ
HIGH Z
ACTIVE
<4.5 VOLTS
>VBAT
X
X
X
X
DESELECT
HIGH Z
CMOS STANDBY
<VBAT
X
X
X
X
DESELECT
HIGH Z
DATA RETENTION
MODE
5 VOLTS ± 10%
SETTING THE CLOCK
The 8–bit of the control register is the write bit. Setting
the write bit to a one, like the read bit, halts updates to
the DS1643 registers. The user can then load them with
the correct day, date and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers
those values to the actual clock counters and allows
normal operation to resume.
STOPPING AND STARTING THE CLOCK
OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to
minimize current drain from the battery. The OSC bit is
the MSB for the seconds registers. Setting it to a 1 stops
the oscillator.
FREQUENCY TEST BIT
Bit 6 of the day byte is the frequency test bit. When the
frequency test bit is set to logic “1” and the oscillator is
running, the LSB of the seconds register will toggle at
512 Hz. When the seconds register is being read, the
DQ0 line will toggle at the 512 Hz frequency as long as
conditions for access remain valid (i.e., CE low, OE low,
CE2 high, and address for seconds register remain valid
and stable).
CLOCK ACCURACY
The DS1643 is guaranteed to keep time accuracy to
within ±1 minute per month at 25°C. The clock is calibrated at the factory by Dallas Semiconductor using
special calibration nonvolatile tuning elements. The
DS1643 does not require additional calibration and temperature deviations will have a negligible effect in most
applications. For this reason, methods of field clock calibration are not available and not necessary. Attempts
to calibrate the clock that may be used with similar device types (MK48T08 family) will not have any effect
even though the DS1643 appears to accept calibration
data.
041697 3/11
DS1643
DS1643 REGISTER MAP – BANK1 Table 2
DATA
ADDRESS
FUNCTION
B7
B6
B5
B4
B3
B2
B1
B0
1FFF
–
–
–
–
–
–
–
–
YEAR
00–99
1FFE
X
X
X
–
–
–
–
–
MONTH
01–12
1FFD
X
X
–
–
–
–
–
–
DATE
01–31
1FFC
X
FT
X
X
X
–
–
–
DAY
01–07
1FFB
X
X
–
–
–
–
–
–
HOUR
00–23
1FFA
X
–
–
–
–
–
–
–
MINUTES
00–59
1FF9
OSC
–
–
–
–
–
–
–
SECONDS
00–59
1FF8
W
R
X
X
X
X
X
X
CONTROL
A
OSC = STOP BIT
W
= WRITE BIT
R
X
=
=
READ BIT
UNUSED
FT =
FREQUENCY TEST
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write
enable) is high and CE (chip enable) is low. The device
architecture allows ripple-through access to any of the
address locations in the NV SRAM. Valid data will be
available at the DQ pins within tAA after the last address
input is stable, providing that the CE and OE access
times and states are satisfied. If CE or OE access times
are not met, valid data will be available at the latter of
chip enable access (tCEA) or at output enable access
time (tOEA). The state of the data input/output pins (DQ)
is controlled by CE and OE. If the outputs are activated
before tAA, the data lines are driven to an intermediate
state until tAA. If the address inputs are changed while
CE and OE remain valid, output data will remain valid for
output data hold time (tOH) but will then go indeterminate
until the next address access.
The DS1643 is in the write mode whenever WE and CE
are in their active state. The start of a write is referenced
to the latter occurring transition of WE or CE. The addresses must be held valid throughout the cycle. CE or
WE must return inactive for a minimum of tWR prior to
the initiation of another read or write cycle. Data in must
be valid tDS prior to the end of write and remain valid for
tDH afterward. In a typical application, the OE signal will
be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus
contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by
the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active.
041697 4/11
DS1643
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5 volts) the
DS1643 can be accessed as described above by read
or write cycles. However, when VCC is below the power–fail point VPF (point at which write protection occurs)
the internal clock registers and RAM is blocked from access. This is accomplished internally by inhibiting access via the CE and CE2 signals. When VCC falls below
the level of the internal battery supply, power input is
switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from
the battery until VCC is returned to nominal level.
INTERNAL BATTERY LONGEVITY
The DS1643 has a self contained lithium power source
that is designed to provide energy for clock activity, and
clock and RAM data retention when the VCC supply is
not present. The capability of this internal power supply
is sufficient to power the DS1643 continuously for the
life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25°C
with the internal clock oscillator running in the absence
of VCC power. The DS1643 is shipped from Dallas
Semiconductor with the clock oscillator turned off, so
the expected life should be considered to start from the
time the clock oscillator is first turned on. Actual life expectancy of the DS1643 will be much longer than 10
years since no internal lithium battery energy is consumed when VCC is present. In fact, in most applications, the life expectancy of the DS1643 will be approximately equal to the shelf life (expected useful life of the
lithium battery with no load attached) of the lithium battery which may prove to be as long as 20 years.
041697 5/11
DS1643
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.3V to +7.0V
0°C to 70°C
–20°C to +70°C
260°C for 10 seconds (See Note 7)
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
(0°C to 70°C)
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
VCC
4.5
5.0
5.5
V
1
Logic 1 Voltage All Inputs
VIH
2.2
VCC+0.3
V
Logic 0 Voltage All Inputs
VIL
–0.3
0.8
V
(0°C ≤ tA ≤ 70°C; VCC = 5.0V ± 10%)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Average VCC Power Supply
Current
ICC1
TTL Standby Current (CE = VIH,
CE2 = VIL)
ICC2
CMOS Standby Current
(CE=VCC–0.2V, CE2=GND+0.2V)
ICC3
Input Leakage Current (any input)
IIL
MIN
MAX
UNITS
NOTES
65
mA
2, 3
3
6
mA
2, 3
2
4.0
mA
2, 3
–1
Output Leakage Current
IOL
–1
Output Logic 1 Voltage
(IOUT = –1.0 mA)
VOH
2.4
Output Logic 0 Voltage
(IOUT = +2.1 mA)
VOL
Write Protection Voltage
VTP
041697 6/11
TYP
4.0
+1
µA
+1
µA
V
4.25
0.4
V
4.5
V
DS1643
(0°C to 70°C; VCC = 5.0V ± 10%)
AC ELECTRICAL CHARACTERISTICS
DS1643–120
DS1643–150
SYMBOL
MIN
Read Cycle Time
tRC
120
Address Access Time
tAA
120
150
ns
CE and CE2 Access Time
tCEA
120
150
ns
CE and CE2 Data Off Time
tCEZ
40
50
ns
Output Enable Access Time
tOEA
100
120
ns
Output Enable Data Off Time
tOEZ
35
45
ns
Output Enable to DQ Low–Z
tOEL
5
5
ns
CE and CE2 to DQ Low–Z
tCEL
5
5
ns
PARAMETER
MAX
MIN
MAX
150
UNITS
NOTES
ns
Output Hold from Address
tOH
5
5
ns
Write Cycle Time
tWC
120
150
ns
Address Setup Time
tAS
0
0
ns
CE and CE2 Pulse Width
tCEW
100
120
ns
Address Hold from End of Write
tAH1
tAH2
5
30
5
30
ns
ns
Write Pulse Width
tWEW
120
150
ns
WE Data Off Time
tWEZ
WE or CE Inactive Time
tWR
10
10
ns
Data Setup Time
tDS
85
110
ns
Data Hold Time High
tDH1
tDH2
0
15
0
15
ns
ns
40
50
5
6
ns
5
6
AC TEST CONDITIONS
Input Levels:
Transition Times:
0V to 3V
5 ns
CAPACITANCE
PARAMETER
(tA = 25°C)
SYMBOL
MIN
TYP
MAX
UNITS
Capacitance on all pins
(except DQ)
CI
7
pF
Capacitance on DQ pins
CDQ
10
pF
NOTES
041697 7/11
DS1643
(0°C to 70°C)
AC ELECTRICAL CHARACTERISTICS (POWER–UP/DOWN TIMING)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
tPD
0
µs
VPF (Max) to VPF (Min)
VCC Fall Time
tF
300
µs
VPF (Min) to VSO
VCC Fall Time
tFB
10
µs
VSO to VPF (Min)
VCC Rise Time
tRB
1
µs
VPF (Min) to VPF (Max)
VCC Rise Time
tR
0
µs
Power–Up
tREC
15
Expected Data Retention Time
(Oscillator On)
tDR
10
CE2, CE or WE at VIH before
Power Down
25
35
NOTES
ms
years
4
DS1643 READ CYCLE TIMING
READ
READ
tRC
tRC
WRITE
tWC
A0–A12
tAA
tAH
tAS
tCEA
CE
tCEL
OE
tOEA
tWR
tWEW
WE
tOEL
tOH
tOEZ
DQ0–DQ7
VALID OUT
041697 8/11
VALID OUT
VALID IN
DS1643
DS1643 WRITE CYCLE TIMING
WRITE
WRITE
tWC
tWC
READ
tRC
A0–A12
tAH2
tAS
tAA
tWR
tAH1
tCEW
CE
tOEA
OE
tWR
tWEW
WE
tDH1
tCEZ
DQ0–
DQ7
tDH2
tDS
VALID
OUT
VALID IN
tWEZ
tDS
VALID IN
VALID OUT
POWER–DOWN/POWER–UP TIMING
VCC
VPF (MAX)
VPF (MIN)
VPF
tF
tR
tFB
VSO
VSO
tPD
tRB
tREC
CE
IBATT
DATA RETENTION
tDR
041697 9/11
DS1643
NOTES:
1. All voltages are referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Data retention time is at 25°C and is calculated from the date code on the device package. The date code XXYY
is the year followed by the week of the year in which the device was manufactured. For example, 9225, would
mean the 25th week of 1992.
5. tAH1, tDH1 are measured from WE going high.
6. tAH2, tDH2 are measured from CE going high.
7. Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as
long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post solder
cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.
OUTPUT LOAD
+5 VOLTS
1.8KΩ
D.U.T.
1KΩ
100 pF
041697 10/11
DS1643
DS1643 28–PIN PACKAGE
PKG
1
A
C
F
D
K
G
28–PIN
DIM
MIN
MAX
A IN.
MM
1.470
37.34
1.490
37.85
B IN.
MM
0.675
17.75
0.740
18.80
C IN.
MM
0.335
8.51
0.355
9.02
D IN.
MM
0.075
1.91
0.105
2.67
E IN.
MM
0.015
0.38
0.030
0.76
F
IN.
MM
0.140
3.56
0.180
4.57
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
0.590
14.99
0.630
16.00
J
IN.
MM
0.010
0.25
0.018
0.45
K IN.
MM
0.015
0.43
0.025
0.58
J
E
H
B
041697 11/11