381B CY7C1381B CY7C1383B 512 × 36/1M × 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10.0 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion 3.3V (–5% / +10%) power supply Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) • Automatic power down available using ZZ mode or CE deselect • High-density, high-speed packages • JTAG boundary scan for BGA packaging version Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors. The CY7C1381B and CY7C1383B SRAMs integrate 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and BWe), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). Address, data inputs, and Write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the Write control inputs. Individual byte Write allows individual byte to be written. BWa controls DQ1-DQ8 and DP1. BWb controls DQ9-DQ16 and DP2. BWc controls DQ17-DQ24and DP3. BWd controls DQ25-DQ32 and DP4. BWa, BWb BWc, and BWd can be active only with BWe being LOW. GW being LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the immediately next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. All inputs and outputs of the CY7C1381B and the CY7C1383B are JEDEC-standard JESD8-5-compatible. Selection Guide 117 MHz 100 MHz 83 MHz Unit Maximum Access Time 7.5 8.5 10.0 ns Maximum Operating Current 250 225 185 mA Maximum CMOS Standby Current 20 20 20 mA Cypress Semiconductor Corporation Document #: 38-05196 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 3, 2001 CY7C1381B CY7C1383B Functional Block Diagram Logic Block Diagram ×18 MODE (A0,A1) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[19:0] GW Q 20 18 ADDRESS CE REGISTER D 18 20 1M × 18 MEMORY ARRAY D DQb[15:8],DP1Q BYTEWRITE REGISTERS BWE BWS b D DQa[7:0],DP0 Q BYTEWRITE REGISTERS BWS a 18 CE1 CE2 CE3 18 D ENABLE Q CE REGISTER CLK INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQ[15:0] DP[1:0] Logic Block Diagram ×36 MODE (A0,A1) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[18:0] GW Q 19 BWE BWS d 17 ADDRESS CE REGISTER D Q D DQd[31:24],DP3 BYTEWRITE REGISTERS BWS c D DQc[23:16],DP2Q BYTEWRITE REGISTERS BWS b D DQb[15:8],DP1Q BYTEWRITE REGISTERS BWSa CE1 CE2 CE3 D DQa[7:0],DP0Q BYTEWRITE REGISTERS 17 19 512K × 36 MEMORY ARRAY 36 36 D ENABLE Q CE REGISTER CLK INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQ[31:0] DP[3:0] Document #: 38-05196 Rev. ** Page 2 of 31 CY7C1381B CY7C1383B Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP NC NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DPb NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1383B (1M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DPb DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa DPa MODE A A A A A1 A0 NC NC VSS VDD A A A A A A A A A CY7C1381B (512K × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC NC VSS VDD A A A A A A A A A DPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DPd Document #: 38-05196 Rev. ** A NC NC VDDQ VSSQ NC DPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC Page 3 of 31 CY7C1381B CY7C1383B Pin Configurations (continued) 119-ball BGA CY7C1381B (512K × 36) 1 2 A VDDQ A 3 A B NC A A C NC A A D DQc DQPc E DQc DQc 4 5 A 6 A 7 VDDQ ADSC VDD A A NC A A NC VSS NC VSS DQPb DQb VSS CE1 VSS DQb DQb ADSP F VDDQ DQc VSS OE VSS DQb VDDQ G H J DQc DQc VDDQ DQc DQc VDD BWc VSS NC ADV BWb VSS NC DQb DQb VDD DQb DQb VDDQ K L M DQd DQd VDDQ DQd DQd DQd VSS VSS BWd VSS CLK NC DQa DQa VDDQ N DQd DQd VSS BWE A1 DQa DQa DQa VSS DQa DQa P DQd DQPd VSS A0 VSS DQPa DQa R NC VDD NC A NC NC A 64M MODE T A A A 32M ZZ U VDDQ TMS TDI TCK TDO NC VDDQ GW VDD BWa VSS CY7C1383B (1M × 18) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC A A A NC NC A A ADSC VDD A C A A NC D DQb NC VSS NC VSS DQPa NC E NC DQb VSS CE1 VSS NC DQa F VDDQ NC VSS OE VSS DQa VDDQ G H J NC DQb VDDQ DQb NC VDD BWb VSS NC ADV VSS VSS NC NC DQb VDD DQa NC VDDQ K L NC DQb DQb NC VSS VSS CLK NC VSS NC DQa DQa NC M VDDQ DQb VSS NC VDDQ N DQb NC VSS BWE A1 VSS DQa NC P NC DQPb VSS A0 VSS NC DQa R NC A MODE VDD NC A NC T U 64M VDDQ A TMS A TDI 32M TCK A TDO A NC ZZ VDDQ Document #: 38-05196 Rev. ** GW VDD BWa VSS Page 4 of 31 CY7C1381B CY7C1383B Pin Configurations (continued) 165-ball Bump FBGA CY7C1381B (512K × 36) – 11 × 15 FBGA 1 2 3 4 5 6 7 8 9 10 11 A NC A CE1 BWc BWb CE3 BWE ADSC ADV A NC B C D E F G H J K L M N P NC DPc A NC CE2 VDDQ BWd VSS BWa VSS CLK VSS GW VSS OE VSS ADSP VDDQ A NC 128M DPb DQb R DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb NC DQd VSS DQd NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ DQa DQd DQd DQd DQd VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DPd NC VDDQ VSS NC A NC VSS VDDQ NC DPa NC 64M A A TDI A1 TDO A A A A MODE 32M A A TMS A0 TCK A A A A 11 CY7C1383B (1M × 18) – 11 × 15 FBGA 1 2 3 4 5 6 7 8 9 10 A NC A CE1 BWb NC CE3 BWE ADSC ADV A A B C D E F G H J K L M N P NC NC A NC CE2 VDDQ NC VSS BWa VSS CLK VSS GW VSS OE VSS ADSP VDDQ A NC 128M DPa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VSS NC NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ NC DQb DQb NC NC VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa NC NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DPb NC VDDQ VSS NC A NC VSS VDDQ NC NC NC 64M A A TDI A1 TDO A A A A MODE 32M A A TMS A0 TCK A A A A R Document #: 38-05196 Rev. ** Page 5 of 31 CY7C1381B CY7C1383B Pin Definitions Name I/O Description A0 A1 A InputSynchronous Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two-bit counter. BWa BWb BWc BWd InputSynchronous Byte Write Select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable input, active LOW. When asserted LOW on the rising edge of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE). BWE InputSynchronous Byte Write Enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte Write. CLK Input-Clock Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputSynchronous Chip Enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE2 InputSynchronous Chip Enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device (TQFP only). CE3 InputSynchronous Chip Enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device (TQFP only) . OE InputAsynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state. ADV InputSynchronous Advance input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. MODE InputStatic Selects burst order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. ZZ InputAsynchronous ZZ “sleep” input. This active HIGH input places the device in a non-time-critical “sleep” condition with data integrity preserved. DQa, DPa DQb, DPb DQc, DPc DQd, DPd I/OSynchronous Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[X]during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQa–DQd and DPa–DPd are placed in a three-state condition. DQ a,b,c and d are eight-bits wide. DP a,b,c and d are one-bit wide. TDO JTAG serial output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). TDI JTAG serial input Synchronous Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only). Document #: 38-05196 Rev. ** Page 6 of 31 CY7C1381B CY7C1383B Pin Definitions (continued) Name I/O Description TMS Test Mode Select Synchronous This pin controls the Test Access Port (TAP) state machine. Sampled on the rising edge of TCK (BGA only). TCK JTAG Serial Clock Serial clock to the JTAG circuit (BGA only). VDD Power Supply VSS Ground VDDQ I/O Power Supply VSSQ I/O Ground Power supply inputs to the core of the device. Should be connected to 3.3V –5% +10% power supply. Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Ground for the I/O circuitry. Should be connected to ground of the system. NC – No connects. Pins are not internally connected. 32M 64M 128M – No connects. Reserved for address expansion. Pins are not internally connected. Document #: 38-05196 Rev. ** Page 7 of 31 CY7C1381B CY7C1383B Functional Description Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, and (2) Chip Enable (CE1, CE2, CE3 on TQFP, CE1 on BGA) is asserted active, and (3) the Write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) Chip Enable is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the RAM core. The Write signals (GW, BWE, and BWx) and ADV inputs are ignored during this first clock cycle. If the Write inputs are asserted active (see Write Cycle Descriptions table on page 10 for appropriate states that indicate a Write) on the next clock rise, the appropriate data will be latched and written into the device. The CY7C1381B/CY7C1383B provides byte Write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable (BWE) input with the selected Byte Write (BWa,b,c,d for CY7C1381B and BWa,b for CY7C1383B) input will selectively Write to only the desired bytes. Bytes not selected during a byte Write operation will remain unaltered. All I/Os are three-stated during a byte Write. Because the CY7C1381B/CY7C1383B is a common I/O device, the OE must be deasserted HIGH before presenting data to the DQx inputs. Doing so will three-state the output drivers. As a safety precaution, DQx are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) Chip Enable (CE1, CE2, CE3 on TQFP, CE1 on BGA) is asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BWx) is asserted active to conduct a Write to the desired byte(s). ADSC is ignored if ADSP is active LOW. The address presented to A[17:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQx is written into the corresponding address location in the RAM core. If a byte Write is conducted, only the selected Document #: 38-05196 Rev. ** bytes are written. Bytes not selected during a byte Write operation will remain unaltered. All I/Os are three-stated during a byte Write because the CY7C1381B/CY7C1383B is a common I/O device, the OE must be deasserted HIGH before presenting data to the DQx inputs. Doing so will three-state the output drivers. As a safety precaution, DQx are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1381B/CY7C1383B provides a two-bit wraparound counter fed by A[1:0] that implements either an interleaved or linear burst sequence to support processors that follow a linear burst sequence. The burst sequence is user-selectable through MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Interleaved Burst Sequence First Address Second Address Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Sequence First Address Second Address Third Address Fourth Address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ HIGH places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. Chip Enable (CE1, CE2, CE3, on TQFP, CE1 on BGA), ADSP and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Leaving ZZ unconnected defaults the device into an active state. Page 8 of 31 CY7C1381B CY7C1383B ZZ Mode Electrical Characteristics Parameter Description Test Conditions ICCZZ Sleep mode standby current tZZS Device operation to ZZ tZZREC ZZ recovery time Min. Max. Unit ZZ < VDD – 0.2V 20 mA ZZ < VDD – 0.2V 2tCYC ns ZZ ≤ 0.2V 2tCYC ns Cycle Descriptions[1, 2, 3] Next Cycle Add. Used ZZ CE3 CE2 CE1 ADSP ADSC ADV OE DQ Write Unselected None 0 X X 1 X 0 X X Hi-Z X Unselected None 0 1 X 0 0 X X X Hi-Z X Unselected None 0 X 0 0 0 X X X Hi-Z X Unselected None 0 1 X 0 1 0 X X Hi-Z X Unselected None 0 X 0 0 1 0 X X Hi-Z X Begin Read External 0 0 1 0 0 X X X Hi-Z X Begin Read External 0 0 1 0 1 0 X X Hi-Z Read Continue Read Next 0 X X X 1 1 0 1 Hi-Z Read Continue Read Next 0 X X X 1 1 0 0 DQ Read Continue Read Next 0 X X 1 X 1 0 1 Hi-Z Read Continue Read Next 0 X X 1 X 1 0 0 DQ Read Suspend Read Current 0 X X X 1 1 1 1 Hi-Z Read Suspend Read Current 0 X X X 1 1 1 0 DQ Read Suspend Read Current 0 X X 1 X 1 1 1 Hi-Z Read Suspend Read Current 0 X X 1 X 1 1 0 DQ Read Begin Write Current 0 X X X 1 1 1 X Hi-Z Write Begin Write Current 0 X X 1 X 1 1 X Hi-Z Write Begin Write External 0 0 1 0 1 0 X X Hi-Z Write Continue Write Next 0 X X X 1 1 0 X Hi-Z Write Continue Write Next 0 X X 1 X 1 0 X Hi-Z Write Suspend Write Current 0 X X X 1 1 1 X Hi-Z Write Suspend Write Current 0 X X 1 X 1 1 X Hi-Z Write ZZ “sleep” None 1 X X X X X X X Hi-Z X Note: 1. X = ”Don't Care”, 1 = HIGH, 0 = LOW. 2. The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is a “Don't Care” for the remainder of the Write cycle. 3. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle, DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active. Document #: 38-05196 Rev. ** Page 9 of 31 CY7C1381B CY7C1383B Write Cycle Description[1, 2, 3] Function (CY7C1381B) GW BWE BWd BWc BWb BWa Read 1 1 X X X X Read 1 0 1 1 1 1 Write Byte 0 – DQa 1 0 1 1 1 0 Write Byte 1 – DQb 1 0 1 1 0 1 Write Bytes 1, 0 1 0 1 1 0 0 Write Byte 2 – DQc 1 0 1 0 1 1 Write Bytes 2, 0 1 0 1 0 1 0 Write Bytes 2, 1 1 0 1 0 0 1 Write Bytes 2, 1, 0 1 0 1 0 0 0 Write Byte 3 – DQd 1 0 0 1 1 1 Write Bytes 3, 0 1 0 0 1 1 0 Write Bytes 3, 1 1 0 0 1 0 1 Write Bytes 3, 1, 0 1 0 0 1 0 0 Write Bytes 3, 2 1 0 0 0 1 1 Write Bytes 3, 2, 0 1 0 0 0 1 0 Write Bytes 3, 2, 1 1 0 0 0 0 1 Write All Bytes 1 0 0 0 0 0 Write All Bytes 0 X X X X X Function (CY7C1383B) Read GW BWE BWb BWa 1 1 X X Read 1 0 1 1 Write Byte 0 – DQa and DPa 1 0 1 0 Write Byte 1 – DQb and DPb 1 0 0 1 Write All Bytes 1 0 0 0 Write All Bytes 0 X X X Document #: 38-05196 Rev. ** Page 10 of 31 CY7C1381B CY7C1383B IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1381B/CY7C1383B incorporates a serial boundary scan TAP in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1–1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller , TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port – Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The e output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test Document #: 38-05196 Rev. ** circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The ×36 configuration has a 70-bit-long register, and the ×18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does Page 11 of 31 CY7C1381B CY7C1383B not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the I/O ring when these instructions are executed. When the SAMPLE/PRELOAD instructions loaded into the instruction register and the TAP controller in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. Document #: 38-05196 Rev. ** To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (TCS and TCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 12 of 31 CY7C1381B CY7C1383B TAP Controller State Diagram 1 TEST-LOGIC RESET 1 0 TEST-LOGIC/ 1 1 SELECT IDLE SELECT DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 SHIFT-DR SHIFT-IR 0 1 0 1 1 EXIT1-DR 1 EXIT1-IR 0 0 0 PAUSE-DR 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note: 4. Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05196 Rev. ** Page 13 of 31 CY7C1381B CY7C1383B TAP Controller Block Diagram 0 Bypass Register Selection Selection Circuitry TDI 2 1 0 2 1 0 2 1 0 Circuitry TDO Instruction Register 31 30 29 . . Identification Register x . . . . Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[5, 6] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = −4.0 mA 2.4 V VOH2 Output HIGH Voltage IOH = −100 µA VDD – 0.2 V VOL1 Output LOW Voltage IOL = 8.0 mA 0.4 V VOL2 Output LOW Voltage IOL = 100 µA 0.2 V VIH Input HIGH Voltage 1.7 VDD + 0.3 V VIL Input LOW Voltage −0.5 0.7 V IX Input Load Current −5 5 µA 5. 6. GND ≤ VI ≤ VDDQ All voltage referenced to Ground. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC / 2; undershoot: VIL (AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. Document #: 38-05196 Rev. ** Page 14 of 31 CY7C1381B CY7C1383B TAP AC Switching Characteristics Over the Operating Range[7, 8] Parameters Description Min. Max Unit 10 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency 100 ns tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after Clock Rise 10 ns Set-up Times Hold Times Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock HIGH to TDO Invalid 20 0 ns ns Notes: 7. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 8. Test conditions are specified using the load in TAP AC test conditions. Tr / Tf = 1 ns. Document #: 38-05196 Rev. ** Page 15 of 31 CY7C1381B CY7C1383B TAP Timing and Test Conditions 1.25V 50Ω ALL INPUT PULSES TDO 3.3V Z0 = 50Ω 1.50V CL = 20 pF 0V GND (a) tTH tTL Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV Document #: 38-05196 Rev. ** tTDOX Page 16 of 31 CY7C1381B CY7C1383B Identification Register Definitions Instruction Field 512K × 36 Revision Number (31:28) 1M × 18 Description xxxx xxxx Device Depth (27:23) 00111 01000 Reserved for version number. Defines depth of SRAM. 512K or 1M Device Width (22:18) 00100 00011 Defines with of the SRAM. ×36 or ×18 Cypress Device ID (17:12) xxxxx xxxxx Reserved for future use. Cypress JEDEC ID (11:1) 00011100100 00011100100 ID Register Presence (0) 1 1 Allows unique identification of SRAM vendor. Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size (×18) Bit Size (×36) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 51 70 Identification Codes Instruction Code Description EXTEST 000 Captures the I/O ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the I/O contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use. This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. RESERVED 101 Do Not Use. This instruction is reserved for future use. RESERVED 110 Do Not Use. This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05196 Rev. ** Page 17 of 31 CY7C1381B CY7C1383B Boundary Scan Order (512K × 18) Bit # Signal Name Bump ID Signal Name Bit # Boundary Scan Order (1M × 18) Bump ID Bit # Signal Name Bump ID Signal Name Bit # Bump ID 1 A 2R 36 A 6B 1 A 2R 36 DQb 2E 2 A 3T 37 BWa# 5L 2 A 2T 37 DQb 2G 3 A 4T 38 BWb# 5G 3 A 3T 38 DQb 1H 4 A 5T 39 BWc# 3G 4 A 5T 39 NC 5R 5 A 6R 40 BWd# 3L 5 A 6R 40 DQb 2K 6 A 3B 41 A 2B 6 A 3B 41 DQb 1L 7 A 5B 42 CE# 4E 7 A 5B 42 DQb 2M 8 DQa 6P 43 A 3A 8 DQa 7P 43 DQb 1N 9 DQa 7N 44 A 2A 9 DQa 6N 44 DQb 2P 10 DQa 6M 45 DQc 2D 10 DQa 6L 45 MODE 3R 11 DQa 7L 46 DQc 1E 11 DQa 7K 46 A 2C 12 DQa 6K 47 DQc 2F 12 ZZ 7T 47 A 3C 13 DQa 7P 48 DQc 1G 13 DQa 6H 48 A 5C 14 DQa 6N 49 DQc 1D 14 DQa 7G 49 A 6C 15 DQa 6L 50 DQc 1D 15 DQa 6F 50 A1 4N 16 DQa 7K 51 DQc 2E 16 DQa 7E 51 A0 4P 17 ZZ 7T 52 DQc 2G 17 DQa 6D 18 DQb 6H 53 DQc 1H 18 A 6T 19 DQb 7G 54 NC 5R 19 A 6A 20 DQb 6F 55 DQd 2K 20 A 5A 21 DQb 7E 56 DQd 1L 21 ADV# 4G 22 DQb 6D 57 DQd 2M 22 ADSP# 4A 23 DQb 7H 58 DQd 1N 23 ADSC# 4B 24 DQb 6G 59 DQd 2P 24 OE# 4F 25 DQb 6E 60 DQd 1K 25 BWE# 4M 26 DQb 7D 61 DQd 2L 26 GW# 4H 27 A 6A 62 DQd 2N 27 CLK 4K 28 A 5A 63 DQd 1P 28 A 6B 29 ADV# 4G 64 MODE 3R 29 BWa# 5L 30 ADSP# 4A 65 A 2C 30 BWb# 3G 31 ADSC# 4B 66 A 3C 31 A 2B 32 OE# 4F 67 A 5C 32 CE# 4E 33 BWE# 4M 68 A 6C 33 A 3A 34 GW# 4H 69 A1 4N 34 A 2A 35 CLK 4K 70 A0 4P 35 DQb 1D Document #: 38-05196 Rev. ** Page 18 of 31 CY7C1381B CY7C1383B Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −55°C to +150°C Ambient Temperature with Power Applied.................................................. −55°C to +125°C Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[9])................................ −0.5V to VDDQ + 0.5V DC Input Voltage[9] ..................................−0.5V to VDDQ + 0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage .......................................... >1500V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Ambient Temp[10] Range Commercial Industrial 0°C to +70°C –40°C to +85°C VDD VDDQ 3.3V 2.5V – 5% –5% / +10% 3.3V + 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.135 3.63 V VDDQ I/O Supply Voltage 2.375 3.63 V VOH Output HIGH Voltage VOL VIH VIL IX Output LOW Voltage VDD = Min., IOH = –1.0 mA VDDQ = 2.5V 2.0 V VDD = Min., IOH = –4.0 mA VDDQ = 3.3V 2.4 V VDD = Min., IOL = 1.0 mA VDDQ = 2.5V 0.4 V VDD = Min., IOL = 8.0 mA VDDQ = 3.3V 0.4 V Input HIGH Voltage Input LOW Voltage Input Load Current VDDQ = 3.3 V 2 V VDDQ = 2.5V 1.7 V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V 5 µA –30 30 µA –30 30 µA 5 µA 8.5-ns cycle, 117 MHz 250 mA 10-ns cycle, 100 MHz 225 mA GND < VI < VDDQ Input Current of MODE Input Current of ZZ Input = VSS IOZ Output Leakage Current GND < VI < VDDQ, Output Disabled IDD VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB1 Automatic CE Power-Down Current—TTL Inputs 12-ns cycle, 83 MHz 185 mA Max. VDD, Device Deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC 8.5-ns cycle, 117 MHz 100 mA 10-ns cycle, 100 MHz 90 mA 12-ns cycle, 83 MHz 75 mA ISB2 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, VIN < 0.3V or VIN > VDDQ – 0.3V, f=0 All speed grades 20 mA ISB3 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, or VIN < 0.3V or VIN > VDDQ – 0.3V f = fMAX = 1/tCYC 8.5-ns cycle, 117 MHz 90 mA 10-ns cycle, 100 MHz 75 mA 12-ns cycle, 83 MHz 60 mA Max. VDD, Device Deselected, VIN > VIH or VIN < VIL, f = 0 All speeds 50 mA ISB4 Automatic CS Power-Down Current—TTL Inputs Notes: 9. Minimum Voltage equals -2.0V for pulse duration of less than 20ns. 10. TA is the case temperature. Document #: 38-05196 Rev. ** Page 19 of 31 CY7C1381B CY7C1383B Capacitance[11] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V, VDDQ = 3.3V Max. Unit 3 pF 3 pF 3 pF AC Test Loads and Waveforms R = 1667Ω VDDQ OUTPUT ALL INPUT PULSES OUTPUT Z0 = 50Ω RL = 50Ω VDD 10% 5 pF (a) INCLUDING JIG AND SCOPE 90% 10% 90% GND R = 1538Ω < 1V/ns VTH= 1.25V [12] < 1 V/ns (c) (b) Thermal Resistance[11] Description 119 BGA 165 FBGA 100-pin TQFP Test Conditions QJA (Junction to Ambient) QJC (Junction to Case) Units 41.54 6.33 °C/W 44.51 2.38 °C/W 25 9 °C/W Still Air, soldered on a 114.3 × 101.6 × 1.57 mm3, 2-layer board Still Air, soldered on a 4.25 × 1.125 inch, 4-layer printed circuit board Notes: 11. Tested initially and after any design or process changes that may affect these parameters. 12. Input waveform should have a slew rate of 1 V/ns. Document #: 38-05196 Rev. ** Page 20 of 31 CY7C1381B CY7C1383B Switching Characteristics Over the Operating Range[13, 14, 15] –117 Parameter Description Min. –100 Max. Min. Max. –83 Min. Max. Unit tCYC Clock Cycle Time 8.5 10.0 12.0 ns tCH Clock HIGH 2.3 2.5 3.0 ns tCL Clock LOW 2.3 2.5 3.0 ns tAS Address Set-Up Before CLK Rise 1.5 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 ns tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.5 1.5 1.5 ns tADS ADSP, ADSC Set-Up Before CLK Rise 1.5 1.5 1.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 ns tWES BWE, GW, BWx Set-Up Before CLK Rise 1.5 1.5 1.5 ns tWEH BWE, GW, BWx Hold After CLK Rise 0.5 0.5 0.5 ns tADVS ADV Set-Up Before CLK Rise 1.5 1.5 1.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 ns tDS Data Input Set-Up Before CLK Rise 1.5 1.5 1.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 ns tCES Chip enable Set-Up 1.5 1.5 1.5 ns tCEH Chip enable Hold After CLK Rise 0.5 0.5 0.5 ns tCHZ tCLZ [13] Clock to High-Z 8.5 3.0 [13] Clock to Low-Z 1.3 [13, 14] tEOHZ OE HIGH to Output High-Z tEOLZ OE LOW to Output Low-Z[13, 14] tEOV 7.5 [13] OE LOW to Output Valid 3.0 1.3 4.0 0 3.0 1.3 4.0 0 3.4 10.0 ns ns 4.0 0 3.8 ns ns ns 4.2 ns Notes: 13. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads. 14. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 15. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ. Document #: 38-05196 Rev. ** Page 21 of 31 CY7C1381B CY7C1383B 1 Switching Waveforms Write Cycle Timing[16, 17] Burst Write Single Write Pipelined Write Unselected tCH tCYC CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADH tADS ADSC initiated Write ADSC tADVH tADVS ADV tAS ADD ADV must be inactive for ADSP Write WD1 WD3 WD2 tAH GW tWS tWH BWE tCES tWH tWS tCEH CE1 masks ADSP CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDH tDS Data-In High-Z 1a 1a 2a = Undefined 2b 2c 2d 3a High-Z Don’t Care Notes: 16. WE is the combination of BWE, BWx, and GW to define a Write cycle (see Write Cycle Descriptions table). 17. WDx stands for Write Data to Address X. Document #: 38-05196 Rev. ** Page 22 of 31 CY7C1381B CY7C1383B Switching Waveforms (continued) Read Cycle Timing[16, 18] Burst Read Single Read Unselected tCH tCYC Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated Read ADSC tADVS tADH Suspend Burst ADV tADVH tAS ADD RD1 RD3 RD2 tAH GW tWS tWS tWH BWE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES OE Data Out tCEH tEOV tCDV tOEHZ tDOH 2a 1a 1a 2b 2c 2c 2d 3a tCLZ tCHZ = Don’t Care = Undefined Note: 18. RDx stands for Read Data from Address X. Document #: 38-05196 Rev. ** Page 23 of 31 CY7C1381B CY7C1383B Switching Waveforms (continued) Read/Write Cycle Timing[16, 17, 18] Read/Write Timing tCYC tCH tCL CLK tAH tAS ADD A B D C tADH tADS ADSP tADH tADS ADSC tADVS tADVH ADV tCEH tCES CE1 tCEH tCES CE tWEH tWES BWE ADSP ignored with CE1 HIGH OE tEOHZ tCLZ Data In/Out Q(A) Q(B) Q Q (B+1) (B+2) Q (B+3) Q(B) D(C) D (C+1) D (C+2) D (C+3) Q(D) tCDV tDOH tCHZ Device originally deselected WE is the combination of BWE, BWx, and GW to define a Write cycle (see Write cycle description table). CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = Don’t Care Document #: 38-05196 Rev. ** = Undefined Page 24 of 31 CY7C1381B CY7C1383B Switching Waveforms (continued) Back to Back Read/Write Timing[19, 20] tCH tCYC tCL CLK tAS RD1 ADD tADS RD2 RD3 WD1 RD4 WD2 WD3 WD4 tADH ADSC initiated Reads ADSC ADSP initiated Reads ADSP ADV tCEH tCES CE1 CE tWEH tWES BWE ADSP ignored with CE1 HIGH OE tCLZ Data In/Out 1a Out 2a Out 3a Out 4a Out 1a In 2a In 3a In 4a D(C) In tCDV tDOH Back-to-Back Reads tCHZ Back-to-Back Writes = Don’t Care = Undefined Notes: 19. Device originally deselected. 20. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. Document #: 38-05196 Rev. ** Page 25 of 31 CY7C1381B CY7C1383B Switching Waveforms (continued) OE Switching Waveforms OE tEOV tEOHZ Three-State I/Os tEOLZ ZZ Mode Timing [19, 21] CLK ADSP HIGH ADSC CE1 CE2 LOW HIGH CE3 ZZ tZZS ICC ICC(active) tZZREC ICCZZ I/Os Three-state Note: 21. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05196 Rev. ** Page 26 of 31 CY7C1381B CY7C1383B Ordering Information Speed (MHz) 117 100 83 100 83 Ordering Code CY7C1381B-117AC CY7C1383B-117AC Package Name A101 CY7C1381B-117BGC CY7C1383B-117BGC BG119 CY7C1381B-117BZC CY7C1383B-117BZC BA165A CY7C1381B-100AC CY7C1383B-100AC A101 CY7C1381B-100BGC CY7C1383B-100BGC BG119 CY7C1381B-100BZC CY7C1383B-100BZC BA165A CY7C1381B-83AC CY7C1383B-83AC A101 CY7C1381B-83BGC CY7C1383B-83BGC BG119 CY7C1381B-83BZC CY7C1383B-83BZC BA165A CY7C1381B-100AI CY7C1383B-100AI A101 CY7C1381B-100BGI CY7C1383B-100BGI BG119 CY7C1381B-100BZI CY7C1383B-100BZI BA165A CY7C1381B-83AI CY7C1383B-83AI A101 CY7C1381B-83BGI CY7C1383B-83BGI BG119 CY7C1381B-83BZI CY7C1383B-83BZI BA165A Package Type Operating Range 100-Lead Thin Quad Flat Pack Commercial 119 BGA 165 FBGA 100-Lead Thin Quad Flat Pack 119 BGA 165 FBGA 100-Lead Thin Quad Flat Pack 119 BGA 165 FBGA 100-Lead Thin Quad Flat Pack Industrial 119 BGA 165 FBGA 100-Lead Thin Quad Flat Pack 119 BGA 165 FBGA Shaded areas contain advance information. Document #: 38-05196 Rev. ** Page 27 of 31 CY7C1381B CY7C1383B Pin Configurations 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 Document #: 38-05196 Rev. ** Page 28 of 31 CY7C1381B CY7C1383B Pin Configurations (continued) 119-lead FBGA (14 × 22 × 2.4 mm) BG119 Document #: 38-05196 Rev. ** Page 29 of 31 CY7C1381B CY7C1383B Pin Configurations (continued) 165-ball FBGA (13 × 15 × 1.2 mm) BB165A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05196 Rev. ** Page 30 of 31 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1381B CY7C1383B Revision History Document Title: CY7C1381B/CY7C1383B 512K x36/1M x18 Flow-Thru SRAM Document Number: 38-05196 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE ** 112032 12/09/01 DSG Document #: 38-05196 Rev. ** DESCRIPTION OF CHANGE Change from Spec number: 38-01077 to 38-05196 Page 31 of 31