AD ADUM4135 Single-/dual-supply, high voltage isolated igbt gate driver with miller clamp Datasheet

Single-/Dual-Supply, High Voltage Isolated
IGBT Gate Driver with Miller Clamp
ADuM4135
Data Sheet
FEATURES
GENERAL DESCRIPTION
4 A peak drive output capability
Output power device resistance: <1 Ω
Desaturation protection
Isolated desaturation fault reporting
Soft shutdown on fault
Miller clamp output with gate sense input
Isolated fault and ready functions
Low propagation delay: 55 ns typical
Minimum pulse width: 50 ns
Operating temperature range: −40°C to +125°C
Output voltage range to 30 V
Input voltage range from 2.3 V to 6 V
Output and input undervoltage lockout (UVLO)
Creepage distance: 7.8 mm minimum
100 kV/µs common-mode transient immunity (CMTI)
20 year lifetime for 600 V rms or 1092 V dc working voltage
Safety and regulatory approvals (pending)
5 kV ac for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak (reinforced/basic)
The ADuM4135 is a single-channel gate driver specifically
optimized for driving insulated gate bipolar transistors (IGBTs).
Analog Devices, Inc., iCoupler® technology provides isolation
between the input signal and the output gate drive.
The ADuM4135 includes a Miller clamp to provide robust
IGBT turn-off with a single-rail supply when the gate voltage
drops below 2 V. Operation with unipolar or bipolar secondary
supplies is possible, with or without the Miller clamp operation.
The Analog Devices chip scale transformers also provide
isolated communication of control information between the
high voltage and low voltage domains of the chip. Information
on the status of the chip can be read back from dedicated
outputs. Control of resetting the device after a fault on the
secondary is performed on the primary side of the device.
Integrated onto the ADuM4135 is a desaturation detection
circuit that provides protection against high voltage shortcircuit IGBT operation. The desaturation protection contains
noise reducing features such as a 300 ns masking time after a
switching event to mask voltage spikes due to initial turn-on.
An internal 500 µA current source allows low device count,
while the internal blanking switch allows the addition of an
external current source if more noise immunity is needed.
APPLICATIONS
MOSFET/IGBT gate drivers
PV inverters
Motor drives
Power supplies
The secondary UVLO is set to 11 V with common IGBT
threshold levels taken into consideration.
FUNCTIONAL BLOCK DIAGRAM
VSS1 1
VI+ 2
VSS2
15
GATE_SENSE
14
VOUT_ON
13
VDD2
2
2
CLAMP
LOGIC
VI– 3
16
2V
TSD
ADuM4135
1
UVLO
READY 4
MASTER
LOGIC
PRIMARY
1
FAULT 5
1
ENCODE
DECODE
DECODE
ENCODE
MASTER
LOGIC
SECONDARY
2
9V
RESET 6
12
VOUT_OFF
11
GND2
10
DESAT
9
VSS2
2
VDD1 7
VSS1 8
1
UVLO
2
13082-001
1
NOTES
1. GROUNDS ON PRIMARY AND SECONDARY SIDE ARE
ISOLATED FROM EACH OTHER.
Figure 1.
Rev. A
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ADuM4135
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................7
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................8
General Description ......................................................................... 1
Typical Performanace Characteristics ............................................9
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 12
Revision History ............................................................................... 2
PCB Layout ................................................................................. 12
Specifications..................................................................................... 3
Propagation Delay Related Parameters ................................... 12
Electrical Characteristics ............................................................. 3
Protection Features .................................................................... 12
Package Characteristics ............................................................... 5
Power Dissipation....................................................................... 14
Regulatory Information ............................................................... 5
DC Correctness and Magnetic Field Immunity........................... 15
Insulation and Safety Related Specifications ............................ 5
Insulation Lifetime ..................................................................... 15
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 6
Typical Application .................................................................... 16
Outline Dimensions ....................................................................... 17
Recommended Operating Conditions ...................................... 6
Ordering Guide .......................................................................... 17
Absolute Maximum Ratings............................................................ 7
REVISION HISTORY
9/15—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changed TA to TJ .............................................................................. 3
Added Common-Mode Transient Immunity (CMTI)
Parameter, Table 1............................................................................. 4
Changes to Table 3 and Table 4 ....................................................... 5
Changes to Table 6 ............................................................................ 6
Changes to Table 7 ............................................................................ 7
Changes to Figure 16 Caption and Figure 17 Caption .............. 11
Changes to Fault Reporting Section............................................. 12
Change to Figure 28 ....................................................................... 16
7/15—Revision 0: Initial Version
Rev. A | Page 2 of 17
Data Sheet
ADuM4135
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Low-side voltages referenced to VSS1. High-side voltages referenced to GND2, 2.3 V ≤ VDD1 ≤ 6 V, 12 V ≤ VDD2 ≤ 30 V, and TJ = −40°C to +125°C.
All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are
at TJ = 25°C, VDD1 = 5.0 V, and VDD2 = 15 V.
Table 1.
Parameter
DC SPECIFICATIONS
High-Side Power Supply
Input Voltage
VDD2
VSS2
Input Current, Quiescent
VDD2
VSS2
Logic Supply
VDD1 Input Voltage
Input Current
Output Low
Output High
Logic Inputs (VI+, VI−, RESET)
Input Current (VI+, VI− Only)
Logic High Input Voltage
Symbol
Min
VDD2
VSS2
12
−15
Max
Unit
Test Conditions/Comments
30
0
V
V
VDD2 − VSS2 ≤ 30 V
4.37
6.21
mA
mA
6
V
1.78
4.78
2.17
5.89
mA
mA
Output signal low
Output signal high
+0.01
+1
µA
V
2.3 V ≤ VDD1 − VSS1 ≤ 5 V
V
V
VDD1 − VSS1 > 5 V
2.3 V ≤ VDD1 − VSS1 ≤ 5 V
V
kΩ
VDD1 − VSS1 > 5 V
Ready high
IDD2 (Q)
ISS2 (Q)
VDD1
IDD1
II
VIH
Logic Low Input Voltage
VIL
RESET Internal Pull-Down
RRESET_PD
UVLO
VDD1 Positive Going Threshold
VDD1 Negative Going Threshold
VDD1 Hysteresis
VDD2 Positive Going Threshold
VDD2 Negative Going Threshold
VDD2 Hysteresis
FAULT Pull-Down FET Resistance
Typ
VVDD1UV+
VVDD1UV−
VVDD1UVH
VVDD2UV+
VVDD2UV−
VVDD2UVH
RFAULT
3.62
4.82
2.3
−1
0.7 ×
VDD1
3.5
0.29 ×
VDD1
1.5
300
2.0
10.4
2.23
2.135
0.095
11.5
11.1
0.4
11
2.3
50
V
V
V
V
V
V
Ω
12.0
Tested at 5 mA
11
50
Ω
Tested at 5 mA
9.2
537
9.61
593
V
µA
2.25
625
625
975
975
°C
°C
V
mΩ
mΩ
mΩ
mΩ
_PD_FET
READY Pull-Down FET Resistance
Desaturation (DESAT)
Desaturation Detect Comparator Voltage
Internal Current Source
Thermal Shutdown
TSD Positive Edge
TSD Hysteresis
Miller Clamp Voltage Threshold
Internal NMOS Gate Resistance
RRDY_PD_FET
TTSD_POS
TTSD_HYST
VCLP_TH
RDSON_N
Internal PMOS Gate Resistance
RDSON_P
VDESAT, TH
IDESAT_SRC
8.73
481
1.75
155
20
2
315
318
471
479
Rev. A | Page 3 of 17
Referenced to VSS2
Tested at 250 mA
Tested at 1 A
Tested at 250 mA
Tested at 1 A
ADuM4135
Parameter
Soft Shutdown NMOS
Internal Miller Clamp Resistance
Peak Current
SWITCHING SPECIFICATIONS
Pulse Width1
Data Sheet
Symbol
RDSON_FAULT
RDSON_MILLER
Min
PW
50
RESET Debounce
tDEB_RESET
500
615
700
ns
Propagation Delay3
tDHL, tDLH
40
55
66
ns
Propagation Delay Skew4
tPSK
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
11
16
22.9
ns
tDESAT_DELAY
tREPORT
213
312
0.5
529
2
ns
μs
|CM|
100
Blanking Capacitor Discharge Switch Masking
Time to Report Desaturation Fault to FAULT
Pin
Common-Mode Transient Immunity (CMTI)
Static CMTI5
Dynamic CMTI6
Typ
10.2
1.1
4.61
1
Max
22
2.75
Unit
Ω
Ω
A
Test Conditions/Comments
Tested at 250 mA
Tested at 100 mA
VDD2 = 12 V, 2 Ω gate resistance
ns
CL = 2 nF, VDD2 = 15 V,
RGON2 = RGOFF2 = 3.9 Ω
kV/μs
CL = 2 nF, VDD2 = 15 V,
RGON2 = RGOFF2 = 3.9 Ω
CL = 2 nF, RGON2 = RGOFF2 = 3.9 Ω,
VDD1 = 5 V to 6 V
CL = 2 nF, VDD2 = 15 V,
RGON2 = RGOFF2 = 3.9 Ω
VCM = 1000 V
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
See the Power Dissipation section.
tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOUTx signal. tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOUTx signal. See Figure 20 for waveforms of propagation
delay parameters.
4
tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
5
Static common-mode transient immunity (CMTI) is defined as the largest dv/dt between VSS1 and VSS2, with inputs held either high or low, such that the output voltage
remains either above 0.8 × VDD2 for output high or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets.
6
Dynamic common-mode transient immunity (CMTI) is defined as the largest dv/dt between VSS1 and VSS2 with the switching edge coincident with the transient test
pulse. Operation with transients above recommended levels can cause momentary data upsets.
2
3
Rev. A | Page 4 of 17
Data Sheet
ADuM4135
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input Side to High-Side Output) 1
Capacitance (Input Side to High-Side Output)1
Input Capacitance
Junction to Ambient Thermal Resistance
Junction to Case Thermal Resistance
1
Symbol
RI-O
CI-O
CI
θJA
θJC
Min
Typ
1012
2.0
4.0
75.4
35.4
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions/Comments
4-layer printed circuit board (PCB)
4-layer PCB
The device is considered a two-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
REGULATORY INFORMATION
The ADuM4135 is pending approval by the organizations listed in Table 3.
Table 3.
UL (Pending)
Recognized under UL 1577
Component Recognition Program 1
Single Protection,
5000 V rms Isolation Voltage
File E214100
1
2
CSA (Pending)
Approved under CSA Component Acceptance Notice 5A
VDE (Pending)
Certified according to VDE0884-10 2
Basic insulation per CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2, 780 V rms (1103 V
peak) maximum working voltage
Reinforced insulation, 849 V peak
Basic insulation, 849 V peak
Reinforced Insulation per CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2, 390 V rms (551 V
peak) maximum working voltage
File 205078
File 2471900-4880-0001
In accordance with UL 1577, each ADuM4135 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).
In accordance with DIN V VDE V 0884-10, each ADuM4135 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge
detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5000
7.8 min
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
7.8 min
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.026 min
>400
II
mm
V
Rev. A | Page 5 of 17
Test Conditions/Comments
1 minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM4135
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective
circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 5. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety Limiting Values
VIORM × 1.875 = Vpd (m), 100% production test, tini = tm =
1 sec, partial discharge < 5 pC
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 2)
VIO = 500 V
Symbol
Characteristic
Unit
VIORM
Vpd (m)
I to IV
I to III
I to II
40/105/21
2
849
1592
V peak
V peak
Vpd (m)
1274
V peak
Vpd (m)
1019
V peak
VIOTM
VIOSM
8000
8000
V peak
V peak
TS
PS
RS
150
2.77
>109
°C
W
Ω
RECOMMENDED OPERATING CONDITIONS
3.0
Table 6.
2.5
2.0
1.5
1.0
0.5
0
0
100
150
50
AMBIENT TEMPERATURE (°C)
200
13082-002
SAFE OPERATING PVDD1 , PVDD1 , PVDD1 POWER (W)
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
Test Conditions/Comments
Figure 2. ADuM4135 Thermal Derating Curve, Dependence of Safety
Limiting Values on Case Temperature, per DIN V VDE V 0884-10
Parameter
Operating Temperature Range (TA)
Supply Voltages
VDD1 1
VDD2 2
VDD2 − VSS22
VSS22
Input Signal Rise/Fall Time
Static Common-Mode Transient
Immunity 3
Dynamic Common-Mode Transient
Immunity 4
Value
−40°C to +125°C
2.3 V to 6 V
12 V to 30 V
12 V to 30 V
−15 V to 0 V
1 ms
−100 kV/µs to
+100 kV/µs
−100 kV/µs to
+100 kV/µs
Referenced to VSS1.
Referenced to GND2.
Static common-mode transient immunity is defined as the largest dv/dt
between VSS1 and VSS2, with inputs held either high or low, such that the
output voltage remains either above 0.8 × VDD2 for output high or 0.8 V for
output low. Operation with transients above recommended levels can cause
momentary data upsets.
4
Dynamic common-mode transient immunity is defined as the largest dv/dt
between VSS1 and VSS2 with the switching edge coincident with the transient
test pulse. Operation with transients above recommended levels can cause
momentary data upsets.
1
2
3
Rev. A | Page 6 of 17
Data Sheet
ADuM4135
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Storage Temperature Range (TST)
Ambient Operating Temperature
Range (TA)
Supply Voltages
VDD11
VDD22
VSS22
VDD2 − VSS22
Input Voltages
VI+, VI−, RESET
VDESAT
VGATE_SENSE
VOUT_ON
VOUT_OFF
VOUT_ON, VOUT_OFF Current for 1.5 µs
at 15 kHz
Common-Mode Transients (|CM|)
1
2
Table 8. Maximum Continuous Working Voltage1
Rating
−55°C to +150°C
−40°C to +125°C
−0.3 V to +6.5 V
−0.3 V to +40 V
−20 V to +0.3 V
35 V
Parameter
60 Hz AC Voltage
Value
600 V rms
DC Voltage
1092 V peak
1
2
3
−0.3 V to +6.5 V
−0.3 V to VDD2 + 0.3 V
−0.3 V to VDD2 + 0.3 V
−0.3 V to VDD2 + 0.3 V
−0.3 V to VDD2 + 0.3 V
6A
Constraint
20 year lifetime at 0.1%
failure rate, zero average
voltage
Limited by the creepage
of the package,
Pollution Degree 2,
Material Group II2, 3
See the Insulation Lifetime section for details.
Other pollution degree and material group requirements yield a different limit.
Some system level standards allow components to use the printed wiring
board (PWB) creepage values. The supported dc voltage may be higher for
those standards.
ESD CAUTION
−150 kV/µs to +150 kV/µs
Referenced to VSS1.
Referenced to GND2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 9. Truth Table (Positive Logic) 1
VI+ Input
L
L
H
H
X
X
L
X
X
VI− Input
L
H
L
H
X
X
L
X
X
RESET Pin
H
H
H
H
H
H
H
L3
X
READY Pin
H
H
H
H
L
Unknown
L
Unknown
L
FAULT Pin
H
H
H
H
Unknown
L
Unknown
H3
Unknown
X is don’t care, L is low, and H is high.
VGATE is the voltage of the gate being driven.
3
Time dependent value. See the Absolute Maximum Ratings section for details on timing.
1
2
Rev. A | Page 7 of 17
VDD1 State
Powered
Powered
Powered
Powered
Powered
Powered
Unpowered
Powered
Powered
VDD2 State
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Unpowered
VGATE 2
L
L
H
L
L
L
L
L
Unknown
ADuM4135
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
VI+
2
VI–
3
READY
4
16 VSS2
ADuM4135
TOP VIEW
(Not to Scale)
15 GATE_SENSE
14 VOUT_ON
13 VDD2
FAULT
5
12 VOUT_OFF
RESET
6
11 GND2
VDD1
7
10 DESAT
VSS1
8
9
VSS2
13082-003
VSS1
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1, 8
2
3
4
Mnemonic
VSS1
V I+
V I−
READY
5
FAULT
6
7
9, 16
10
RESET
VDD1
VSS2
DESAT
11
GND2
12
13
14
15
VOUT_OFF
VDD2
VOUT_ON
GATE_SENSE
Description
Ground Reference for Primary Side.
Positive Logic CMOS Input Drive Signal.
Negative Logic CMOS Input Drive Signal.
Open-Drain Logic Output. Connect this pin to a pull-up resistor to read the signal. A high state on this pin
indicates that the device is functional and ready to operate as a gate driver. The presence of READY low
precludes the gate drive output from going high.
Open-Drain Logic Output. Connect this pin to a pull-up resistor to read the signal. A low state on this pin
indicates when a desaturation fault has occurred. The presence of a fault condition precludes the gate drive
output from going high.
CMOS Input. When a fault exists, bring this pin low to clear the fault.
Input Supply Voltage on Primary Side, 2.3 V to 5.5 V Referenced to VSS1.
Negative Supply for Secondary Side, −15 V to 0 V Referenced to GND2.
Detection of Desaturation Condition. Connect this pin to an external current source or a pull-up resistor. This
pin can allow NTC temperature detection or other fault conditions. A fault on this pin asserts a fault on the
FAULT pin on the primary side. Until the fault is cleared on the primary side, the gate drive is suspended.
During a fault condition, a smaller turn-off FET slowly brings the gate voltage down.
Ground Reference for Secondary Side. Connect this pin to the emitter of the IGBT or the source of the MOSFET
being driven.
Gate Drive Output Current Path for Off Signal.
Secondary Side Input Supply Voltage, 12 V to 30 V Referenced to GND2.
Gate Drive Output Current Path for On Signal.
Gate Voltage Sense Input and Miller Clamp Output. Connect this pin to the gate of the power device being
driven. This pin senses the gate voltage for the purpose of Miller clamping. When the Miller clamp is not used,
tie GATE_SENSE to VSS2.
Rev. A | Page 8 of 17
Data Sheet
ADuM4135
TYPICAL PERFORMANACE CHARACTERISTICS
CH1 = VI+ (2V/DIV)
CH1 = VI+ (2V/DIV)
1
1
CH2 = VGATE (2V/DIV)
CH2 = VGATE (5V/DIV)
2
B
W
CH2 5.0V
B
W
M 100ns A CH1
520mV
10.0GS/s
20.0ps/pt
CH1 2.0V
B
W
CH2 5.0V
B
W
M 100ns A CH1
520mV
10.0GS/s
20.0ps/pt
13082-007
CH1 2.0V
13082-004
2
Figure 7. Typical Input to Output Waveform, 2 nF Load,
3.9 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V
Figure 4. Typical Input to Output Waveform, 2 nF Load,
5.1 Ω Series Gate Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V
4.0
VDD1 = 5.0V
3.5
VDD1 = 3.3V
CH1 = VI+ (2V/DIV)
3.0
1
IDD1 (mA)
CH2 = VGATE (5V/DIV)
VDD1 = 2.3V
2.5
2.0
1.5
1.0
2
B
W
CH2 5.0V
B
W
520mV
M 100ns A CH1
10.0GS/s
20.0ps/pt
0
13082-005
CH1 2.0V
0
Figure 5. Typical Input to Output Waveform, 2 nF Load,
5.1 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V
200K
400K
600K
FREQUENCY (Hz)
800K
1M
13082-008
0.5
Figure 8. Typical IDD1 Current vs. Frequency, Duty = 50%, VI+ = VDD1
60
50
CH1 = VI+ (2V/DIV)
VDD2 = 15V
1
40
IDD2 (mA)
CH2 = VGATE (5V/DIV)
30
VDD2 = 20V
20
VDD2 = 12V
2
B
W
CH2 5.0V
B
W
M 100ns A CH1
960mV
10.0GS/s
20.0ps/pt
0
13082-006
CH1 2.0V
Figure 6. Typical Input to Output Waveform, 2 nF Load,
3.9 Ω Series Gate Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V
0
200K
400K
600K
FREQUENCY (Hz)
800K
1M
13082-009
10
Figure 9. Typical IDD2 Current vs. Frequency, Duty = 50%, 2 nF Load, VSS2 = 0 V
Rev. A | Page 9 of 17
ADuM4135
Data Sheet
80
CH1 = VI+ (5V/DIV)
tDLH
tDHL
70
1
PROPAGATION DELAY (ns)
CH2 = VGATE (5V/DIV)
2
CH3 = VDD2 (10V/DIV)
60
50
40
30
20
B
B
W
CH2 5.0V
B
W
W
M 10.0µs A CH3
6.0V
1.0GS/s
1.0ns/pt
0
2.3
13082-010
80
80
tDLH
tDHL
70
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
tDLH
tDHL
60
50
40
30
20
60
50
40
30
20
10
10
17
22
VDD2 (V)
0
–40
13082-011
0
12
5.3
Figure 13. Typical Propagation Delay vs. Input Supply Voltage,
VDD2 − VSS2 = 12 V
Figure 10. Typical VDD2 Startup to Output Valid
70
3.3
4.3
INPUT SUPPLY VOLTAGE (V)
27
Figure 11. Typical Propagation Delay vs. Output Supply Voltage (VDD2) for
VDD2 = 15 V and VDD1 = 5 V
10
60
AMBIENT TEMPERATURE (°C)
110
13082-014
CH1 5.0V
CH3 10.0V
13082-013
10
3
Figure 14. Typical Propagation Delay vs. Ambient Temperature,
VDD2 = 5 V, VDD2 – VSS2 = 12 V
30
RISE/FALL TIME (ns)
CH1 = VI+ (5V/DIV)
1
25
CH2 = VGATE (10V/DIV)
20
2
CH3 = FAULT (5V/DIV)
15
10
3
CH4 = DESAT (5V/DIV)
5
17
22
VDD2 (V)
27
13082-012
0
12
CH1 5.0V
CH3 5.0V
Figure 12. Typical Rise/Fall Time vs. VDD2, VDD2 – VSS2 = 12 V, VDD1 = 5 V,
2 nF Load, RG = 3.9 Ω
Rev. A | Page 10 of 17
B
W
B
W
CH2 10.0V
CH4 5.0V
B
W
B
W
M 200ns
5.0GS/s
A CH1
3.1V
200ps/pt
Figure 15. Example Desaturation Event and Reporting
13082-015
4
tDLH
tDHL
Data Sheet
ADuM4135
800
CH1 = VI+ (5V/DIV)
700
SOURCE RESISTANCE
1
500
400
CH2 = VGATE (5V/DIV)
300
2
100
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
CH1 5.0V
CH3 10.0V
Figure 16. Typical Output Resistance (RDSON) vs. Temperature, VDD2 = 15 V,
250 mA Test
700
8
RDSON (mΩ)
PEAK OUTPUT CURRENT (A)
9
SOURCE RESISTANCE
500
400
300
SINK RESISTANCE
200
100
CH2 5.0V
B
W
M 10.0µs A CH3
6.0V
1.0GS/s
1.0ns/pt
PEAK SINK IOUT
7
6
5
PEAK SOURCE IOUT
4
3
2
1
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
13082-017
0
–40
W
B
W
Figure 18. Example RESET to Output Valid
800
600
B
13082-018
3
13082-016
0
–40
CH3 = RESET (5V/DIV)
SINK RESISTANCE
200
0
12
Figure 17. Typical Output Resistance (RDSON) vs. Temperature, VDD2 = 15 V,
1 A Test
14.5
17
19.5
22
OUTPUT SUPPLY VOLTAGE (V)
24.5
13082-019
RDSON (mΩ)
600
Figure 19. Typical Peak Output Current vs. Output Supply Voltage,
2 Ω Series Resistance (IOUT is the Current Going into/out of the Device Gate)
Rev. A | Page 11 of 17
ADuM4135
Data Sheet
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM4135 IGBT gate driver requires no external interface
circuitry for the logic interfaces. Power supply bypassing is required
at the input and output supply pins. Use a small ceramic capacitor
with a value between 0.01 µF and 0.1 µF to provide a good high
frequency bypass. On the output power supply pin, VDD2, it is
recommended also to add a 10 µF capacitor to provide the charge
required to drive the gate capacitance at the ADuM4135 outputs.
On the output supply pin, avoid the use of vias on the bypass
capacitor or employ multiple vias to reduce the inductance in
the bypassing. The total lead length between both ends of the
smaller capacitor and the input or output power supply pin
must not exceed 5 mm.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay describes the time it takes a logic signal to
propagate through a component. The propagation delay to a low
output can differ from the propagation delay to a high output. The
ADuM4135 specifies tDLH as the time between the rising input
high logic threshold (VIH) to the output rising 10% threshold (see
Figure 20). Likewise, the falling propagation delay (tDHL) is defined
as the time between the input falling logic low threshold (VIL) and
the output falling 90% threshold. The rise and fall times are
dependent on the loading conditions and are not included in the
propagation delay, which is the industry standard for gate drivers.
While RESET remains held low, the output remains disabled. The
RESET pin has an internal, 300 kΩ pull-down resistor.
Desaturation Detection
Occasionally, component failures or faults occur with the
circuitry connected to the IGBT connected to the ADuM4135.
Examples include shorts in the inductor/motor windings or
shorts to power/ground buses. The resulting excess in current
flow causes the IGBT to come out of saturation. To detect this
condition and to reduce the likelihood of damage to the FET, a
threshold circuit is used on the ADuM4135. If the DESAT pin
exceeds the desaturation threshold (VDESAT, TH) of 9 V while the
high-side driver is on, the ADuM4135 enters the failure state
and turns the IGBT off. At this time, the FAULT pin is brought
low. An internal current source of 500 µA is provided, as well as
the option to boost the charging current using external current
sources or pull-up resistors. The ADuM4135 has a built-in
blanking time to prevent false triggering while the IGBT first
turns on. The time between desaturation detection and reporting
a desaturation fault to the FAULT pin is less than 2 µs (tREPORT).
Bring RESET low to clear the fault. There is a 500 ns debounce
(tDEB_RESET) on the RESET pin. The time, tDESAT_DELAY, shown in
Figure 21, provides a 300 ns masking time that keeps the
internal switch that grounds the blanking capacitor tied low
for the initial portion of the IGBT on time.
DESAT
EVENT
90%
OUTPUT
V I+
10%
VIH
VGATE
INPUT
VIL
tDESAT_DELAY = 300ns
tDHL
tR
tF
DESAT
SWITCH
13082-020
tDLH
ON OFF
Figure 20. Propagation Delay Parameters
ON
OFF
ON
< 200ns
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM4135
components operating under the same temperature, input
voltage, and load conditions.
VCE
9V
~2µs RECOMMENDED
VDD2
PROTECTION FEATURES
9V
Fault Reporting
VDESAT
Rev. A | Page 12 of 17
Vf
tREPORT < 2µs
13082-021
The ADuM4135 provides protection for faults that may occur
during the operation of an IGBT. The primary fault condition is
desaturation. If saturation is detected, the ADuM4135 shuts down
the gate drive and asserts FAULT low. The output remains disabled
until RESET is brought low for more than 500 ns, and is then
brought high. FAULT resets to high on the falling edge of RESET.
FAULT
Figure 21. Desaturation Detection Timing Diagram
Data Sheet
ADuM4135
In the case of a desaturation event, VCE rises above the 9 V
threshold in the desaturation detection circuit. If no RBLANK resistor
is used to increase the blanking current, the voltage on the blanking
capacitor, CBLANK, rises at a rate of 500 µA (typical) divided by the
CBLANK capacitance. Depending on the IGBT specifications, a
blanking time of approximately 2 µs is a typical design choice.
When the DESAT pin rises above the 9 V threshold, a fault
registers, and within 200 ns, the gate output drives low. The
output is brought low using the N-FET fault MOSFET, which
is approximately 50 times more resistive than the internal gate
driver N-FET, to perform a soft shutdown to reduce the chance
of an overvoltage spike on the IGBT during an abrupt turn-off
event. Within 2 µs, the fault is communicated back to the primary
side FAULT pin. To clear the fault, a reset is required.
Miller Clamp
The ADuM4135 has an integrated Miller clamp to reduce voltage
spikes on the IGBT gate caused by the Miller capacitance during
shut-off of the IGBT. When the input gate signal calls for the IGBT
to turn off (driven low), the Miller clamp MOSFET is initially
off. When the voltage on the GATE_SENSE pin crosses the 2 V
internal voltage reference, as referenced to VSS2, the internal
Miller clamp latches on for the remainder of the off time of the
IGBT, creating a second low impedance current path for the gate
current to follow. The Miller clamp switch remains on until the
input drive signal changes from low to high. An example waveform
of the timings is shown in Figure 22.
V I+
V I–
V DD2
VGATE_SENSE
2V
VSS2
MILLER
CLAMP
SWITCH
OFF
ON
LATCH ON
OFF
LATCH OFF
13082-022
For the following design example, see the schematic shown in
Figure 28 along with the waveforms in Figure 21. Under normal
operation, during IGBT off times, the voltage across the IGBT,
VCE, rises to the rail voltage supplied to the system. In this case,
the blocking diode shuts off, protecting the ADuM4135 from
high voltages. During the off times, the internal desaturation
switch is on, accepting the current going through the RBLANK
resistor, which allows the CBLANK capacitor to remain at a low
voltage. For the first 300 ns of the IGBT on time, the DESAT
switch remains on, clamping the DESAT pin voltage low. After
the 300 ns delay time, the DESAT pin is released, and the DESAT
pin is allowed to rise towards VDD2 either by the internal current
source on the DESAT pin, or additionally with an optional external
pull-up, RBLANK, to increase the current drive if it is not clamped
by the collector or drain of the switch being driven. VRDESAT is
chosen to dampen the current at this time, usually selected around
100 Ω to 2 kΩ. Select the blocking diode to block above the
high rail voltage on the collector of the IGBT and to be a fast
recovery diode.
Figure 22. Miller Clamp Example
Thermal Shutdown
If the internal temperature of the ADuM4135 exceeds 155°C
(typical), the device enters thermal shutdown (TSD). During
the thermal shutdown time, the READY pin is brought low
on the primary side, and the gate drive is disabled. When
TSD occurs, the device does not leave TSD until the internal
temperature drops below 125°C (typical), at which time the
READY pin returns to high, and the device exits shutdown.
Undervoltage Lockout (UVLO) Faults
UVLO faults occur when the supply voltages are below the
specified UVLO threshold values. During a UVLO event on either
the primary side or secondary side, the READY pin goes low, and
the gate drive is disabled. When the UVLO condition is removed,
the device resumes operation, and the READY pin goes high.
READY Pin
The open-drain READY pin is an output that confirms
communication between the primary to secondary sides is
active. The READY pin remains high when there are no UVLO
or TSD events present. When the READY pin is low, the IGBT
gate is driven low.
Table 11. READY Pin Logic Table
UVLO
No
Yes
No
Yes
Rev. A | Page 13 of 17
TSD
No
No
Yes
Yes
READY Pin Output
High
Low
Low
Low
ADuM4135
Data Sheet
FAULT Pin
Gate Resistance Selection
The open-drain FAULT pin is an output to communicate that a
desaturation fault has occurred. When the FAULT pin is low, the
IGBT gate is driven low. If a desaturation event occurs, the
RESET pin must be driven low for at least 500 ns, then high to
return operation to the IGBT gate drive.
The ADuM4135 provides two output nodes for the driving of
an IGBT. The benefit of this approach is that the user can select
two different series resistances for the turn-on and turn-off of
the IGBT. It is generally desired to have the turn-off occur faster
than the turn-on. To select the series resistance, decide what the
maximum allowed peak current is for the IGBT. Knowing the
voltage swing on the gate, as well as the internal resistance of
the gate driver, an external resistor can be chosen.
RESET Pin
The RESET pin has an internal 300 kΩ (typical) pull-down
resistor. The RESET pin accepts CMOS level logic. When the
RESET pin is held low, after a 500 ns debounce time, any faults
on the FAULT pin are cleared. While the RESET pin is held low,
the switch on VOUT_OFF is closed, bringing the gate voltage of the
IGBT low. When RESET is brought high, and no fault exists, the
device resumes operation.
<500ns
IPEAK = (VDD2 − VSS2)/(RDSON_N + RGOFF)
For example, if the turn-off peak current is 4 A, with a (VDD2 − VSS2)
of 18 V,
RGOFF = ((VDD2 − VSS2) − IPEAK × RDSON_N)/IPEAK
RGOFF = (18 V − 4 A × 0.6 Ω)/4 A = 3.9 Ω
After RGOFF is selected, a slightly larger RGON can be selected to
arrive at a slower turn-on time.
500ns
POWER DISSIPATION
RESET
13082-023
FAULT
Figure 23. RESET Timing
VI+ and VI− Operation
The ADuM4135 has two drive inputs, VI+ and VI−, to control
the IGBT gate drive signals, VOUT_ON and VOUT_OFF. Both the VI+
and VI− inputs use CMOS logic level inputs. The input logic of
the VI+ and VI− pins can be controlled by either asserting the
VI+ pin high or the VI− pin low. With the VI− pin low, the VI+ pin
accepts positive logic. If VI+ is held high, the VI− pin accepts
negative logic. If a fault is asserted, transmission is blocked
until the fault is cleared by the RESET pin.
VI+
VOUT_ON
VI–
2
13082-024
VOUT_OFF
FAULT
Figure 24. VI+ and VI− Block Diagram
The minimum pulse width, PW, is the minimum period in
which the timing specifications are guaranteed.
During the driving of an IGBT gate, the driver must dissipate
power. This power is not insignificant and can lead to TSD if
considerations are not made. The gate of an IGBT can be roughly
simulated as a capacitive load. Due to Miller capacitance and other
nonlinearities, it is common practice to take the stated input
capacitance, CISS, of a given IGBT, and multiply it by a factor of
5 to arrive at a conservative estimate to approximate the load
being driven. With this value, the estimated total power
dissipation in the system due to switching action is given by
PDISS = CEST × (VDD2 − VSS2)2 × fS
where:
CEST = CISS × 5.
fS is the switching frequency of the IGBT.
This power dissipation is shared between the internal on
resistances of the internal gate driver switches and the external
gate resistances, RGON and RGOFF. The ratio of the internal gate
resistances to the total series resistance allows the calculation of
losses seen within the ADuM4135 chip.
PDISS_ADuM4135 = PDISS × 0.5(RDSON_P/(RGON + RDSON_P) +
RDSON_N/(RGOFF + RDSON_N))
Taking the power dissipation found inside the chip and
multiplying it by the θJA gives the rise above ambient temperature
that the ADuM4135 experiences.
TADuM4135 = θJA × PDISS_ADuM4135 + TAMB
For the device to remain within specification, TADUM4135 must
not exceed 125°C. If TADuM4135 exceeds 155°C (typical), the
device enters thermal shutdown.
Rev. A | Page 14 of 17
Data Sheet
ADuM4135
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Surface Tracking
The ADuM4135 is resistant to external magnetic fields. The
limitation on the ADuM4135 magnetic field immunity is set by
the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which a false reading condition can occur. The 2.3 V operating
condition of the ADuM4135 is examined because it represents
the most susceptible mode of operation.
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working
voltage, the environmental conditions, and the properties of the
insulation material. Safety agencies perform characterization
testing on the surface insulation of components that allows the
components to be categorized in different material groups.
Lower material group ratings are more resistant to surface
tracking and therefore can provide adequate lifetime with
smaller creepage. The minimum creepage for a given working
voltage and material group is in each system level standard and
is based on the total rms voltage across the isolation, pollution
degree, and material group. The material group and creepage
for the ADuM4135 isolator are presented in Table 8.
10
1
Insulation Wear Out
0.1
0.01
0.001
1K
10K
100K
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
13082-029
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
100
Testing and modeling have shown that the primary driver of
long-term degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as:
dc stress, which causes very little wear out because there is no
displacement current, and an ac component time varying
voltage stress, which causes wear out.
Figure 25. Maximum Allowable External Magnetic Flux Density
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
10K
100K
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
13082-030
MAXIMUM ALLOWABLE CURRENT (kA)
1k
0.01
1K
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. It is the working voltage
applicable to tracking that is specified in most standards.
Figure 26. Maximum Allowable Current for Various
Current-to-ADuM4135 Spacings
The ratings in certification documents are usually based on 60 Hz
sinusoidal stress because this stress reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as
shown in Equation 2. For insulation wear out with the polyimide
materials used in this product, the ac rms voltage determines
the product lifetime.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation, as well as on the
materials and material interfaces.
Two types of insulation degradation are of primary interest:
breakdown along surfaces exposed to air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
VRMS = VAC RMS2 + VDC 2
(1)
VAC RMS = VRMS 2 − VDC 2
(2)
or
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
Rev. A | Page 15 of 17
ADuM4135
Data Sheet
Calculation and Use of Parameters Example
This working voltage of 466 V rms is used together with the
material group and pollution degree when looking up the
creepage required by a system standard.
The following is an example that frequently arises in power
conversion applications. Assume that the line voltage on one
side of the isolation is 240 V ac rms, and a 400 V dc bus voltage
is present on the other side of the isolation barrier. The isolator
material is polyimide. To establish the critical voltages in
determining the creepage clearance and lifetime of a device,
see Figure 27 and the following equations.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. The ac rms voltage can be obtained
from Equation 2.
VAC RMS = VRMS 2 − VDC 2
VAC RMS = 240 V rms
VAC RMS
VRMS
VDC
Note that the dc working voltage limit in Table 8 is set by the
creepage of the package as specified in IEC 60664-1. This value
may differ for specific system level standards.
TIME
Figure 27. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
TYPICAL APPLICATION
VRMS = VAC RMS 2 + VDC 2
The typical application schematic in Figure 28 shows a bipolar
setup with an additional RBLANK resistor to increase charging
current of the blanking capacitor for desaturation detection.
The RBLANK resistor is optional. If unipolar operation is desired,
the VSS2 supply can be removed, and VSS2 must be tied to GND2.
VRMS = 240 2 + 400 2
VRMS = 466 V rms
ADuM4135
1
VDD1
1
1
1
VSS1
2
VI+
3
VI–
4
READY
VDD2 13
5
FAULT
VOUT_OFF 12
6
RESET
7
VDD1
DESAT
10
8
VSS1
VSS2
9
VSS2 16
GATE_SENSE
15
2
IC
RG_ON
VOUT_ON 14
VDD2
GND 2 11
VSS2
+
VCE
–
RG_OFF
RBLANK
CBLANK
+ VRDESAT –
+ Vf –
RDESAT
2
NOTES
1. GROUNDS ON PRIMARY AND SECONDARY SIDE ARE
ISOLATED FROM EACH OTHER.
Figure 28. Typical Application Schematic
Rev. A | Page 16 of 17
13082-032
VPEAK
In this case, ac rms voltage is simply the line voltage of 240 V rms.
This calculation is more relevant when the waveform is not
sinusoidal. The value of the ac waveform is compared to the
limits for working voltage in Table 8 for expected lifetime, less
than a 60 Hz sine wave, and it is well within the limit for a
20 year service life.
13082-031
ISOLATION VOLTAGE
VAC RMS = 466 2 − 400 2
Data Sheet
ADuM4135
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
1
Figure 29. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1
ADuM4135BRWZ
ADuM4135BRWZ-RL
EVAL-ADuM4135EBZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W], 13” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13082-0-9/15(A)
Rev. A | Page 17 of 17
Package Option
RW-16
RW-16