512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Features DDR2 SDRAM VLP Mini-RDIMM MT9HVF6472(P)K – 512MB MT9HVF12872(P)K – 1GB For component data sheets, refer to Micron’s Web site: www.micron.com Features Figure 1: • 244-pin, very low profile mini registered dual in-line memory module (VLP Mini-RDIMM) • Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300, or PC2-6400 • 512MB (64 Meg x 72) or 1GB (128 Meg x 72) • Supports ECC error detection and correction • VDD = VDDQ = +1.8V • VDDSPD = +1.7V to +3.6V • JEDEC-standard 1.8V I/O (SSTL_18-compatible) • Differential data strobe (DQS, DQS#) option • 4n-bit prefetch architecture • Multiple internal device banks for concurrent operation • Supports duplicate output strobe (RDQS/RDQS#) • Programmable CAS# latency (CL) • Posted CAS# additive latency (AL) • WRITE latency = READ latency - 1 tCK • Programmable burst lengths: 4 or 8 • Adjustable data-output drive strength • 64ms, 8,192-cycle refresh • On-die termination (ODT) • Serial presence-detect (SPD) with EEPROM • Gold edge contacts • Single rank 244-Pin VLP Mini-RDIMM PCB height: 18.2mm (0.72in) Options Marking • Parity • Operating temperature1 – Commercial (0°C ≤ TA ≤ +70°C) – Industrial (–40°C ≤ TA ≤ +85°C) • Package – 244-pin DIMM (Pb-free) • Frequency/CAS latency2 – 2.5ns @ CL = 5 (DDR2-800) – 2.5ns @ CL = 6 (DDR2-800) – 3ns @ CL = 5 (DDR2-667) – 3.75ns @ CL = 4 (DDR2-533) – 5.0ns @ CL = 3 (DDR2-400) • PCB height – 18.2mm (0.72in) P None I Y -80E -800 -667 -53E -40E Notes: 1. Contact Micron for industrial temperature module offerings. 2. CL = CAS (READ) latency; registered mode will add one clock cycle to CL. Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 6 CL = 5 CL = 4 CL = 3 (ns) tRP (ns) tRC (ns) -80E -800 -667 -53E -40E PC2-6400 PC2-6400 PC2-5300 PC2-4200 PC2-3200 – 800 – – – 800 667 667 – – 533 53E 533 533 400 – – 400 400 400 12.5 15 15 15 15 12.5 15 15 15 15 55 55 55 55 55 PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN 1 tRCD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Features Table 2: Addressing Refresh count Row address Device bank address Device page size per bank Device configuration Column address Module rank address Table 3: 512MB 1GB 8K 16K (A0–A13) 4 (BA0, BA1) 1KB 512Mb (64 Meg x 8) 1K (A0–A9) 1 (S0#) 8K 16K (A0–A13) 8 (BA0–BA2) 1KB 1Gb (128 Meg x 8) 1K (A0–A9) 1 (S0#) Part Numbers and Timing Parameters – 512MB Modules Base device: MT47H64M8,1 512Mb DDR2 SDRAM Part Number2 MT9HVF6472(P)KY-80E__ MT9HVF6472(P)KY-800__ MT9HVF6472(P)KY-667__ MT9HVF6472(P)KY-53E__ MT9HVF6472(P)KY-40E__ Table 4: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 512MB 512MB 512MB 512MB 512MB 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 6.4 GB/s 6.4 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 2.5ns/800 MT/s 2.5ns/800 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 Part Numbers and Timing Parameters – 1GB Modules Base device: MT47H128M8,1 1Gb DDR2 SDRAM Part Number2 MT9HVF12872(P)KY-80E__ MT9HVF12872(P)KY-800__ MT9HVF12872(P)KY-667__ MT9HVF12872(P)KY-53E__ MT9HVF12872(P)KY-40E__ Notes: PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) 1GB 1GB 1GB 1GB 1GB 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 6.4 GB/s 6.4 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 2.5ns/800 MT/s 2.5ns/800 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9HVF12872KY-40EE1. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 244-Pin VLP Mini-RDIMM Front 244-Pin VLP Mini-RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 32 VSS 63 VDDQ 94 DQS5# 123 VSS 154 2 3 4 VSS DQ0 DQ1 33 34 35 DQ24 DQ25 VSS 64 65 66 A2 VDD VSS 95 96 97 DQS5 VSS DQ42 124 125 126 DQ4 DQ5 VSS 155 156 157 5 VSS 36 DQS3# 67 VSS 98 DQ43 127 6 DQS0# 37 DQS3 683 99 VSS 128 7 8 9 10 11 12 DQS0 VSS DQ2 DQ3 VSS DQ8 38 39 40 41 42 43 VSS DQ26 DQ27 VSS CB0 CB1 69 70 71 72 73 74 NC/ PAR_IN VDD A10 BA0 VDD WE# VDDQ 100 101 102 103 104 105 DQ48 DQ49 VSS SA2 NC Vss 13 DQ9 44 VSS 75 CAS# 106 14 VSS 45 DQS8# 76 VDDQ 15 DQS1# 46 DQS8 77 16 17 18 19 20 21 DQS1 VSS RESET# NC VSS DQ10 47 48 49 50 51 52 VSS CB2 CB3 VSS NC VDDQ 22 DQ11 53 23 VSS 54 24 25 DQ16 DQ17 26 VSS 27 28 29 30 31 185 A3 186 187 188 A1 VDD CK0 189 CK0# 220 VSS 190 VDD 221 DQ52 129 130 131 132 133 134 DM0/ RDQS0 NC/ RDQS0# VSS DQ6 DQ7 VSS DQ12 DQ13 DQ29 VSS DM3/ RDQS3 158 NC/ RDQS3# 159 VSS NC/ RDQS5# 217 VSS 218 DQ46 219 DQ47 160 161 162 163 164 165 191 192 193 194 195 196 A0 BA1 VDD RAS# VDDQ S0# 222 223 224 225 226 227 DQS6# 135 VSS 166 VDDQ 107 DQS6 136 ODT0 NC 108 VSS 137 A13 230 78 79 80 81 82 83 NC VDDQ NC VSS DQ32 DQ33 109 110 111 112 113 114 DQ50 DQ51 VSS DQ56 DQ57 VSS 138 139 140 141 142 143 DM1/ RDQS1 NC/ RDQS1# VSS RFU RFU VSS DQ14 DQ15 DM8/ 197 RDQS8 167 NC/ 198 RDQS8# 168 VSS 199 169 170 171 172 173 174 CB6 CB7 VSS NC VDDQ NC 200 201 202 203 204 205 VDD NC VSS DQ36 DQ37 VSS 231 232 233 234 235 236 CKE0 84 VSS 115 DQS7# 144 VSS 175 VDD 206 VDD 85 DQS4# 116 DQS7 145 DQ20 176 NC 551 NC/BA2 562 NC/ ERR_OUT 57 VDDQ 86 87 DQS4 VSS 117 118 VSS DQ58 146 147 DQ21 VSS 177 178 NC VDDQ 88 DQ34 119 DQ59 148 179 A12 210 DQ39 241 VSS DQS2# 58 A11 89 DQ35 120 VSS 149 180 A9 211 VSS 242 SDA DQS2 VSS DQ18 DQ19 59 60 61 62 A7 VDD A5 A4 90 91 92 93 VSS DQ40 DQ41 VSS 121 122 SA0 SA1 150 151 152 153 DM2/ RDQS2 NC/ RDQS2# VSS DQ22 DQ23 VSS 181 182 183 184 VDD A8 A6 VDDQ 212 213 214 215 DQ44 DQ45 VSS DM5/ RDQS5 243 244 SCL VDDSPD Notes: PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN DQ28 DQ30 DQ31 VSS CB4 CB5 VSS 216 DQ53 VSS RFU RFU VSS DM6/ RDQS6 228 NC/ RDQS#6 229 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/ RDQS7 237 NC/ RDQS7# 238 VSS DM4/ RDQS4 207 NC/ RDQS4# 208 VSS 239 209 DQ38 240 DQ62 DQ63 1. Pin 55 is NC for 512MB, BA2 for 1GB. 2. Pin 56 is NC for non-parity and ERR_OUT for parity. 3. Pin 68 is NC for non-parity and PAR_IN for parity. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type Description ODT0 Input (SSTL_18) CK0, CK0# Input (SSTL_18) CKE0 Input (SSTL_18) Input (SSTL_18) On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD MODE (LM) command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LM command. S0# RAS#, CAS#, WE# BA0, BA1 (512MB) BA0–BA2 (1GB) A0–A13 PAR_IN Input (SSTL_18) Input (SSTL_18) Input (SSTL_18) DQS0–DQS8, DQS0#–DQS8# Input (SSTL_18) Input (SSTL_18) Input (SSTL_18) Input (SSTL_18) I/O (SSTL_18) I/O (SSTL_18) DM0–DM8 (RDQS0–RDQS8) I/O (SSTL_18) CB0–CB7 I/O (SSTL_18) I/O (SSTL_18) Output (open drain) Supply SCL SA0–SA2 RESET# DQ0–DQ63 SDA ERR_OUT VDD/VDDQ PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LM command. Parity bit for the address and control bus. Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-detect address inputs: These pins are used to configure the presence-detect device. Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQs are High-Z. Data input/output: Bidirectional data bus. Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LM command. DQS9#–DQS17# are only used when RDQS# is enabled via the LM command. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. If RDQS is enabled, DQS0#–DQS8# are used only during the READ command. If RDQS is disabled, RDQS0–RDQS8 become DM0–DM8 and RDQS0#–RDQS8# are not used. Check bits. Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Parity error found on the address and control bus. Power supply: 1.8V ±0.1V. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions (continued) Symbol Type VREF VSS VDDSPD NC RFU Supply Supply Supply – – PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN Description SSTL_18 reference voltage. Ground. Serial EEPROM positive power supply: +1.7V to +3.6V. No connect: These pins should be left unconnected. Reserved for future use. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram RS0# DQS4 DQS4# DM4/DQS13 NC/DQS13# DQS0 DQS0# DM0/DQS9 NC/DQS9# DM/ RDQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U1 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U6 DQS5 DQS5# DM5/DQS14 NC/DQS14# DQS1 DQS1# DM1/DQS10 NC/DQS10# DM/ RDQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# DM/ RDQS U12 NU/ CS# DQS DQS# RDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS2 DQS2# DM2/DQS11 NC/DQS11# U9 DQS6 DQS6# DM6/DQS15 NC/DQS15# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 NU/ CS# DQS DQS# RDQS# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2 NU/ CS# DQS DQS# RDQS# U7 DQS7 DQS7# DM7/DQS16 NC/DQS16# DQS3 DQS3# DM3/DQS12 NC/DQS12# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U3 DQS8 DQS8# DM8/DQS17 NC/DQS17# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 NU/ CS# DQS DQS# RDQS# CK0 CK0# U8 DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM Register PLL U11 RESET# SCL R E G I S T E R NU/ CS# DQS DQS# RDQS# U5 U10 SPD EEPROM WP A0 U4 S0# BA0–BA1/BA2 A0–A15 RAS# CAS# WE# CKE0 ODT0 PAR_IN DM/ RDQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 RS0#: DDR2 SDRAM RBA0–RBA1/RBA2: DDR2 SDRAM RA0–RA13: DDR2 SDRAM RRAS#: DDR2 SDRAM RCAS#: DDR2 SDRAM RWE#: DDR2 SDRAM RCKE0: DDR2 SDRAM RODT0: DDR2 SDRAM ERR_OUT A1 SDA A2 Vss SA0 SA1 SA2 VDDSPD SPD EEPROM VDD/ VDDQ DDR2 SDRAM VREF DDR2 SDRAM VSS DDR2 SDRAM RESET# PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM General Description General Description The MT9HVF6472(P)K and MT9HVF12872(P)K DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 512MB and 1GB memory modules organized in a x72 configuration. DDR2 SDRAM modules use internally configured 4-bank (512Mb) or 8-bank (1Gb) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Register and PLL Operation DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and re-drives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address, command, control, and clock signal loading by isolating DRAM from the system controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the module, permanently disabling hardware write protect. PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions above those indicated in each device’s data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Symbol VDD/VDDQ VIN, VOUT II IOZ IVREF TA TC1 Absolute Maximum Ratings Parameter Min Max Units VDD/VDDQ supply voltage relative to VSS Voltage on any pin relative to VSS Command/address Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under RAS#, CAS#, WE#, S#, test = 0V) CKE, ODT, BA CK, CK# DM Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = valid VREF level Module ambient operating temperature Commercial Industrial DDR2 SDRAM component case operating Commercial temperature2 Industrial –0.5 –0.5 –5 +2.3 +2.3 +5 V V µA –250 –5 –5 +250 +5 +5 µA –18 0 –40 0 –40 +18 +70 +85 +85 +95 µA °C °C °C °C Notes: 1. Refresh rate is required to double when 85°C < TC ≤ 95°C. 2. For further information, refer to technical note TN-00-08: Thermal Applications, available on Micron’s Web site. Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Operating Specifications Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades as shown in Table 8. Table 8: Module and Component Speed Grades Module Speed Grade Component Speed Grade -80E -800 -667 -53E -40E -25E -25 -3 -37E -5E PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM IDD Specifications IDD Specifications Table 9: IDD Specifications and Conditions – 512MB Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet Parameter/Condition Operating one bank active-precharge current: tCK = tCK (IDD), t RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address MR[12] = 0 bus inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), t RAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN 9 Symbol -80E -800 -667 -53E -40E Units IDD0 900 810 720 720 mA IDD1 1,035 945 855 810 mA IDD2P 63 63 63 63 mA IDD2Q 450 405 360 315 mA IDD2N 495 450 405 360 mA IDD3P 360 315 270 225 mA 108 108 108 108 mA IDD3N 630 585 495 405 mA IDD4W 1,755 1,530 1,260 1,035 mA IDD4R 1,845 1,620 1,305 1,035 mA IDD5 2,070 1,620 1,530 1,485 mA IDD6 63 63 63 63 mA IDD7 2,700 2,160 2,025 1,980 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM IDD Specifications Table 10: IDD Specifications and Conditions – 1GB Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet Parameter/Condition t t Operating one bank active-precharge current: CK = CK (IDD), t RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), t RAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), t RAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every t RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN 10 Symbol -80E800 -667 -53E -40E Units IDD0 810 765 630 630 mA IDD1 990 900 855 810 mA IDD2P 63 63 63 63 mA IDD2Q 450 360 360 315 mA IDD2N 450 360 360 315 mA IDD3P 360 270 270 270 mA 90 90 90 90 mA IDD3N 540 495 405 360 mA IDD4W 1,440 1,215 1,125 945 mA IDD4R 1,440 1,215 1,125 945 mA IDD5 2,115 1,935 1,890 1,845 mA IDD6 63 63 63 63 mA IDD7 3,015 2,520 2,430 2,340 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Register and PLL Specifications Register and PLL Specifications Table 11: Register Specifications SSTU32865 device or equivalent JESD82-19 Parameter Symbol Pins Condition Min Max Units DC high-level input voltage VIH(DC) SSTL_18 VREF(DC) + 125 VDDQ + 250 mV DC low-level input voltage VIL(DC) SSTL_18 0 VREF(DC) - 125 mV AC high-level input voltage VIH(AC) SSTL_18 VREF(DC) + 250 VDD mV AC low-level input voltage VIL(AC) Address, control, command Address, control, command Address, control, command Address, control, command Parity output Parity output All pins All pins All pins SSTL_18 0 VREF(DC) - 250 mV 1.2 – –5 – – – 0.5 +5 200 80 V V µA µA mA – Varies by manufacturer µA – Varies by manufacturer µA 2.5 3.5 pF – Varies by manufacturer pF Output high voltage Output low voltage Input current Static standby Static operating VOH VOL II IDD IDD Dynamic operating (clock tree) IDDD Dynamic operating (per each input) IDDD Input capacitance (per device, per pin) Input capacitance (per device, per pin) CI Notes: PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN CI LVCMOS LVCMOS VI = VDDQ or VSSQ RESET# = VSSQ (IO = 0) RESET# = VSSQ; VI = VIH(AC) or VIL(DC) IO = 0 n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle; One data input switching at tCK/2, 50% duty cycle All inputs VI = VREF ±250mV; except RESET# VDDQ = 1.8V RESET# VI = VDDQ or VSSQ 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2 SDRAM registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC standard JESD82. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Register and PLL Specifications Table 12: PLL Specifications CU877 device or equivalent JESD82-8.01 Parameter Symbol Pins Condition Min Max Units DC high-level input voltage DC low-level input voltage Input voltage (limits) VIH RESET# LVCMOS 0.65 × VDD – V VIL RESET# LVCMOS – 0.35 × VDD V VIN –0.3 VDDQ + 0.3 V DC high-level input voltage DC low-level input voltage Input differential-pair cross voltage Input differential voltage Input differential voltage Input current VIH RESET#, CK, CK# CK, CK# Differential input 0.65 × VDD – V VIL CK, CK# Differential input – 0.35 × VDD V VIX CK, CK# Differential input (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 V VID(DC) CK, CK# Differential input 0.3 VDDQ + 0.4 V VID(AC) CK, CK# Differential input 0.6 VDDQ + 0.4 V II RESET# CK, CK# VI = VDDQ or VSSQ VI = VDDQ or VSSQ RESET# = VSSQ; VI = VIH(AC) or VIL(DC) CK = CK# = LOW CK, CK# = 270 MHz, all outputs open (not connected to PCB) VI = VDDQ or VSSQ –10 –250 100 10 250 – µA µA µA – – 500 300 µA mA 2 3 pF Output current IODL Static supply current Dynamic supply IDDLD IDD n/a CIN Each input Input capacitance Table 13: PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Stabilization time Input clock slew rate SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (–3dB from unity gain) Notes: PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN Symbol Min Max Units tL – 1.0 30 0.0 2.0 15 4 33 –0.50 – µs V/ns kHz % MHz tLS I 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information is available in JEDEC standard JESD82. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Register and PLL Specifications Table 14: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 1.7 VDDSPD × 0.7 –0.6 – 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 VDDSPD × 0.3 0.4 3 3 4 1 3 V V V V µA µA µA mA mA Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDDSPD Output leakage current: VOUT = GND to VDDSPD Standby current Power supply current, READ: SCL clock frequency = 100 kHz Power supply current, WRITE: SCL clock frequency = 100 kHz Table 15: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN Symbol Min Max Units Notes tAA 0.2 1.3 200 – 0 0.6 0.6 – 1.3 – – 100 0.6 0.6 – 0.9 – – 300 – – – 50 – 0.3 400 – – – 10 µs µs ns ns µs µs µs ns µs µs kHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT tSU:STA tSU:STO t WRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Register and PLL Specifications Table 16: Byte Serial Presence-Detect Matrix Description 0 1 2 3 4 5 Number of SPD bytes used by Micron Total number of bytes in SPD device Fundamental memory type Number of row addresses on assembly Number of column addresses on assembly DIMM height and module ranks 6 7 8 9 Module data width Reserved Module voltage interface levels SDRAM cycle time, tCK (CL = MAX value, see byte 18) 10 SDRAM access from clock, tAC (CL = MAX value, see byte 18) 11 Module configuration type 12 13 14 15 16 17 18 Refresh rate/type SDRAM device width (primary SDRAM) Error-checking SDRAM data width Reserved Burst lengths supported Number of banks on SDRAM device CAS latencies supported 19 20 Module thickness DDR2 DIMM type 21 22 SDRAM module attributes SDRAM device attributes: weak driver (01) and 50Ω ODT (03) SDRAM cycle time, tCK, MAX CL - 1 23 24 SDRAM access from CK, tAC, MAX CL - 1 25 SDRAM cycle time, tCK, MAX CL - 2 26 SDRAM access from CK, tAC, MAX CL - 2 PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN Entry (Version) 512MB 1GB 128 256 DDR2 SDRAM 14 10 18.2mm, single rank 72 0 SSTL 1.8V -80E/-800 -667 -53E -40E -80E/-800 -667 -53E -40E ECC ECC and parity 7.81µs/SELF 8 8 0 4, 8 4 or 8 -80E (5, 4) -800 (6, 5, 4) -667 (5, 4, 3) -53E/-40E (4, 3) 80 08 08 0E 0A 00 80 08 08 0E 0A 00 48 00 05 25 30 3D 50 40 45 50 60 02 06 82 08 08 00 0C 04 30 70 38 18 01 10 48 00 05 25 30 3D 50 40 45 50 60 02 06 82 08 08 00 0C 08 30 70 38 18 01 10 04 03 01 3D 30 50 40 45 50 60 00/3D 50 00 00/40 45 00 04 03 01 3D 30 50 40 45 50 60 00/3D 50 00 00/40 45 00 Registered Mini-RDIMM 1 PLL, 2 Reg -80E/-800/-667 -53E/-40E -80E/-667 -800 -53E/-40E -80E/-800 -667 -53E -40E -80E/-800 -667 -53E/-40E -80E/-800 -667 -53E/-40E 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Register and PLL Specifications Table 16: Byte Serial Presence-Detect Matrix (continued) Description tRP 27 MIN row precharge time, 28 29 MIN row active-to-row active, tRRD MIN RAS#-to-CAS# delay, tRCD 30 MIN active-to-precharge time, tRAS 31 32 Module rank density Address and command setup time, tISb 33 Address and command hold time, tIHb 34 Data/data mask input setup time, tDSb 35 Data/data mask input hold time, tDHb 36 37 Write recovery time, tWR WRITE-to-READ command delay, tWTR 38 39 40 READ-to-PRECHARGE command delay, tRTP Memory analysis probe Extension for bytes 41 and 42 41 MIN active-to-active/refresh time, tRC1 42 MIN AUTO REFRESH-to-ACTIVE/AUTO REFRESH command period, tRFC SDRAM device MAX cycle time, tCK (MAX) SDRAM device MAX DQS–DQ skew time, tDQSQ 43 44 45 46 47–61 62 SDRAM device MAX read data hold skew factor, tQHS PLL relock time Optional features, not supported SPD revision PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN Entry (Version) 512MB 1GB -80E -800/-667/-53E/-40E 32 3C 1E 32 3C 2D 28 80 17 20 25 35 25 27 37 47 05 10 15 12 17 22 27 3C 1E 28 1E 1E 32 3C 1E 32 3C 2D 28 01 17 20 25 35 25 27 37 47 05 10 15 12 17 22 27 3C 1E 28 1E 1E 00 30 00 39 3C 37 69 00 36 06 39 3C 37 7F 80 80 14 18 1E 23 1E 22 28 2D 0F 00 12 14 18 1E 23 1E 22 28 2D 0F 00 12 -80E -800/-667/-53E/-40E -80E/-800/-667/-53E -40E 512MB, 1GB -80E/-800 -667 -53E -40E -80E/-800 -667 -53E -40E -80E/-800 -667/-53E -40E -80E/-800 -667 -53E -40E -80E -800/-40E -667/-53E -80E -800/-667/-53E/-40E -80E -800/-667/-53E -40E -80E/-800 -667 -53E -40E -80E/-800 -667 -53E -40E Release 1.2 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Register and PLL Specifications Table 16: Byte 63 64 65–71 72 73–90 91 92 93 94 95–98 99–127 128–255 Serial Presence-Detect Matrix (continued) Description Checksum for bytes 0–62 ECC/ECC and parity Manufacturer’s JEDEC ID code Manufacturer’s JEDEC ID code Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Reserved for manufacturer-specific data Reserved for customer-specific data Notes: PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN Entry (Version) 512MB 1GB -80E -800 -667 -53E -40E MICRON (continued) 1–12 – 1–9 0 – – – 62/66 03/07 1E/22 C9/CD 30/34 2C FF 01–0C Variable data 01–09 00 Variable data Variable data Variable data 00 FF 03/07 A4/A8 BF/C3 6A/6E D1/D5 2C FF 01–0C Variable data 01–09 00 Variable data Variable data Variable data 00 FF 1. The tRC SPD values shown are JEDEC DDR2 device specification values. The actual Micron DDR2 device specification is tRC = 55ns for all speed grades. 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved. 512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Module Dimensions Module Dimensions Figure 3: 244-Pin DDR2 VLP Mini-RDIMM Front view 3.80 (0.150) MAX 82.127 (3.233) 81.873 (3.223) 1.00 (0.039) R X2 U1 U2 U4 U3 U6 U5 1.80 (0.071) D X2 6.00 (0.236) TYP 1.00 (0.039) TYP 2.00 (0.079) TYP 0.60 (0.024) PIN 1 TYP U7 18.30 (0.720) 18.10 (0.713) 10.00 (0.394) TYP 0.50 (0.02) R 0.45 (0.018) TYP PIN 122 1.10 (0.043) 0.90 (0.035) 42.90 (1.689) TYP 78.00 (3.071) TYP Back view U10 U8 U9 U11 U12 3.30 (0.130) TYP 3.60 (0.142) TYP PIN 123 PIN 244 33.60 (1.323) TYP 38.40 (1.512) TYP 3.20 (0.126) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for complete design dimensions. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef81c9620b/Source: 09005aef81c961ec HVF9C64_128x72K.fm - Rev. C 3/07 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2005 Micron Technology, Inc. All rights reserved.